CN107331669B - Manufacturing method of TFT (thin film transistor) driving back plate - Google Patents
Manufacturing method of TFT (thin film transistor) driving back plate Download PDFInfo
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- CN107331669B CN107331669B CN201710465756.7A CN201710465756A CN107331669B CN 107331669 B CN107331669 B CN 107331669B CN 201710465756 A CN201710465756 A CN 201710465756A CN 107331669 B CN107331669 B CN 107331669B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 239000010409 thin film Substances 0.000 title description 11
- 239000010410 layer Substances 0.000 claims abstract description 279
- 239000011229 interlayer Substances 0.000 claims abstract description 36
- 229910052751 metal Inorganic materials 0.000 claims description 60
- 239000002184 metal Substances 0.000 claims description 60
- 238000000034 method Methods 0.000 claims description 34
- 238000000059 patterning Methods 0.000 claims description 24
- 239000003990 capacitor Substances 0.000 claims description 22
- 238000000151 deposition Methods 0.000 claims description 22
- 229910044991 metal oxide Inorganic materials 0.000 claims description 21
- 150000004706 metal oxides Chemical class 0.000 claims description 21
- 238000002161 passivation Methods 0.000 claims description 19
- 230000008569 process Effects 0.000 claims description 18
- 239000004065 semiconductor Substances 0.000 claims description 16
- 239000000758 substrate Substances 0.000 claims description 14
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 13
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 13
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 13
- 239000010949 copper Substances 0.000 claims description 10
- 239000010936 titanium Substances 0.000 claims description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 9
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 9
- 229910052782 aluminium Inorganic materials 0.000 claims description 9
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 9
- 229910052802 copper Inorganic materials 0.000 claims description 9
- 229910052719 titanium Inorganic materials 0.000 claims description 9
- 229910001182 Mo alloy Inorganic materials 0.000 claims description 8
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 6
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 6
- 229910052733 gallium Inorganic materials 0.000 claims description 6
- 229910052738 indium Inorganic materials 0.000 claims description 6
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 6
- 150000002500 ions Chemical class 0.000 claims description 4
- HRHKULZDDYWVBE-UHFFFAOYSA-N indium;oxozinc;tin Chemical compound [In].[Sn].[Zn]=O HRHKULZDDYWVBE-UHFFFAOYSA-N 0.000 claims description 3
- KYKLWYKWCAYAJY-UHFFFAOYSA-N oxotin;zinc Chemical compound [Zn].[Sn]=O KYKLWYKWCAYAJY-UHFFFAOYSA-N 0.000 claims description 3
- 239000011787 zinc oxide Substances 0.000 claims description 3
- 230000004888 barrier function Effects 0.000 claims description 2
- 238000002360 preparation method Methods 0.000 claims description 2
- 238000003860 storage Methods 0.000 description 26
- 238000010586 diagram Methods 0.000 description 8
- 238000005530 etching Methods 0.000 description 7
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 3
- 239000002253 acid Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 230000001678 irradiating effect Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 230000005856 abnormality Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1237—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a different composition, shape, layout or thickness of the gate insulator in different devices
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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Abstract
The invention provides a manufacturing method of TFT driving back plates, which comprises the steps of firstly forming a capacitance increasing groove and a through hole above a shielding layer electrode block on a buffer layer, forming a gate layer electrode block above the capacitance increasing groove, then forming a second through hole communicated with a through hole on an interlayer insulating layer, and enabling a subsequent signal connecting block to be in contact with the shielding layer electrode block through a through hole and the second through hole.
Description
Technical Field
The invention relates to the technical field of display, in particular to a manufacturing method of TFT driving back plates.
Background
Thin Film Transistors (TFTs) are the main driving elements in Liquid Crystal Displays (LCDs) and Active Matrix Organic electroluminescent displays (AMOLEDs), and are directly related to the development of high performance flat panel displays.
The thin film transistor has various structures, and the materials for preparing the active layer of the thin film transistor with the corresponding structures are various, wherein the metal oxide thin film transistor (metal oxide TFT) has high field effect mobility (more than or equal to 10 cm)2V · s), simple preparation process, good uniformity of large-area deposition, fast response speed, high transmittance in visible light range, etc., and is considered as the most potential backplane technology for the development of displays towards large size and flexibility.
Since the metal oxide thin film is very sensitive to acid, even weak acid can rapidly corrode the oxide semiconductor, and meanwhile, the metal oxide semiconductor layer in the TFT device is usually very thin, is between 30-50nm, even in hydrofluoric acid (HF) diluted by 500:1, it only needs several seconds to be etched, and most metals need to be etched under strong acid and the etching rate is slow, therefore, for the metal oxide thin film transistor with the bottom gate structure, when the metal layer is etched on the metal oxide semiconductor to form the source electrode and the drain electrode, the metal oxide semiconductor itself is easily damaged, so the top gate (toprate) metal oxide thin film transistor structure becomes the main development direction at present.
As shown in fig. 1, the TFT driving backplane of the top gate type metal oxide in the prior art mainly includes a substrate 100, a Buffer layer (Buffer)200, an active layer 300, a gate insulating layer 450, a gate metal layer 400, an interlayer Insulating Layer (ILD) 500, a source electrode 610, a drain electrode 620, a passivation layer (PV)700, and a pixel electrode 800, and further , in order to avoid light from irradiating the active layer 300 to affect the performance of the thin film transistor, in the TFT driving backplane, a metal shielding layer 900 is further disposed between the Buffer layer 200 and the substrate 100 to avoid light from irradiating the active layer 300.
As the development of pixel technology requires, how to increase the storage capacitance becomes an important concern for , in the prior art, in order to increase the storage capacitance, as shown in fig. 1, in the driving backplane in which the thin film transistor is in a top gate type structure, the storage capacitance is increased by forming the storage capacitance with the metal shielding layer 900 located below the buffer layer 200 and the subsequent gate metal layer 400. specifically, in order to apply a signal to the metal shielding layer 900, the metal shielding layer 900 needs to be electrically connected with the common electrode and the like located subsequently through the connection portion 550 located on the interlayer insulating layer 500, wherein the connection portion 550 needs to be electrically connected with the metal shielding layer 900 through the via 250 penetrating through the buffer layer 200 and the interlayer insulating layer 500, so that the buffer layer 200 and the interlayer insulating layer 500 need to be etched to be opened, since the depth of the second via 580 for connecting the active layer 300 with the source 610 and drain 620 is smaller than that of the via 250 above the active layer 300, if the contact between the buffer layer 200 and the interlayer insulating layer 500 is selected, the contact area of the source 610 and the drain 620 is etched to be opened, so that the buffer layer 300 is too thick, the performance of the storage capacitance is generally reduced, and the storage capacitance of the storage capacitor 200 is also often damaged.
Disclosure of Invention
The invention aims to provide a manufacturing method of TFT driving back plates, which can avoid electrical abnormity of devices caused by openings formed by a buffer layer and an interlayer insulating layer , effectively improve the charge storage capacity of a storage capacitor, reduce the occupied area of the storage capacitor and increase the aperture opening ratio.
In order to achieve the above object, the present invention provides a method for manufacturing TFT driving back plates, comprising the following steps:
step S1, providing a substrate, dividing a TFT forming area and a capacitor forming area which are arranged in parallel on the substrate, depositing a metal shielding layer on the substrate, and patterning the metal shielding layer to obtain a metal shading block and a shielding layer electrode block which are respectively positioned above the TFT forming area and the capacitor forming area;
step S2, sequentially depositing a buffer layer and a metal oxide semiconductor layer on the metal shading block, the shielding layer electrode block and the substrate, and patterning the metal oxide semiconductor layer to obtain an active layer correspondingly positioned above the metal shading block;
step S3, patterning the buffer layer, and forming a capacitance increasing groove and a th through hole which are spaced above the shielding layer electrode block;
step S4, sequentially depositing an insulating layer and a gate metal layer on the buffer layer and the active layer, patterning the gate metal layer and the insulating layer to obtain a gate electrode located above the TFT formation region and a gate electrode block correspondingly located above the capacitance increasing trench from the gate metal layer, and obtaining a gate insulating layer correspondingly located below the gate electrode and the gate electrode block from the insulating layer;
step S5, depositing an interlayer insulating layer on the gate, the active layer and the buffer layer, patterning the interlayer insulating layer, and forming a second via hole corresponding to the position above the th via hole and communicating with the th via hole, and a third via hole and a fourth via hole corresponding to the positions above two sides of the active layer, respectively, on the interlayer insulating layer;
and S6, depositing and forming a source and drain metal layer on the interlayer insulating layer, and patterning the source and drain metal layer to obtain a signal connecting block correspondingly positioned above the shielding layer electrode block and a source electrode and a drain electrode respectively positioned above the TFT forming area, wherein the signal connecting block is contacted with the shielding layer electrode block through the through hole and the second through hole, and the source electrode and the drain electrode are contacted with two sides of the active layer through the third through hole and the fourth through hole respectively.
In the step S1, the thickness of the deposited metal shielding layer is
The material of the metal shielding layer is or more alloys of molybdenum, aluminum, copper and titanium.
In the step S2, the thickness of the deposited buffer layer isThe buffer layer is a silicon oxide layer, a silicon nitride layer or a combination of the two.
In the step S2, the thickness of the metal oxide semiconductor layer is 
The metal oxide semiconductor layer is made of indium gallium zinc oxide, indium zinc tin oxide or indium gallium zinc tin oxide.
The step S4 further includes ion doping the active layer by a plasma doping process using the gate and the gate insulating layer as barrier layers, so that the conductivity of the region of the active layer not covered by the gate and the gate insulating layer is enhanced.
In step S4, the insulation layer is deposited to a thickness of
The insulating layer is a silicon oxide layer, a silicon nitride layer or a combination of the silicon oxide layer and the silicon nitride layer; the deposited gate metal layer has a thickness of 
The material of the gate metal is or more alloys of molybdenum, aluminum, copper and titanium.
In the step S5, the interlayer insulating layer is deposited to a thickness ofThe interlayer insulating layer is a silicon oxide layer, a silicon nitride layer or a combination of the two.
In step S6, the thickness of the deposited source/drain metal layer is set to
The source and drain electrode metal layer is made of or more alloys of molybdenum, aluminum, copper and titanium.
The manufacturing method of the TFT driving back plate further includes step S7, depositing a passivation layer on the interlayer insulating layer, the signal connection block, the source electrode and the drain electrode, patterning the passivation layer, forming a fifth via hole on the passivation layer corresponding to the upper portion of the drain electrode, depositing and patterning the passivation layer to form a pixel electrode, and the pixel electrode contacts the drain electrode through the fifth via hole.
In step S7, the passivation layer is deposited to a thickness of
The passivation layer is a silicon oxide layer, a silicon nitride layer or a combination of the two.
The manufacturing method of TFT driving back plates has the advantages that a capacitance increasing groove and a through hole are formed above a shielding layer electrode block on a buffer layer, a grid layer electrode block is formed above the capacitance increasing groove, a second through hole communicated with a through hole is formed on an interlayer insulating layer, a subsequent signal connecting block is contacted with the shielding layer electrode block through the through hole and the second through hole, the through hole and the second through hole are formed on the buffer layer and the interlayer insulating layer in sequence, electrical abnormity of a device caused by opening holes in the buffer layer and the interlayer insulating layer is avoided, and compared with the prior art, the thickness of a dielectric layer of a storage capacitor formed by the grid layer electrode block and the shielding layer electrode block is reduced, so that the charge storage capacity of the storage capacitor is effectively improved, the area occupied by the storage capacitor is correspondingly reduced, and the aperture opening ratio of the TFT driving back plate is increased.
Drawings
The technical solution and other advantages of the present invention will become apparent from the following detailed description of specific embodiments of the present invention, which is to be read in connection with the accompanying drawings.
In the drawings, there is shown in the drawings,
FIG. 1 is a schematic structural diagram of a conventional TFT driving backplane;
FIG. 2 is a schematic flow chart of a method for fabricating a TFT driving backplane according to the present invention;
FIG. 3 is a schematic diagram of step S1 of the method for manufacturing a TFT driving backplane according to the present invention;
FIGS. 4-5 are schematic diagrams of step S2 of the method for fabricating a TFT driving backplane according to the present invention;
FIG. 6 is a schematic diagram of step S3 of the method for fabricating a TFT driving backplane according to the present invention;
FIGS. 7-9 are schematic diagrams of step S4 of the method for fabricating a TFT driving backplane according to the present invention;
FIGS. 10-11 are schematic diagrams of step S5 of the method for fabricating a TFT driving backplane according to the present invention;
FIGS. 12-13 are schematic diagrams of step S6 of the method for fabricating a TFT driving backplane according to the present invention;
fig. 14-15 are schematic diagrams of step S7 in an embodiment of a method for manufacturing a TFT driving back plate according to the present invention.
Detailed Description
To further explain the technical means and effects of the present invention, the following detailed description is given with reference to the preferred embodiments of the present invention and the accompanying drawings.
Referring to fig. 2, the present invention provides a method for manufacturing TFT driving backplates, which comprises the following steps:
step S1, as shown in fig. 3, providing a substrate 10, dividing the substrate 10 into a TFT forming region and a capacitor forming region which are arranged in parallel, depositing a metal shielding layer on the substrate 10, and patterning the metal shielding layer by using a yellow light process and an etching process in sequence to obtain a metal light shielding block 101 and a shielding layer electrode block 102 which are respectively located above the TFT forming region and the capacitor forming region.
Specifically, in step S1, the thickness of the deposited metal shielding layer is 
The metal shielding layer is made of or more alloys of molybdenum (Mo), aluminum (Al), copper (Cu) and titanium (Ti).
Step S2, as shown in fig. 4-5, sequentially depositing a buffer layer 20 and a metal oxide semiconductor layer 30 on the metal light shielding block 101, the shielding layer electrode block 102 and the substrate 10, and sequentially performing a yellow light process and an etching process to pattern the metal oxide semiconductor layer 30 to obtain an active layer 35 correspondingly located above the metal light shielding block 101.
Specifically, in step S2, the buffer layer 20 is deposited to have a thickness of
The buffer layer 20 is a silicon oxide (SiOx) layer, a silicon nitride (SiNx) layer, or a combination thereof.
Specifically, in step S2, the thickness of the metal oxide semiconductor layer 30 is
The metal oxide semiconductor layer 30 is made of Indium Gallium Zinc Oxide (IGZO), Indium Zinc Tin Oxide (IZTO), or Indium Gallium Zinc Tin Oxide (IGZTO).
Step S3, as shown in fig. 6, patterning the buffer layer 20 by using a photolithography process and an etching process in sequence, and forming a capacitance increasing groove 21 and a th via hole 22 spaced above the shielding layer electrode block 102.
Specifically, the capacitance increase groove 21 formed in step S3 corresponds to a region of the storage capacitor to be formed later, and the thickness of the dielectric layer between the two electrodes of the storage capacitor can be reduced by forming the capacitance increase groove 21 on the buffer layer 20, thereby improving the charge storage capacity of the storage capacitor.
Step S4, as shown in fig. 7-9, sequentially depositing an insulating layer 40 and a gate metal layer 50 on the buffer layer 20 and the active layer 35, patterning the gate metal layer 50 and the insulating layer 40, obtaining a gate electrode 55 located above the TFT formation region and a gate electrode block 52 located above the capacitance increasing trench 21 from the gate metal layer 50, and obtaining a gate insulating layer 45 located below the gate electrode 55 and the gate electrode block 52 from the insulating layer 40.
Specifically, the gate electrode block 52 formed in step S4 and the shielding layer electrode block 102 therebelow together form a storage capacitor, and since the capacitance increasing groove 21 is formed in the buffer layer 20 between the gate electrode block 52 and the shielding layer electrode block 102, compared with the prior art, the thickness of the dielectric layer in the storage capacitor is reduced, thereby increasing the charge storage capacity of the storage capacitor.
Specifically, the specific process of patterning the gate metal layer 50 and the insulating layer 40 in step S4 is to fabricate a patterned photoresist layer 58 on the gate metal layer 50 through exposure and development processes, etch the gate metal layer 50 by using the photoresist layer 58 as a shielding layer to obtain a gate 55 and a gate electrode block 52 with corresponding patterns, and then continuously etch the insulating layer 40 by using a self-alignment technique to obtain a gate insulating layer 45 with the same patterns as the gate 55 and the gate electrode block 52
Specifically, the step S4 further includes, with the gate electrode 55 and the gate insulating layer 45 as blocking layers, performing P-type ion doping or N-type ion doping on the active layer 35 through a plasma doping process to form a P-type TFT or an N-type TFT, respectively, so that the conductivity of a region of the active layer 35 not covered by the gate electrode 55 and the gate insulating layer 45 is enhanced to form a source/drain contact region, and the undoped region forms a channel region.
Specifically, in step S4, the insulating layer 40 is deposited to a thickness of 
The insulating layer 40 is a silicon oxide layer, a silicon nitride layer or a combination of the two; the gate metal layer 50 is deposited to a thickness ofThe material of the gate metal layer 50 is kinds of alloy among molybdenum, aluminum, copper and titanium.
Step S5, as shown in fig. 10 to 11, depositing an interlayer insulating layer 60 on the gate 55, the active layer 35 and the buffer layer 20, sequentially patterning the interlayer insulating layer 60 by a photolithography process and an etching process, forming a second via hole 62 corresponding to the via hole 22 and communicating with the via hole 22, and a third via hole 63 and a fourth via hole 64 corresponding to the upper portions of both sides of the active layer 35 on the interlayer insulating layer 60.
Specifically, in step S5, the interlayer insulating layer 60 is deposited to have a thickness of
The interlayer insulating layer 60 is a silicon oxide layer, a silicon nitride layer, or a combination of both.
Step S6, as shown in fig. 12 to 13, depositing a source/drain metal layer 70 on the interlayer insulating layer 60, sequentially performing a patterning process on the source/drain metal layer 70 by using a yellow light process and an etching process to obtain a signal connection block 72 correspondingly located above the shielding layer electrode block 102 and a source 73 and a drain 74 respectively located above the TFT formation region, where the signal connection block 72 is in contact with the shielding layer electrode block 102 through the via hole 22 and the second via hole 62, so that the signal connection block 72 inputs a signal to the shielding layer electrode block 102, and the source 73 and the drain 74 are in contact with both sides of the active layer 35 through the third via hole 63 and the fourth via hole 64, respectively.
Specifically, in the step S6, the thickness of the deposited source/drain metal layer 70 is as follows
The source-drain metal layer 70 is made of kinds of alloy of molybdenum, aluminum, copper and titanium.
Step S7, as shown in fig. 14 to 15, depositing a passivation layer 80 on the interlayer insulating layer 60, the signal connection block 72, the source electrode 73, and the drain electrode 74, patterning the passivation layer 80 by a photolithography process and an etching process in sequence, forming a fifth via hole 85 on the passivation layer 80, the fifth via hole corresponding to the upper portion of the drain electrode 74, depositing and patterning a pixel electrode 90 on the passivation layer 80, and the pixel electrode 90 contacting the drain electrode 74 through the fifth via hole 85.
Specifically, in step S7, the passivation layer 80 is deposited to a thickness of
The passivation layer 80 is a silicon oxide layer, a silicon nitride layer, or a combination of both.
According to the manufacturing method of the TFT driving back plate, the th through hole 22 and the second through hole 62 are sequentially formed on the buffer layer 20 and the interlayer insulating layer 60 respectively, so that the electrical property abnormity of a device caused by the fact that holes are formed in the buffer layer 20 and the interlayer insulating layer 60 is avoided, and compared with the prior art, the thickness of a dielectric layer of a storage capacitor formed by the grid layer electrode block 52 and the shielding layer electrode block 102 is reduced by arranging the capacitor increasing groove on the buffer layer 20, so that the charge storage capacity of the storage capacitor is effectively improved, the area occupied by the storage capacitor is correspondingly reduced, and the aperture ratio of the TFT driving back plate is increased.
In summary, according to the manufacturing method of TFT driving backplates provided by the present invention, a capacitance increasing groove and a th via hole are formed above a shielding layer electrode block on a buffer layer, a gate layer electrode block is formed above the capacitance increasing groove, a second via hole communicated with a th via hole is formed on an interlayer insulating layer, a subsequent signal connecting block contacts with the shielding layer electrode block through the th via hole and the second via hole, and a th via hole and a second via hole are formed on the buffer layer and the interlayer insulating layer in sequence, so that electrical abnormality of a device caused by opening holes in the buffer layer and the interlayer insulating layer is avoided.
As described above, it will be apparent to those skilled in the art that various other changes and modifications can be made based on the technical solution and the technical idea of the present invention, and all such changes and modifications should fall within the protective scope of the appended claims.
Claims (10)
1, kinds of TFT drive backplate's preparation method, characterized by, including the following step:
step S1, providing a substrate (10), dividing a TFT forming area and a capacitor forming area which are arranged in parallel on the substrate (10), depositing and forming a metal shielding layer on the substrate (10), and patterning the metal shielding layer to obtain a metal light shielding block (101) and a shielding layer electrode block (102) which are respectively positioned above the TFT forming area and the capacitor forming area;
step S2, sequentially depositing and forming a buffer layer (20) and a metal oxide semiconductor layer (30) on the metal shading block (101), the shielding layer electrode block (102) and the substrate (10), and patterning the metal oxide semiconductor layer (30) to obtain an active layer (35) correspondingly positioned above the metal shading block (101);
step S3, patterning the buffer layer (20), and forming a capacitance increasing groove (21) and a th through hole (22) which are spaced above the shielding layer electrode block (102);
step S4, sequentially depositing and forming an insulating layer (40) and a gate metal layer (50) on the buffer layer (20) and the active layer (35), patterning the gate metal layer (50) and the insulating layer (40), obtaining a gate electrode (55) located above the TFT forming region and a gate layer electrode block (52) correspondingly located above the capacitance increasing groove (21) from the gate metal layer (50), and obtaining a gate insulating layer (45) correspondingly located below the gate electrode (55) and the gate layer electrode block (52) from the insulating layer (40);
step S5, depositing and forming an interlayer insulating layer (60) on the gate electrode (55), the active layer (35), the gate layer electrode block (52) and the buffer layer (20), patterning the interlayer insulating layer (60), and forming a second via hole (62) which is communicated with the via hole (22) above the via hole (22) and a third via hole (63) and a fourth via hole (64) above two sides of the active layer (35) on the interlayer insulating layer (60);
step S6, depositing and forming a source and drain metal layer (70) on the interlayer insulating layer (60), patterning the source and drain metal layer (70) to obtain a signal connecting block (72) correspondingly positioned above the shielding layer electrode block (102) and a source electrode (73) and a drain electrode (74) respectively positioned above the TFT forming area, wherein the signal connecting block (72) is contacted with the shielding layer electrode block (102) through the through hole (22) and the second through hole (62), and the source electrode (73) and the drain electrode (74) are contacted with two sides of the active layer (35) through the third through hole (63) and the fourth through hole (64).
2. The method for fabricating the TFT driving back plate as claimed in claim 1, wherein the metal shielding layer is deposited to a thickness of S1
The material of the metal shielding layer is or more alloys of molybdenum, aluminum, copper and titanium.
3. The method of fabricating the TFT driving back plate as claimed in claim 1, wherein the buffer layer (20) is deposited to a thickness of S2
The buffer layer (20) is a silicon oxide layer, a silicon nitride layer, or a combination of both.
4. The method of claim 1, wherein in step S2, the metal oxide semiconductor layer (30) is deposited to a thickness of
The metal oxide semiconductor layer (30) is made of indium gallium zinc oxide, indium zinc tin oxide or indium gallium zinc tin oxide.
5. The method of claim 1, wherein the step S4 further comprises ion doping the active layer (35) by a plasma doping process using the gate electrode (55) and the gate insulating layer (45) as a barrier layer, so that the conductivity of the region of the active layer (35) not covered by the gate electrode (55) and the gate insulating layer (45) is enhanced.
6. The method of claim 1, wherein in step S4, the insulating layer (40) is deposited to a thickness of
The insulating layer (40) is a silicon oxide layer, a silicon nitride layer or a combination of the two; the gate metal layer (50) is deposited to a thickness of
The material of the gate metal layer (50) is or more alloys of molybdenum, aluminum, copper and titanium.
7. The method of fabricating a TFT driving backplane according to claim 1, wherein the interlayer insulating layer (60) is deposited to a thickness of S5The interlayer insulating layer (60) is a silicon oxide layer, a silicon nitride layer, or a combination of both.
8. The method for manufacturing the TFT driving back plate as claimed in claim 1, wherein the thickness of the deposited source/drain metal layer (70) in step S6 is equal to
The source drain electrode metal layer (70) is made of or more alloys of molybdenum, aluminum, copper and titanium.
9. The method of fabricating the TFT driving back plate as claimed in claim 1, further comprising step S7, depositing a passivation layer (80) on the interlayer insulating layer (60), the signal connection block (72), the source electrode (73) and the drain electrode (74), patterning the passivation layer (80), forming a fifth via hole (85) on the passivation layer (80) corresponding to the upper portion of the drain electrode (74), depositing and patterning a pixel electrode (90) on the passivation layer (80), wherein the pixel electrode (90) contacts the drain electrode (74) through the fifth via hole (85).
10. The method of fabricating the TFT driving back plate as claimed in claim 9, wherein the passivation layer (80) is deposited to a thickness of S7
The passivation layer (80) is oxygenA silicon nitride layer, or a combination of both.
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| CN108461520A (en) * | 2018-01-09 | 2018-08-28 | 深圳市华星光电半导体显示技术有限公司 | A kind of OLED backboards and preparation method thereof |
| CN108257977B (en) * | 2018-01-10 | 2021-01-01 | 京东方科技集团股份有限公司 | Display back plate and manufacturing method thereof, display panel and display device |
| US10553614B2 (en) | 2018-02-05 | 2020-02-04 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Thin-film transistor array substrate and manufacturing method for the same |
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| CN109461763B (en) * | 2018-10-17 | 2021-04-27 | Tcl华星光电技术有限公司 | Preparation method of display panel and display panel |
| CN109585516B (en) * | 2018-12-13 | 2021-02-23 | 武汉华星光电半导体显示技术有限公司 | TFT drive backplate |
| CN109755260A (en) * | 2018-12-24 | 2019-05-14 | 惠科股份有限公司 | The manufacturing method and display device of a kind of display panel, display panel |
| CN110400809A (en) * | 2019-07-24 | 2019-11-01 | 深圳市华星光电半导体显示技术有限公司 | TFT drives backboard and Micro-LED display |
| CN111312753A (en) * | 2019-11-29 | 2020-06-19 | 京东方科技集团股份有限公司 | Method for improving aperture opening ratio of back plate, manufacturing method, back plate and display panel |
| CN111599750A (en) * | 2020-05-29 | 2020-08-28 | 福建华佳彩有限公司 | Compensation capacitor structure for improving capacitance value and manufacturing method |
| US11417689B2 (en) | 2020-07-16 | 2022-08-16 | Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Display panel |
| CN111564458B (en) * | 2020-07-16 | 2020-10-23 | 武汉华星光电半导体显示技术有限公司 | Display panel |
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