KR20020072882A - Manufacturing method of thin film transistor array panel for liquid crystal display - Google Patents

Abstract

PURPOSE: A method for fabricating a TFT(Thin Film Transistor) substrate of an LCD(Liquid Crystal Display) is provided to delay the exposure of data lines to the etching gas via contact holes, thereby preventing the short or corrosion of the data lines. CONSTITUTION: A method for fabricating a TFT substrate of an LCD includes the steps of forming gate wires having gate lines(22), gate electrodes(26) connected to the gate lines and gate pads(24) on an insulating substrate(10) by stacking and patterning a conductive material, forming a gate insulating film, forming a semiconductor layer(40) on the gate insulating film, forming data wires having data lines(62) intersecting the gate lines, source electrodes(65) connected to the data lines and adjacent to the gate electrodes, drain electrodes(66) opposing the source electrodes with respect to the gate electrodes, and data pads(68) connected to the data lines by stacking and patterning a conductive material, forming first to third contact holes(72,74,76) by stacking and patterning a protection film to expose the gate pads, the data pads and the drain electrodes, and forming pixel electrodes(82) electrically connected to the drain electrodes via the third contact holes, wherein the contact holes are formed by photo-etching using a photosensitive film pattern having different thickness partially.

Description

The manufacturing method of the thin-film transistor board | substrate for liquid crystal display devices {MANUFACTURING METHOD OF THIN FILM TRANSISTOR ARRAY PANEL FOR LIQUID CRYSTAL DISPLAY}

The present invention relates to a method for manufacturing a thin film transistor substrate for a liquid crystal display device.

The liquid crystal display is one of the most widely used flat panel display devices. The liquid crystal display includes two substrates on which electrodes are formed and a liquid crystal layer interposed therebetween, and rearranges the liquid crystal molecules of the liquid crystal layer by applying a voltage to the electrode. By controlling the amount of light transmitted.

Among the liquid crystal display devices, a liquid crystal display device having a thin film transistor for forming an electrode on each of two substrates and switching a voltage applied to the electrode is generally used. The thin film transistor is generally formed on one of two substrates.

The substrate on which the thin film transistor is formed is generally manufactured by a photolithography process using a mask, and a process of forming a gate wiring, a semiconductor layer, a data wiring, a pixel electrode, and wiring for electrically connecting external circuits and wiring. The insulating film covering the substrate is etched to expose the gate and the data pad of the wiring. In this case, the data line is formed of a molybdenum series such as molybdenum (Mo) or molybdenum-tungsten (Mo-W) having excellent contact characteristics with the semiconductor layer and low resistance.

However, SF ₆ , CF _4, etc. are preferably used as an etching gas for etching the insulating film of silicon nitride in the process of exposing the pad. When molybdenum-based metal is exposed to the etching gas for a long time during the etching of the insulating film, molybdenum There is a problem that the wiring of the series is etched and the wiring is disconnected or eroded.

An object of the present invention is to provide a method for manufacturing a thin film transistor substrate that can prevent the disconnection or erosion failure of the data wiring.

1 is a thin film transistor substrate for a liquid crystal display device according to a first embodiment of the present invention;

FIG. 2 is a cross-sectional view of the thin film transistor substrate illustrated in FIG. 1 taken along the line II-II.

3A, 4A, 5A, and 7A are layout views of a thin film transistor substrate in an intermediate process of manufacturing a thin film transistor substrate for a liquid crystal display device according to a first embodiment of the present invention;

3B is a cross-sectional view taken along the line IIIb-IIIb ′ in FIG. 3A;

4B is a cross-sectional view taken along the line IVb-IVb ′ in FIG. 4A and is a cross-sectional view showing the next step in FIG. 3B;

FIG. 5B is a cross-sectional view taken along the line Vb-Vb ′ in FIG. 5A and is a cross-sectional view showing the next step in FIG. 4B;

6 is a sectional view showing the next step of 5b,

FIG. 7B is a cross-sectional view taken along the line VIIb-VIIb ′ of FIG. 7A and illustrating the next step of FIG. 6;

8 is a layout view of a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment of the present invention.

9 and 10 are cross-sectional views of the thin film transistor substrate illustrated in FIG. 8 taken along lines IX-IX 'and X-X',

11A is a layout view of a thin film transistor substrate at a first stage of manufacture in accordance with a second embodiment of the present invention,

11B and 11C are cross-sectional views taken along the lines XIb-XIb 'and XIc-XIc' of FIG. 11A, respectively.

12A and 12B are cross-sectional views taken along the lines XIb-XIb 'and XIc-XIc' of FIG. 11A, respectively, and are cross-sectional views of the next steps of FIGS. 11B and 11C;

FIG. 13A is a layout view of a thin film transistor substrate at a next step of FIGS. 12A and 12B;

13B and 13C are cross-sectional views taken along the lines XIIIb-XIIIb 'and XIIIc-XIIIc' of FIG. 13A, respectively.

14A, 15A, 16A and 14B, 15B, 16B are cross-sectional views taken along the lines XIIIb-XIIIb 'and XIIIc-XIIIc' in FIG. 13A, respectively, illustrating the following steps in the order of the process. ,

17A is a layout view of a thin film transistor substrate in the next steps of FIGS. 16A and 16B,

17B and 17C are cross-sectional views taken along the lines XVIIb-XVIIb 'and XVIIc-XVIIc', respectively, in FIG. 17A.

In order to solve this problem, the present invention delays the exposure of the data wiring to the etching gas in the process of etching the insulating film by leaving a photosensitive film at a portion corresponding to the contact portion exposing the data wiring.

More specifically, in the method for manufacturing a thin film transistor substrate according to the present invention, first, a gate wiring conductive material is laminated and patterned on an insulating substrate to form a gate wiring including a gate line, a gate electrode connected to the gate line, and a gate pad. Next, a gate insulating film and a semiconductor layer are formed, and a conductive material for data wiring is stacked and patterned thereon, so that the data electrode crossing the gate line and the source electrode connected to the data line and adjacent to the gate electrode, A data line is formed to include a drain electrode positioned at an opposite side thereof and a data pad connected to the data line. Subsequently, the protective layer is stacked and patterned to form first to third contact holes exposing the gate pad, the data pad, and the drain electrode, respectively, and to form a pixel electrode electrically connected to the drain electrode through the third contact hole. In this case, the first to third contact hole forming steps may be formed by a photolithography process using photoresist patterns having partially different thicknesses.

Here, the photoresist pattern may include a first portion having a first thickness, a second portion having almost no thickness, a third portion having a thickness greater than the first thickness, and excluding the first and second portions, and a photograph. In the etching process, the photoresist pattern is formed using an optical mask including a first region, a second region having a higher transmittance than the first region, and a third region having a lower transmittance than the first region.

In this case, in the photolithography process, the first portion may be formed to correspond to the second and third contact holes, and the second portion corresponds to the third contact hole.

In order to control the transmittance of the first to third regions differently, it is preferable that a slit pattern smaller than the resolution of the translucent film or the exposure machine is formed in the photomask.

The data line and the semiconductor layer may be formed by a photolithography process using photoresist patterns having different thicknesses.

The conductive material for data wiring includes an aluminum-based or molybdenum-based metal, and the pixel electrode is preferably formed of IZO or ITO.

Next, a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings so that a person skilled in the art may easily implement the present invention.

First, a structure of a thin film transistor substrate for a liquid crystal display according to a first embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.

1 is a thin film transistor substrate for a liquid crystal display device according to a first embodiment of the present invention, and FIG. 2 is a cross-sectional view of the thin film transistor substrate shown in FIG. 1 taken along the line II-II.

A gate wiring made of an aluminum-based metal material having low resistance is formed on the insulating substrate 10. The gate wire is connected to the gate line 22 and the gate line 22 extending in the horizontal direction, and are connected to the gate pad 24 and the gate line 22 which receive a gate signal from the outside and transmit the gate signal to the gate line. A gate electrode 26 of the thin film transistor.

On the substrate 10, a gate insulating film 30 made of silicon nitride (SiN _x ) covers the gate wirings 22, 24, and 26, and the gate insulating film 30 is provided with a gate pad along with a protective film 70 formed thereafter. (24) It has a contact hole 74 that exposes the top.

A semiconductor layer 40 made of a semiconductor such as amorphous silicon is formed on the gate insulating film 30 of the gate electrode 24, and n + having a high concentration of silicide or n-type impurity is formed on the semiconductor layer 40. Resistive contact layers 55 and 56 made of a material such as hydrogenated amorphous silicon are formed, respectively.

On the resistive contact layers 55 and 56 and the gate insulating film 30, data lines 62, 64, 66, and 68 made of a single film of molybdenum (Mo) or molybdenum-tungsten (MoW) alloy are formed. The data line is formed in the vertical direction and crosses the gate line 22 to define a pixel, and the data line 62 is a branch of the data line 62 and the source electrode 65 extending to the upper portion of the ohmic contact layer 55. ), Which is connected to one end of the data line 62 and is separated from the data pad 68 and the source electrode 65 to which an image signal from the outside is applied, and is opposite to the source electrode 65 with respect to the gate electrode 26. And a drain electrode 66 formed on the ohmic contact layer 56. In addition, the data line may include a conductor pattern 64 for an organic capacitor that overlaps the gate line 22 to improve the storage capacitance.

The data lines 62, 65, 66, and 68 may be formed of a single layer of aluminum series. In the case of forming more than two layers, one layer is formed of an aluminum series material having low resistance and the other layer is separated from other materials. It is preferable to make the material such as molybdenum series or chromium having good contact characteristics. Examples thereof include Cr / Al (or Al alloy) or Al (or Al alloy) / Mo.

The passivation layer 70 is formed on the data lines 62, 64, 65, 66, and 68 and the semiconductor layer 40 which is not covered by the data lines 62. In the passivation layer 70, contact holes 72, 76, and 78 that expose the conductive capacitor 64 for the storage capacitor, the drain electrode 66, and the data pad 68 are formed, respectively, and together with the gate insulating layer 30. The contact hole 74 which exposes the gate pad 24 is formed.

On the passivation layer 70, contact holes 74 and 78 are connected to the conductive pattern 64 for the storage capacitor and the drain electrode 66 through the contact holes 72 and 76 and the pixel electrode 82 positioned in the pixel. A subsidiary gate pad 84 and an auxiliary data pad 88 connected to the gate pad 24 and the data pad 68, respectively, and a pixel wiring made of a transparent conductive material such as IZO or ITO have.

1 and 2, the pixel electrode 82 overlaps with the gate line 22 to form a storage capacitor. When the storage capacitor is insufficient, the pixel electrode 82 is disposed on the same layer as the gate wirings 22, 24, and 26. It is also possible to add a storage capacitor wiring.

In the structure according to the embodiment of the present invention, the low resistance includes data wires 62, 64, 65, 66, and 68 made of molybdenum-based metal, and thus it can be applied to a liquid crystal display device having a high resolution.

Next, a method of manufacturing a thin film transistor substrate for a liquid crystal display device having a structure according to a first embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2 and FIGS. 3A to 7B.

First, as shown in FIGS. 3A and 3B, an aluminum-based conductive film having a low resistance is stacked and patterned on the substrate 10 to a thickness of about 2,500 kV to form a gate line 22, a gate electrode 26, and a gate pad. The horizontal gate wiring including 24 is formed.

Next, as shown in FIGS. 4A and 4B, three layers of the gate insulating film 30, the amorphous silicon layer 40, and the doped amorphous silicon layer 50 are successively laminated, and the amorphous silicon layer is formed by a patterning process using a mask. The semiconductor layer 40 and the ohmic contact layer 50 are formed on the gate insulating layer 30 facing the gate electrode 24 by patterning the doped amorphous silicon layer 50.

Next, as shown in FIGS. 5A and 5B, a molybdenum or molybdenum alloy having low resistance and excellent contact characteristics with the amorphous silicon layers 40 and 50 is laminated and patterned by a photo process using a mask to form a gate line 22. ) And a data pad 68 connected to the data line 62, a source electrode 65 extending to the upper portion of the gate electrode 26, and a data pad 62 connected to one end thereof. And a conductive pattern 64 for the storage capacitor which is separated from the source electrode 65 and overlaps the drain electrode 66 and the gate line 22 facing the source electrode 66 with respect to the gate electrode 26. To form a data wiring comprising a.

Subsequently, the doped amorphous silicon layer pattern 50, which is not covered by the data lines 62, 64, 65, 66, and 68, is etched to separate the gate electrode 26 from both sides, while the doped amorphous silicon on both sides is etched. The semiconductor layer pattern 40 between the layers 55 and 56 is exposed. Subsequently, in order to stabilize the surface of the exposed semiconductor layer 40, it is preferable to perform oxygen plasma.

Next, as shown in FIG. 6, a protective film 70 made of silicon nitride or an organic insulating film is laminated on the substrate 10, and a photoresist film is applied thereon with a thickness of 1 μm to 2 μm, and then a mask The contact holes 76, 72, and 78 exposing the photoresist film through a photolithography process and then developing to expose the drain electrode 66, the conductive capacitor pattern 64 for the storage capacitor, and the data pad 68 are formed of molybdenum series. Photosensitive film patterns 102 and 104 having an intermediate thickness in the C region to be formed and having almost no thickness in the B region in which the contact hole 74 exposing the gate pad 24 is formed, and having a thickness thicker than the C region in the remaining A region. ).

As such, there may be various methods of varying the thickness of the photoresist layer according to the position. In order to control the light transmittance in the A region, a slit or lattice-shaped pattern is mainly formed or a translucent film is used.

In this case, the line width of the pattern located between the slits, or the interval between the patterns, that is, the width of the slits, is preferably smaller than the resolution of the exposure apparatus used for exposure. A thin film having a thickness or a thin film may be used.

When the light is irradiated to the photosensitive film through such a mask, the polymers are completely decomposed at the part directly exposed to the light, and the polymers are not completely decomposed because the amount of light is small at the part where the slit pattern or the translucent film is formed. In the area covered by, the polymer is hardly decomposed. Subsequently, when the photoresist film is developed, only a portion where the polymer molecules are not decomposed is left, and a thin photoresist film may be left at a portion where the light is not irradiated at a portion less irradiated with light. In this case, if the exposure time is extended, all molecules are decomposed, so it should not be so.

This medium-thick photoresist film 104 is developed by using a photoresist film made of a reflowable material and exposed with a conventional mask that is divided into a part that can completely transmit light and a part that can't completely transmit light. It can also be formed by making a part of the photosensitive film flow to the part which does not remain | survive by making it low.

Here, leaving the photosensitive film pattern 102 having an intermediate thickness in the C region may be performed by using an etching gas including SF _6, CF ₄ , or the like in the subsequent process to protect the silicon nitride protective film 70 and the gate insulating film 30. This is to prevent the molybdenum-based data lines 64, 66, and 68 from being exposed to the etching gas for a long time when the contact holes 72, 74, 76, and 78 are formed by etching. That is, in order to form the contact holes 72, 74, 76, and 78, the etching process should proceed until the gate pad 24 is exposed by etching the passivation layer 70 and the gate insulating layer 30. However, only the passivation layer 70 is formed on the data lines 64, 66, and 68, and the contact holes 72 and 76 are formed in the passivation layer 70 while the gate insulation layer 30 is etched to expose the gate pad 24. , 78 has already been completed and the data wires 64, 66, 68 are exposed through the contact holes 72, 76, 78 to expose to the etching gas, which causes the data wires 64, 66, 68 to be disconnected or eroded. do. As in the present invention, the data wirings 64, 66, and 68 formed of molybdenum series are exposed through the contact holes 72, 76, and 78 in the protective layer 70 by leaving the photoresist pattern 102 having an intermediate thickness in the C region. Delay to prevent exposure of the data lines 64, 66, 68 to the contact holes 72, 76, 78. In this case, the thickness of the photoresist pattern 102 may be adjusted differently according to etching conditions, and in the case of selecting a process condition having no etching selectivity between the photoresist pattern 102, the protective layer 70, and the gate insulating layer 30, the photoresist pattern It is preferable to form the thickness of 102 equal to the thickness of the gate insulating film 30.

Next, as shown in FIGS. 7A and 7B, the photoresist pattern 104 and the lower layers thereof, that is, the protective layer 70 and the gate insulating layer 30 are etched to form contact holes 72, 74, 76, and 78. To complete).

Next, as shown in FIGS. 1 and 2, the IZO or ITO film is laminated and patterned using a mask to conduct the conductive capacitor pattern 64 and the drain electrode 66 for the storage capacitor through the contact holes 72 and 76. The auxiliary gate pad 86 and the auxiliary data pad 88 connected to the gate pad 24 and the data pad 68 through the pixel electrode 82 and the contact holes 74 and 78 electrically connected to Form each.

In the manufacturing method according to the embodiment of the present invention, when forming the contact holes 72, 74, 76, and 78, the photoresist layer pattern 104 is left on the data lines 64, 66, and 68, so that the protective layer 70 and Delaying or erosion of the data lines 64, 66, and 68 may be prevented by delaying the molybdenum-based data lines 64, 66, and 68 from being exposed to the etching gas for etching the gate insulating layer 30.

As described above, the method can be applied to a manufacturing method using five masks, but the same method can be applied to a manufacturing method of a thin film transistor substrate for a liquid crystal display device using four masks. This will be described in detail with reference to the drawings.

First, a unit pixel structure of a thin film transistor substrate for a liquid crystal display device completed using four masks according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 8 to 10.

FIG. 8 is a layout view of a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment of the present invention, and FIGS. 9 and 10 are lines IIX-IIX 'and IX-IX', respectively, of the thin film transistor substrate shown in FIG. 8. A cross-sectional view taken along the line.

First, a gate line including a gate line 22, a gate pad 24, and a gate electrode 26 made of an aluminum-based metal is formed on the insulating substrate 10 as in the first embodiment. The gate wiring includes a sustain electrode 28 that is parallel to the gate line 22 on the substrate 10 and receives a voltage such as a common electrode voltage input to the common electrode of the upper plate from the outside. The storage electrode 28 overlaps with the conductive capacitor conductor 68 for the storage capacitor connected to the pixel electrode 82, which will be described later, to form a storage capacitor which improves the charge retention capability of the pixel. The pixel electrode 82 and the gate line, which will be described later, If the holding capacity generated by the overlap of (22) is sufficient, it may not be formed.

A gate insulating film 30 made of silicon nitride (SiN _x ) is formed on the gate wirings 22, 24, 26, and 28 to cover the gate wirings 22, 24, 26, and 28.

Semiconductor patterns 42 and 48 made of semiconductors such as hydrogenated amorphous silicon are formed on the gate insulating layer 30, and high concentrations of n-type impurities such as phosphorus (P) are formed on the semiconductor patterns 42 and 48. An ohmic contact layer pattern or an intermediate layer pattern 55, 56, 58 made of amorphous silicon doped with is formed.

The resistive contact layer patterns 55, 56, and 58 are made of a molybdenum-based conductive material having low resistance and excellent contact properties with amorphous silicon of the semiconductor patterns 42 and 48 or the intermediate layer patterns 55, 56, and 58. The data wiring is formed. The data line is a thin film transistor which is a branch of the data line 62 formed in the vertical direction, the data pad 68 connected to one end of the data line 62 to receive an image signal from the outside, and the data line 62. And a data line portion of the source electrode 65 of the source electrode 65. The data line portion is separated from the data line portions 62, 68, and 65, and the source electrode 65 is separated from the gate electrode 26 or the channel portion C of the thin film transistor. It also includes a conductive capacitor conductor 64 for the storage capacitor located on the drain electrode 66 and the storage electrode 28 of the thin film transistor located on the opposite side. When the sustain electrode 28 is not formed, the conductor pattern 64 for the storage capacitor is also not formed.

The data wirings 62, 64, 65, 66, and 68 also include an aluminum-based conductive film similar to the gate wirings 22, 24, 26, and 28, and similarly to the first embodiment, include chromium, molybdenum, or molybdenum alloys. It may be formed as a double film.

The contact layer patterns 55, 56, and 58 serve to lower the contact resistance between the semiconductor patterns 42 and 48 below and the data lines 62, 64, 65, 66, and 68 above them. It has exactly the same form as (62, 64, 65, 66, 68). That is, the data line part intermediate layer pattern 55 is the same as the data line parts 62, 68, and 65, the drain electrode intermediate layer pattern 56 is the same as the drain electrode 66, and the storage capacitor intermediate layer pattern 58 is It is the same as the conductor pattern 64 for holding capacitors.

The semiconductor patterns 42 and 48 have the same shapes as the data lines 62, 64, 65, 66, and 68 and the ohmic contact layer patterns 55, 56, and 57 except for the channel portion C of the thin film transistor. Doing. Specifically, the semiconductor capacitor 48 for the storage capacitor, the conductor pattern 64 for the storage capacitor, and the contact layer pattern 58 for the storage capacitor have the same shape, but the semiconductor pattern 42 for the thin film transistor has data wiring and contact. Slightly different from the rest of the layer pattern. That is, in the channel portion C of the thin film transistor, the data line portions 62, 68, and 65, in particular, the source electrode 65 and the drain electrode 66 are separated, and the contact layer pattern for the data line intermediate layer 55 and the drain electrode. Although 56 is also separated, the semiconductor pattern 42 for thin film transistors is not disconnected here and is connected to generate a channel of the thin film transistor.

The passivation layer 70 is formed on the data wires 62, 64, 65, 66, and 68, and the passivation layer 70 forms the drain electrode 66, the data pad 68, and the conductive pattern 64 for the storage capacitor. It has exposed contact holes 76, 78 and 72, and also has a contact hole 74 which exposes the gate pad 24 together with the gate insulating film 30. As shown in FIG. The passivation layer 70 may be made of an organic insulating material such as silicon nitride or acrylic.

On the passivation layer 70, a pixel electrode 82 that receives an image signal from a thin film transistor and generates an electric field together with the electrode of the upper plate is formed. The pixel electrode 82 is made of a transparent conductive material such as indium zinc oxide (IZO) or indium tin oxide (ITO), and is electrically connected to the drain electrode 66 through the contact hole 76 to receive an image signal. The pixel electrode 82 also overlaps with the neighboring gate line 22 and the data line 62 to increase the aperture ratio, but may not overlap. In addition, the pixel electrode 82 is electrically connected to the conductor pattern 64 for the storage capacitor through the contact hole 72 to transmit an image signal to the conductor pattern 64. On the other hand, an auxiliary gate pad 84 and an auxiliary data pad 88 connected to the gate pad 24 and the data pad 68 through the contact holes 74 and 78, respectively, are formed. 68) and to protect the pads and the adhesion of the external circuit device, and is not essential, their application is optional.

Here, transparent IZO and ITO have been cited as examples of the material of the pixel electrode 82. However, in the case of a reflective liquid crystal display, an opaque conductive material may be used.

Next, a method of manufacturing a thin film transistor substrate for a liquid crystal display device having the structure of FIGS. 8 to 10 using four masks will be described in detail with reference to FIGS. 8 to 10 and FIGS. 11A to 17C. .

First, as shown in FIGS. 11A to 11C, the gate line 22 is formed on the substrate 10 by a photolithography process using a first mask by stacking a low resistance aluminum-based conductive material as in the first embodiment. A gate wiring including the gate pad 24, the gate electrode 26, and the sustain electrode 28 is formed.

Next, as shown in FIGS. 12A and 12B, the gate insulating film 30, the semiconductor layer 40, and the intermediate layer 50 are respectively 1,500 kV to 5,000 kV, 500 kV to 2,000 kV, and 300 kV using chemical vapor deposition. The film is continuously deposited to a thickness of 600 kPa, and then the molybdenum-based conductor layer 60 is successively laminated by sputtering or the like, and then the photosensitive film 110 is applied thereon in a thickness of 1 μm to 2 μm.

Thereafter, the photoresist film 110 is irradiated with light through a second mask and then developed to form photoresist patterns 112 and 114 as illustrated in FIGS. 13B and 13C. In this case, among the photoresist patterns 112 and 114, the channel portion C of the thin film transistor, that is, the first portion 114 positioned between the source electrode 65 and the drain electrode 66, is the data wiring portion A, that is, the data. The thickness of the wirings 62, 64, 65, 66, and 68 is smaller than that of the second portion 112 positioned at the portion where the wirings 62, 64, 65, 66, and 68 are to be formed, and all the photoresist of the other portion B is removed. At this time, the ratio of the thickness of the photoresist film 114 remaining in the channel portion C to the thickness of the photoresist film 112 remaining in the data wiring portion A should be different depending on the process conditions in the etching process described later. It is preferable to make the thickness of the 1st part 114 into 1/2 or less of the thickness of the 2nd part 112, for example, it is good that it is 4,000 Pa or less.

In this way, the method of varying the thickness of the photosensitive film according to the position is the same as that of the first embodiment.

Subsequently, etching is performed on the photoresist pattern 114 and the underlying layers, that is, the conductor layer 60, the intermediate layer 50, and the semiconductor layer 40. In this case, the data line and the lower layer of the data line remain in the data wiring portion A, and only the semiconductor layer should remain in the channel portion C, and the upper three layers 60, 50, 40 must be removed to expose the gate insulating film 30.

First, as shown in FIGS. 14A and 14B, the exposed conductor layer 60 of the other portion B is removed to expose the lower intermediate layer 50. In this process, either a dry etching method or a wet etching method may be used. In this case, the conductor layer 60 may be etched and the photoresist patterns 112 and 114 may be hardly etched. However, in the case of dry etching, it is difficult to find a condition in which only the conductor layer 60 is etched and the photoresist patterns 112 and 114 are not etched, so that the photoresist patterns 112 and 114 may also be etched together. In this case, the thickness of the first portion 114 is thicker than that of the wet etching so that the first portion 114 is removed in this process so that the lower conductive layer 60 is not exposed.

When the conductor layer 60 is any one of Mo or MoW alloy, Al or Al alloy, and Ta, either dry etching or wet etching can be used. However, since Cr is not easily removed by the dry etching method, it is preferable to use only wet etching if the conductor layer 60 is Cr. In the case of wet etching in which the conductor layer 60 is Cr, CeNHO ₃ may be used as an etchant. In the case of dry etching in which the conductor layer 60 is Mo or MoW, the mixed gas or CF of CF ₄ and HCl may be used as the etching gas. A mixed gas of ₄ and O ₂ can be used, and in the latter case, the etching ratio to the photoresist film is almost the same.

In this way, as shown in Figs. 14A and 14B, only the conductor layer of the channel portion C and the data wiring portion B, that is, the conductor pattern 67 for the source / drain and the conductor pattern 64 for the storage capacitor All of the conductor layer 60 of the remaining portion B is removed, revealing the underlying intermediate layer 50. The remaining conductor patterns 67 and 64 have the same shape as the data lines 62, 64, 65, 66 and 68 except that the source and drain electrodes 65 and 66 are connected without being separated. In addition, when dry etching is used, the photoresist patterns 112 and 114 are also etched to a certain thickness.

Subsequently, as shown in FIGS. 15A and 15B, the exposed intermediate layer 50 of the other portion B and the semiconductor layer 40 below it are simultaneously removed together with the first portion 114 of the photosensitive film by a dry etching method. do. At this time, etching is performed under the condition that the photoresist patterns 112 and 114, the intermediate layer 50, and the semiconductor layer 40 (the semiconductor layer and the intermediate layer have almost no etching selectivity) are simultaneously etched, and the gate insulating layer 30 is not etched. In particular, it is preferable to etch under conditions in which the etch ratios of the photoresist patterns 112 and 114 and the semiconductor layer 40 are almost the same. For example, by using a mixed gas of SF ₆ and HCl or a mixed gas of SF ₆ and O ₂ , the two films can be etched to almost the same thickness. When the etching ratios of the photoresist patterns 112 and 114 and the semiconductor layer 40 are the same, the thickness of the first portion 114 should be equal to or smaller than the sum of the thicknesses of the semiconductor layer 40 and the intermediate layer 50.

This removes the first portion 114 of the channel portion C, revealing the source / drain conductor pattern 67, as shown in FIGS. 15A and 15B, and the intermediate layer 50 of the other portion B. And the semiconductor layer 40 is removed to expose the gate insulating layer 30 thereunder. On the other hand, since the second portion 112 of the data wiring portion A is also etched, the thickness becomes thin. In this step, the semiconductor patterns 42 and 48 are completed. Reference numerals 57 and 58 denote intermediate layer patterns under the source / drain conductor patterns 67 and intermediate layer patterns under the storage capacitor conductor patterns 64, respectively.

Subsequently, ashing removes photoresist residue remaining on the surface of the source / drain conductor pattern 67 of the channel portion C.

Next, as shown in FIGS. 16A and 16B, the source / drain conductor pattern 67 of the channel part C and the source / drain interlayer pattern 57 below are etched and removed. In this case, the etching may be performed only by dry etching with respect to both the source / drain conductor pattern 67 and the intermediate layer pattern 57. The etching may be performed by wet etching on the source / drain conductor pattern 67. 57 may be performed by dry etching. In the former case, it is preferable to perform etching under a condition in which the etching selectivity of the source / drain conductor pattern 67 and the interlayer pattern 57 is large, which is difficult to find the etching end point when the etching selectivity is not large. This is because it is not easy to adjust the thickness of the semiconductor pattern 42 remaining in the " For example, those of etching the SF ₆ and O ₂ by using the mixed gas of the source / drain conductive pattern 67. In the latter case of alternating between wet etching and dry etching, the side surface of the conductive pattern 67 for wet etching of the source / drain is etched, but the intermediate layer pattern 57 which is dry etched is hardly etched, and thus is formed in a step shape. Examples of the etching gas used to etch the intermediate layer pattern 57 and the semiconductor pattern 42 include the aforementioned mixed gas of CF ₄ and HCl or mixed gas of CF ₄ and O ₂ , and CF ₄ and O _{Using 2} can leave the semiconductor pattern 42 in a uniform thickness. In this case, as shown in FIG. 15B, a portion of the semiconductor pattern 42 may be removed to reduce the thickness, and the second portion 112 of the photoresist pattern may also be etched to a certain thickness at this time. At this time, the etching should be performed under the condition that the gate insulating film 30 is not etched, and the photoresist film is not exposed so that the second part 112 is etched so that the data lines 62, 64, 65, 66, and 68 underneath are not exposed. It is a matter of course that the pattern is thick.

In this way, the source electrode 65 and the drain electrode 66 are separated, thereby completing the data lines 62, 64, 65, 66, and 68 and the contact layer patterns 55, 56, and 58 under the data lines.

Finally, the second photoresist layer 112 remaining in the data wiring portion A is removed. However, the removal of the second portion 112 may be made after removing the conductor pattern 67 for the channel portion C source / drain and before removing the intermediate layer pattern 57 thereunder.

As mentioned earlier, wet and dry etching can be alternately used or only dry etching can be used. In the latter case, since only one type of etching is used, the process is relatively easy, but it is difficult to find a suitable etching condition. On the other hand, in the former case, the etching conditions are relatively easy to find, but the process is more cumbersome than the latter.

After the data wirings 62, 64, 65, 66, and 68 are formed in this manner, as shown in FIGS. 17A to 17C, silicon nitride is deposited by CVD or spin-coated an organic insulating material to have a thickness of 3,000 Å or more. After the protective film 70 is formed, the same photosensitive film patterns 102, 104, and 6 as in the first embodiment are used by using a third mask to delay the data lines 64, 66, and 68 from being exposed to the etching gas. ). Subsequently, the photoresist layer patterns 102 and 104, the lower protective layer 70, and the gate insulating layer 30 are etched to form a drain electrode 66, a gate pad 24, a data pad 68, and a conductor for a storage capacitor. Contact holes 76, 74, 78, and 72 are formed to expose the pattern 64, respectively.

Finally, as shown in Figs. 8 to 10, a 400 kHz to 500 kHz thick IZO or ITO layer is deposited and etched using a fourth mask to etch the drain electrode 66 and the contact holes 72 and 76. The data pad 68 at the pixel electrode 82 and the auxiliary gate pad 84 connected to the gate pad 24 through the contact hole 74 and the contact hole 78 electrically connected with the conductive pattern 64 for the storage capacitor. ) To form an auxiliary data pad 88.

In the second embodiment of the present invention, the data wirings 62, 64, 65, 66, and 68 and the contact layer patterns 55, 56, 58 and the semiconductor pattern 42 below the data wirings 62, 64, 65, 66, and 68, as well as the effects of the first embodiment. , 48) may be formed using one mask, and the source electrode 65 and the drain electrode 66 may be separated in this process to simplify the manufacturing process.

As described above, according to the present invention, by delaying the exposure of the molybdenum-based data line to the etching gas through the contact hole, it is possible to prevent the data line from being disconnected or eroded.

Claims (8)

Stacking and patterning a conductive material for a gate wiring on an insulating substrate to form a gate wiring including a gate line, a gate electrode connected to the gate line, and a gate pad; Forming a gate insulating film, Forming a semiconductor layer on the gate insulating layer; Stacking and patterning the conductive material for the data wiring, a data line crossing the gate line, a source electrode connected to the data line and adjacent to the gate electrode, a drain electrode located opposite the source electrode with respect to the gate electrode, and Forming a data line including a data pad connected to the data line; Stacking and patterning a passivation layer to form first to third contact holes exposing the gate pad, the data pad, and the drain electrode, respectively; Forming a pixel electrode electrically connected to the drain electrode through the third contact hole, The first to third contact hole forming steps may be formed by a photolithography process using photoresist patterns having partially different thicknesses. In claim 1, The photoresist pattern includes a first portion having a first thickness, a second portion having almost no thickness, and a third portion having a second thickness greater than the first thickness and excluding the first and second portions. Method for manufacturing a thin film transistor substrate for a device. In claim 2, In the photolithography process, the photoresist pattern is formed using a photomask including a first region, a second region having a higher transmittance than the first region, and a third region having a lower transmittance than the first region. Method for manufacturing a thin film transistor substrate for a device. In claim 3, The method of claim 1, wherein the first portion is formed in the second and third contact holes and the second portion corresponds to the third contact hole in the photolithography process. In claim 4, A method of manufacturing a thin film transistor substrate for a liquid crystal display device, in which a slit pattern smaller than the resolution of a translucent film or an exposure machine is formed in the photomask in order to differently control the transmittance of the first to third regions. In claim 1, And the data line and the semiconductor layer are formed by a photolithography process using a photoresist pattern having a partially different thickness. In claim 1, And the conductive material for data wiring comprises an aluminum-based or molybdenum-based metal. In claim 1, And the pixel electrode is formed of IZO or ITO.