KR100878263B1 - thin film transistor array panel for liquid crystal display and manufacturing method thereof - Google Patents

Abstract

A gate line including a gate line, a gate electrode, and a gate pad formed of a double layer of a lower transparent conductive film and an upper opaque conductive film is formed on an insulating substrate, and a storage capacitor electrode formed of a transparent conductive film is formed between the gate lines. It is. A gate insulating film is formed on the gate wiring and the storage capacitor electrode, and a semiconductor layer and an ohmic contact layer are sequentially formed on the gate insulating film. A data line including a data line, a source electrode, a drain electrode, and a data pad is formed on the ohmic contact layer, and a protective film is formed thereon. A contact hole for exposing the drain electrode, the gate pad, and the data pad is formed in the passivation layer, and a pixel electrode overlapping the storage capacitor electrode, an auxiliary gate pad and an auxiliary data pad connected to the gate pad and the data pad, respectively, are formed on the passivation layer. It is. The storage capacitor electrode overlaps the pixel electrode with an insulating film therebetween to form the storage capacitor. Since the storage capacitor electrode is formed of a transparent conductive film, the aperture ratio does not decrease.

Storage capacitor electrode, transparent conductive film, aperture ratio

Description

Thin film transistor substrate for liquid crystal display device and manufacturing method therefor {thin film transistor array panel for liquid crystal display and manufacturing method}

1 is a layout view illustrating a thin film transistor substrate for a liquid crystal display according to a first embodiment of the present invention.

2 is a cross-sectional view taken along the line II-II in FIG.

3A is a cross-sectional view illustrating a thin film transistor substrate in a first step of manufacturing according to the first embodiment of the present invention;

3B and 3C are cross-sectional views sequentially showing the processes in the next step of FIG. 3A in the order thereof;

4A is a layout view in the next step of FIG. 3C;

4B is a cross sectional view taken along line IVb-IVb in FIG. 4A;

FIG. 5A is a layout view of the next step of FIG. 4A;

FIG. 5B is a cross sectional view taken along the line Vb-Vb in FIG. 5A;

FIG. 6a is a layout view in the next step of FIG. 5a;

FIG. 6B is a cross sectional view taken along the line VIb-VIb in FIG. 6A;

FIG. 7a is a layout view in the next step of FIG.                 

FIG. 7B is a cross sectional view taken along the line VIIb-VIIb in FIG. 7A;

8 is a layout view illustrating a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment of the present invention.

9 is a cross-sectional view taken along line VII-VII in FIG. 8,

10A is a cross-sectional view illustrating a thin film transistor substrate at a first stage of manufacture in accordance with a second embodiment of the present invention;

10B and 10C are cross-sectional views sequentially showing the processes in the next step of FIG. 10A in the order thereof;

FIG. 11A is a layout view in the next step of FIG. 10C;

FIG. 11B is a cross-sectional view taken along the line XIB-XIB in FIG. 11A,

12A is a layout view at the next step of FIG. 11A;

FIG. 12B is a cross sectional view taken along the line XIIb-XIIb in FIG. 12A;

FIG. 13A is a layout view in the next step of FIG. 12A;

FIG. 13B is a cross sectional view taken along line XIIIb-XIIIb in FIG. 13A;

FIG. 14a is a layout view in the next step of FIG. 13a;

FIG. 14B is a cross-sectional view taken along line XIVb-XIVb in FIG. 14A.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor substrate for a liquid crystal display device and a manufacturing method thereof, and more particularly, to a thin film transistor substrate for a liquid crystal display device and a method for manufacturing the same, which improve an aperture ratio.

The liquid crystal display is one of the most widely used flat panel display devices. The liquid crystal display includes two glass substrates on which electrodes are formed and a liquid crystal layer interposed therebetween. A display device for controlling the amount of light transmitted by rearranging them.

One substrate of such a liquid crystal display device generally includes a thin film transistor for switching a voltage applied to an electrode. In addition to the thin film transistor, the substrate includes a wiring including a gate line and a data line and a gate line receiving a signal from the outside. And gate pads and data pads respectively transferred to the data lines. A pixel electrode electrically connected to the thin film transistor is formed in the pixel region defined by the intersection of the gate line and the data line.

In such a liquid crystal display, in order to form the storage capacitor, a gate line of a front end is used or a storage capacitor line is formed of the same layer as the gate line or the data line, and the insulating layer is interposed between the pixel electrode. In this case, since the gate line and the data line are formed of an opaque conductive material, there is a problem that the aperture ratio as much as overlapping with the pixel electrode is reduced.

An object of the present invention is to improve the aperture ratio of a liquid crystal display device.

In order to achieve this object, in the present invention, a storage capacitor electrode is formed using a transparent conductive film.

According to the present invention, a gate line including a gate line formed of a lower transparent conductive film and an upper opaque conductive film and a gate electrode that is part of the gate line is formed on the insulating substrate. A storage capacitor electrode made of a transparent conductive film is formed between the gate lines. The gate wiring and the storage capacitor electrode are covered with a gate insulating film, and a semiconductor layer and an ohmic contact layer are sequentially formed on the gate insulating film. A data line including a data line, a source electrode that is a part of the data line, and a drain electrode separated from the source electrode is formed on the ohmic contact layer. A protective film having a contact hole for exposing the drain electrode is formed, and a pixel electrode overlapping the storage capacitor electrode is formed on the protective film.

Here, the storage capacitor electrode may be connected to the gate line.

On the other hand, the storage capacitor electrode is formed of a transparent conductive film between the gate lines, it may be connected to the storage capacitor line.

When manufacturing a thin film transistor substrate for a liquid crystal display device according to the present invention, first, a transparent conductive film and an opaque conductive film are sequentially formed on an insulating substrate, and a photosensitive film pattern having a different thickness is formed according to a position. Next, using the photosensitive film pattern as a mask, the opaque conductive film and the transparent conductive film are etched to form a gate wiring including a gate line and a gate electrode formed of a double layer of a transparent conductive film and an opaque conductive film, and a storage capacitor electrode made of a transparent conductive film. Form. Next, a gate insulating film, a semiconductor layer, and an ohmic contact layer are sequentially formed. Next, a data line including a data line, a source electrode and a drain electrode is formed, and a protective film having contact holes for exposing the drain electrode is formed. Next, a pixel electrode connected to the drain electrode is formed.

In this case, the photoresist pattern may include a first portion disposed above the storage capacitor electrode, a second portion thicker than the first portion, and a second portion disposed above the gate wiring, and having no thickness and located at the remaining portions except the first and second portions. The photomask comprising a third portion and used to form the photoresist pattern includes a first region, a second region having a lower transmittance than the first region, and a third region having a higher transmittance than the first region. The first, second and third regions of the mask are preferably aligned to correspond to the first, second and third portions of the photoresist pattern, respectively.

In the present invention, the storage capacitor electrode can be formed of a transparent conductive film to improve the aperture ratio.

Next, a thin film transistor substrate for a liquid crystal display device and a method for manufacturing the same according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the same. do.

First, the structure of the liquid crystal display according to the first exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.

1 is a layout view illustrating a thin film transistor substrate for a liquid crystal display according to a first exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along line II-II of FIG. 1.                     

1 and 2, a transparent conductive film 211 such as indium tin oxide (ITO) or indium zinc oxide (IZO), aluminum (Al), aluminum alloy (Al alloy), molybdenum, etc., is formed on the insulating substrate 10. Gate wirings 21, 22, and 23 formed of a double film of an opaque conductive film 212 such as (Mo) or molybdenum-tungsten alloy (MoW) are formed. The gate wiring is connected to the gate line 21 extending in the horizontal direction, the gate electrode 22 that is part of the gate line 21, and the end of the gate line 21, and receives a scan signal from the outside to the gate line 21. A gate pad 23. On the substrate 10, the storage capacitor electrodes 25 and 26 made of the same layer as the transparent conductive film 211 of the gate wirings 21, 22, and 23 extend in the longitudinal direction from the gate line 21.

The gate insulating film 30 made of silicon nitride (SiN _x ) is formed on the gate wirings 21, 22, 23, and the storage capacitor electrodes 25, 26.

A semiconductor layer 41 made of a semiconductor such as amorphous silicon is formed on the gate insulating film 30, and a resistivity made of a semiconductor such as amorphous silicon doped with n-type impurities such as phosphorus (P) is formed on the semiconductor layer 41. The contact layers 52 and 53 are formed separated from both sides with respect to the gate electrode 22.

On the ohmic contacts 52 and 53, data wirings 61, 62, 63 and 64 made of a metal or a conductor such as aluminum or an aluminum alloy, molybdenum or molybdenum-tungsten alloy, chromium and tantalum are formed. The data line includes a data line 61 extending in the vertical direction, a source electrode 62 which is a part of the data line 61, a drain electrode 63 facing the source electrode 62 around the gate electrode 22, and data. And a data pad 64 connected to the line 61 to receive an image signal from the outside and transmit the image signal to the data line 61.

The data lines 61, 62, 63, and 64 may be formed in a single layer, but may be formed in a double layer or a triple layer. In the case of forming more than two layers, it is preferable that one layer is formed of a material having a low resistance and the other layer is formed of a material having good contact properties with other materials.

A protective film 70 made of silicon nitride or an organic insulating film is formed on the data lines 61, 62, 63, and 64 and the gate insulating film 30. The passivation layer 70 has not only a contact hole 73 exposing the gate pad 23 together with the gate insulating film 30, but also a contact hole 74 and a drain electrode 63 exposing the data pad 64. It has a contact hole 72 that exposes.

The pixel electrode 80, the auxiliary gate pad 83, and the auxiliary data pad 84 made of a transparent conductive material such as ITO or IZO are formed on the passivation layer 70.

The pixel electrode 80 is connected to the drain electrode 63 through the contact hole 72 to receive an image signal, and overlaps with the storage capacitor electrodes 25 and 26 connected to the gate line 21 of the previous stage. Forming capacity. The auxiliary gate pad 83 and the auxiliary data pad 84 are connected to the gate pad 23 and the data pad 64 through the contact holes 73 and 74, respectively, which are the pads 23 and 64 and the external circuit. It serves to complement the adhesion with the device and to protect the pads 23 and 64.

As described above, in the first exemplary embodiment of the present invention, the pixel electrode 80 overlaps with the storage capacitor electrodes 25 and 26 to form the storage capacitor, and the storage capacitor electrodes 25 and 26 are connected to the gate wirings 21, 22, and the like. Since the lower conductive film 211 is a transparent conductive film, the aperture ratio does not decrease due to the storage capacitor electrodes 25 and 26.

Next, a method of manufacturing a thin film transistor substrate for a liquid crystal display according to a first exemplary embodiment of the present invention will be described with reference to FIGS. 3A to 7B and FIGS. 1 and 2.

First, as shown in FIG. 3A, a transparent conductive film 211, such as ITO or IZO, and an opaque conductive film 212, such as aluminum or an aluminum alloy, molybdenum or molybdenum-tungsten alloy, are sequentially deposited on the insulating substrate 10, and then the photosensitive film is deposited. Apply. Next, the photosensitive film is irradiated with light using a mask 100 having a different transmittance depending on the location, and then developed to form photosensitive film patterns 112 and 114 having different thicknesses according to the location. In this case, the thickness of the second portion 114 located in the portion C of the photoresist patterns 112 and 114 where the storage capacitor electrodes 25 and 26 are to be formed is a portion where the gate wirings 21, 22, and 23 are to be formed ( It is thinner than the first portion 112 located in A), and the photosensitive film of the other portion B is removed to expose the conductive film 212.

As such, there may be various methods of varying the thickness of the photoresist layer according to the position. In order to control the light transmittance in the C region, a slit or lattice-shaped pattern is mainly formed or a semi-transmissive layer is used.

Next, the photoresist patterns 112 and 114 and the conductive films 211 and 212 are etched.

First, as shown in FIG. 3B, the opaque conductive film 212 and the transparent conductive film 211 not covered by the photoresist patterns 112 and 114 are sequentially etched by wet etching.

Next, as shown in FIG. 3C, the photoresist patterns 112 and 114 are ashed to remove the photoresist pattern 114 of the C portion to expose the opaque conductive layer 212, and then the remaining photoresist pattern 112 is removed. 4A and 4B, the gate line 21 including the double layers 211 and 212, the gate electrode 22, and the gate pad 23 may be formed into a transparent conductive layer 211. The sustained capacitor electrodes 25 and 26 are formed.

Next, as shown in FIGS. 5A and 5B, the gate insulating layer 30, the amorphous silicon layer, and the amorphous silicon layer doped with the n-type impurity are respectively 1,500 kPa to 5,000 using chemical vapor deposition (CVD). 증착, 500 Å to 1,500 Å and 300 Å to 600 Å in thickness, and the two upper layers are patterned by a photolithography process using a mask to form a semiconductor layer 41 and an ohmic contact layer 51.

6A and 6B, a data wiring conductor or metal is deposited to a thickness of 1,500 kV to 3,000 kV by a method such as sputtering, and patterned by a photolithography process using a mask to form a data line 61 and a source. A data line including an electrode 62, a drain electrode 63, and a data pad 64 is formed. Next, the ohmic contact layer 51 not covered by the source electrode 62 and the drain electrode 63 is removed to separate the two portions 52 and 53.

Next, as shown in FIGS. 7A and 7B, silicon nitride is deposited or an organic insulating film is coated to form a protective film 70, and then patterned by a photolithography process using a mask to form a drain electrode 63 and a gate pad 23. And contact holes 72, 73, and 74 that expose the data pads 64, respectively.

Next, as shown in FIGS. 1 and 2, a transparent conductive material such as ITO or IZO is deposited on the passivation layer 70 to a thickness of 400 μs to 500 μs by a sputtering method, and patterned by a photolithography process using a mask. The pixel electrode 80, the auxiliary gate pad 83, and the auxiliary data pad 84 are formed.

In the first embodiment of the present invention, a case in which the storage capacitor electrodes 25 and 26 are formed between the gate lines 21 adjacent to the data line 61 by one pair for each pixel region is given as an example. The shape may be formed in various other shapes. For example, the gate line 21 of the front end may be partially extended in width to form the storage capacitor electrode, and the portion may overlap the pixel electrode.

Next, a structure of a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment of the present invention will be described with reference to FIGS. 8 and 9.

8 and 9, a double layer of a transparent conductive film 211, such as ITO or IZO, and an opaque conductive film 212, such as aluminum or an aluminum alloy, molybdenum or molybdenum-tungsten alloy, is formed on the insulating substrate 10. The gate wirings 21, 22, and 23 which were formed are formed. The gate wiring is connected to the gate line 21 extending in the horizontal direction, the gate electrode 22 that is part of the gate line 21, and the end of the gate line 21, and receives a scan signal from the outside to the gate line 21. A gate pad 23. A storage capacitor line 25 formed of the lower layer 211 of the gate lines 21, 22, and 23 is formed to be parallel to the gate line 21 between the gate lines 21, and the storage capacitor line 25 is formed. The storage capacitor electrode 26 which is a branch line is formed.

A gate insulating film 30 made of silicon nitride is formed on the gate wirings 21, 22, 23, the storage capacitor line 25, and the storage capacitor electrode 26.

A semiconductor layer 41 made of a semiconductor such as amorphous silicon is formed on the gate insulating film 30, and a resistivity made of a semiconductor such as amorphous silicon doped with n-type impurities such as phosphorus (P) is formed on the semiconductor layer 41. The contact layers 52 and 53 are formed separated from both sides with respect to the gate electrode 22.

On the ohmic contacts 52 and 53, data wirings 61, 62, 63 and 64 made of a metal or a conductor such as aluminum or an aluminum alloy, molybdenum or molybdenum-tungsten alloy, chromium and tantalum are formed. The data line includes a data line 61 extending in the vertical direction, a source electrode 62 which is a part of the data line 61, a drain electrode 63 facing the source electrode 62 around the gate electrode 22, and data. And a data pad 64 connected to the line 61 to receive an image signal from the outside and transmit the image signal to the data line 61.

A protective film 70 made of silicon nitride or an organic insulating film is formed on the data lines 61, 62, 63, and 64 and the gate insulating film 30. In the passivation layer 70, contact holes 72, 73, and 74 are formed to expose the drain electrode 63, the gate pad 23, and the data pad 64.

The pixel electrode 80 and the gate pad connected to the drain electrode 63 through the contact hole 72 and overlapping the storage capacitor line 25 and the storage capacitor electrode 26 are formed on the passivation layer 70 to form the storage capacitor. An auxiliary gate pad 83 and an auxiliary data pad 84 are formed which are connected to the 23 and the data pad 64 through the contact holes 73 and 74, respectively.

Next, a method of manufacturing a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment of the present invention will be described with reference to FIGS. 10A to 14B and FIGS. 8 and 9.

First, as shown in FIG. 10A, a transparent conductive film 211, such as ITO or IZO, and an opaque conductive film 212, such as aluminum or an aluminum alloy, molybdenum or molybdenum-tungsten alloy, are sequentially deposited on the insulating substrate 10, and then the photosensitive film is deposited. Apply. Next, the photosensitive film is irradiated with light using a mask 100 having a different transmittance depending on the location, and then developed to form photosensitive film patterns 112 and 114 having different thicknesses according to the location. In this case, the thickness of the second portion 114 located in the portion C of the photoresist patterns 112 and 114 where the storage capacitor line 25 and the storage capacitor electrode 26 are to be formed is the gate wirings 21, 22, and 23. The thickness is thinner than the first portion 112 positioned in the portion A to be formed, and the photosensitive film of the other portion B is removed to expose the conductive film 212.

As a method of varying the thickness of the photoresist film according to the position, as in the first embodiment of the present invention, a slit or lattice-shaped pattern or a semi-transmissive film may be used to control the amount of light transmission in the C region.

Next, the photoresist patterns 112 and 114 and the conductive films 211 and 212 are etched.

First, as shown in FIG. 10B, the opaque conductive film 212 and the transparent conductive film 211 not covered by the photosensitive film patterns 112 and 114 are sequentially etched by wet etching.

Next, as shown in FIG. 10C, the photoresist patterns 112 and 114 are ashed to remove the C portion photoresist pattern 114 to expose the opaque conductive film 212, and then the remaining photoresist pattern 112 is exposed. 11A and 11B, the gate wiring 21 including the gate line 21, the gate electrode 22, and the gate pad 23 including the double layers 211 and 212 and the transparent conductive film 211 are removed. The storage capacitor line 25 and the storage capacitor electrode 26 formed of the same are formed.

Next, as shown in FIGS. 12A and 12B, the gate insulating layer 30, the amorphous silicon layer, and the amorphous silicon layer doped with n-type impurities are sequentially deposited by using a chemical vapor deposition method, and the upper two layers are formed by using a mask. The semiconductor layer 41 and the ohmic contact layer 51 are formed by patterning by a photolithography process.

Next, as shown in FIGS. 13A and 13B, a conductor or a metal for data wiring is deposited by a method such as sputtering, and patterned by a photolithography process using a mask to form a data line 61, a source electrode 62, and a drain electrode ( 63) and a data line including the data pad 64 is formed. Next, the ohmic contact layer 51 not covered by the source electrode 62 and the drain electrode 63 is removed to separate the two portions 52 and 53.

Next, as shown in FIGS. 14A and 14B, silicon nitride is deposited or an organic insulating film is coated to form a protective film 70, and then patterned by a photolithography process using a mask to form a drain electrode 63 and a gate pad 23. And contact holes 72, 73, and 74 that expose the data pads 64, respectively.

Next, as shown in FIGS. 8 and 9, a transparent conductive material such as ITO or IZO is deposited on the passivation layer 70 by a sputtering method, and patterned by a photolithography process using a mask to form the pixel electrode 80. The auxiliary gate pad 83 and the auxiliary data pad 84 are formed.

As described above, in the present invention, the wiring for forming the storage capacitance can be formed of a transparent conductive film to improve the aperture ratio.

Claims (5)

A gate wiring formed on an insulating substrate, the gate wiring including a gate line formed of a lower transparent conductive film and an upper opaque conductive film and a gate electrode that is part of the gate line; A storage capacitor electrode formed on the insulating substrate and formed of the transparent conductive film and connected to the gate line; A gate insulating film covering the gate wiring and the storage capacitor electrode, A semiconductor layer formed on the gate insulating film, An ohmic contact layer formed on the semiconductor layer, A data line having a source electrode formed on the ohmic contact layer, a data line comprising a drain electrode separated from the source electrode and formed on the ohmic contact layer; A protective film formed on the data wiring, A pixel electrode formed on the passivation layer and overlapping the storage capacitor electrode Including, The vertical side of the pixel electrode is positioned between the data line and the storage capacitor electrode. delete A gate wiring formed on an insulating substrate, the gate wiring including a gate line formed of a lower transparent conductive film and an upper opaque conductive film and a gate electrode that is part of the gate line; A storage capacitor line formed on the insulating substrate and formed of the transparent conductive film and positioned between the gate lines and having a storage capacitor electrode; A gate insulating film covering the gate wiring and the storage capacitor electrode, A semiconductor layer formed on the gate insulating film, An ohmic contact layer formed on the semiconductor layer, A data line having a source electrode formed on the ohmic contact layer, a data line comprising a drain electrode separated from the source electrode and formed on the ohmic contact layer; A protective film formed on the data wiring, A pixel electrode formed on the passivation layer and overlapping the storage capacitor electrode Thin film transistor substrate for a liquid crystal display device comprising a. Sequentially forming a transparent conductive film and an opaque conductive film on the insulating substrate, Forming a photoresist pattern on the opaque conductive film, the photoresist pattern having a first portion and a second portion having a thickness greater than that of the first portion, The opaque conductive layer and the transparent conductive layer are etched using the photosensitive layer pattern as a mask, and the gate line and the transparent electrode are formed of a gate line and a gate electrode including a double layer of the transparent conductive layer and the opaque conductive layer. Forming a storage capacitor electrode connected to the gate line; Forming a gate insulating film on the gate wiring and the storage capacitor electrode; Forming a semiconductor layer on the gate insulating film, Forming an ohmic contact layer over the semiconductor layer; Forming a data line including a data line having a source electrode and a drain electrode on the ohmic contact layer and the gate insulating layer; Forming a protective film having a contact hole exposing the drain electrode on the data line; Forming a pixel electrode on the passivation layer through the drain electrode and the contact hole and having a vertical side between the data line and the storage capacitor electrode; Including, And the first portion of the photosensitive film pattern corresponds to the gate wiring and the storage capacitor electrode. In claim 4, The photomask used in the forming of the photoresist pattern includes a first region, a second region having a lower transmittance than the first region, and a third region having a higher transmittance than the first region. The first and second regions are arranged to correspond to the first and second portions of the photoresist pattern, respectively.

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