KR100915237B1 - Method for manufacturing thin film transistor array panel and mask for manufacturing the panel - Google Patents

Abstract

A gate line is formed over the insulating substrate, and a gate insulating film is stacked over the insulating substrate. Subsequently, the semiconductor and the ohmic contact are sequentially stacked, a data line and a drain electrode are formed thereon, then a protective film is laminated and a photoresist pattern is formed thereon. In this case, the photoresist pattern has a thickness thinner than the first portion and the first portion, and has a thickness smaller than that of the second portion and the second portion corresponding to a portion of the drain electrode, most of the region surrounded by the gate line and the data line, and an end portion of the gate line. And a third portion corresponding to the. The mask for forming the photosensitive film pattern has a slit pattern in a region corresponding to the second portion, wherein the slit pattern overlapping the drain electrode has a different width and spacing of the slit pattern not overlapping the drain electrode. Through this, the photosensitive film of the second portion may be developed to have a uniform thickness. Following. A pixel electrode connected to the drain electrode is formed.

Description

Method for manufacturing thin film transistor array panel and mask therefor {METHOD FOR MANUFACTURING THIN FILM TRANSISTOR ARRAY PANEL AND MASK FOR MANUFACTURING THE PANEL}

The present invention relates to a method of manufacturing a thin film transistor array panel and a mask therefor.

The liquid crystal display is one of the most widely used flat panel display devices. The liquid crystal display includes two substrates on which electrodes are formed and a liquid crystal layer interposed therebetween, and rearranges the liquid crystal molecules of the liquid crystal layer by applying a voltage to the electrode. By controlling the amount of light transmitted.

Among the liquid crystal display devices, a liquid crystal display device having a thin film transistor for forming an electrode on each of two substrates and switching a voltage applied to the electrode is used.

In general, a substrate including a thin film transistor includes a wiring line including a gate line for transmitting a scan signal and a data line for transmitting an image signal, and a scan signal or an image signal from an external source, respectively, to the gate line and the data line. A gate pad and a data pad to be transferred are formed, and a pixel electrode electrically connected to the thin film transistor is formed in a pixel region defined by crossing the gate line and the data line.

A display panel on which a thin film transistor is formed is generally manufactured through a photolithography process using a mask, and five or six masks are usually used. In this case, in order to reduce the production cost, it is preferable to reduce the number of masks. For this purpose, a photosensitive film pattern including a portion having an intermediate thickness is formed by using a mask having a semi-transmissive area capable of adjusting light transmittance, and etching the same. A method of patterning two or more thin films using as a mask has been proposed.

In addition, by using a photosensitive film pattern having a medium thickness in order to prevent the undercut at the bottom of the wiring when exposing the wiring to connect the different conductive films or the end of the wiring connected to the external drive circuit It is used to gently form the profile of the contact portion by preventing the lower layer from being etched.

At this time, a portion having a middle thickness among the photoresist patterns may be prevented from being etched so as not to expose the conductive film or the insulating film positioned at the lower portion thereof, and then completely removed through the ashing process to use the thick left portion as an etching mask. Should be. Therefore, it is desirable to control the manufacturing process so that the thickness of the portion having the intermediate thickness is uniformly developed to secure the etching process and the manufacturing process has a uniform reproducibility.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a method for manufacturing a thin film transistor array panel having a stable etching process and a uniform reproducibility and a mask therefor.

In order to solve this problem, in the manufacturing process of the thin film transistor array panel according to the present invention, a slit pattern for controlling light transmittance is formed at different widths and intervals in a region overlapping the wiring and a region not overlapping the wiring. have.

More specifically, in the mask according to the embodiment of the present invention, a plurality of slit patterns are formed in any region in order to control light transmittance, wherein the slit patterns have two or more different widths and spacings.

In the method for manufacturing a thin film transistor array panel according to an exemplary embodiment of the present invention using such a mask, first, a gate line including a gate electrode is formed on an insulating substrate, and a gate insulating film is formed thereon. Subsequently, a semiconductor is formed, and a drain electrode which is opposite to the source electrode with respect to the data electrode and the gate electrode which intersects the gate line and includes the source electrode is formed thereon. Subsequently, a passivation layer is formed to cover the data line and the drain electrode, and the passivation layer is patterned to form a contact hole that exposes a portion of the drain electrode and a gate insulating layer adjacent to the boundary line of the drain electrode, and is connected to the drain electrode through the contact hole on the passivation layer. A pixel electrode is formed. The contact hole is formed by a photolithography process using a mask, and the mask includes at least a first region corresponding to the data line and the semiconductor, a plurality of slit patterns are disposed, and a second region corresponding to the contact hole and corresponding to an end portion of the gate line. In the photolithography process, some slit patterns overlapping the drain electrode and the remaining slit patterns not overlapping the drain electrode have different widths and spacings.

Here, the first region may not transmit light, the second region may transmit only part of the light, and the third region may transmit light completely, and may be exposed and exposed using a mask in a photolithography process. The developed photoresist pattern is positive, and the photoresist pattern is at least a first portion corresponding to the data line and the semiconductor, at least a second portion corresponding to the contact hole and having a thickness smaller than the first portion, and a second portion corresponding to the end of the gate line. It is preferable to include a third portion having a smaller thickness.

The photoresist pattern may further include a fourth portion corresponding to an end portion of the data line and having a thickness smaller than that of the first portion.

The gate line or data line is preferably formed of a lower conductive film of chromium or molybdenum or molybdenum alloy and an upper conductive film of aluminum or aluminum alloy, and preferably, the upper conductive film is removed before the pixel electrode forming step.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a portion of a layer, film, region, plate, etc. is said to be "on top" of another part, this includes not only when the other part is "right on" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

Now, a method of manufacturing a thin film transistor array panel and a mask therefor according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

First, the structure of a thin film transistor array panel completed through a manufacturing process according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.

1 is a layout view illustrating a structure of a thin film transistor array panel completed through a manufacturing process according to a first exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along the line II-II ′ of FIG. 1.

An upper conductive film made of a conductive material of aluminum or an aluminum alloy having a low specific resistance and a lower conductive film 201 made of chromium, molybdenum or molybdenum alloy, tantalum or titanium, etc. having excellent contact properties with other materials on the insulating substrate 110 ( A plurality of gate lines 121 formed of 202 are formed. One end portion 125 of the gate line 121 transmits a gate signal from the outside to the gate line 121, and the plurality of branches 123 of each gate line 121 are the gate electrode 123 of the thin film transistor. To achieve. In this case, a part of the gate line 121 having a width wider than that of the other couple overlaps the conductor 177 for a storage capacitor connected to the pixel electrode 191 formed later to form a storage capacitor, and the storage capacitor here If this is not sufficient, the storage electrode line separated from the gate line 121 may be added.

On the substrate 110, a gate insulating layer 140 made of silicon nitride (SiN _x ) covers the gate line 121.

A linear semiconductor 150 made of hydrogenated amorphous silicon or the like is formed on the gate insulating layer 140 of the gate electrode 125, and n + hydrogenation in which silicide or n-type impurities are heavily doped is formed on the semiconductor 150. A plurality of pairs of ohmic contacts 163 and 165 made of amorphous silicon are formed. Each pair of ohmic contacts 163 and 165 are separated from each other with respect to the gate line 121.

A plurality of data lines 171 and a plurality of drain electrodes 175 are formed on the ohmic contacts 163 and 165 and the gate insulating layer 140. The data line 171 and the drain electrode 175 include a conductive film made of a low resistance conductive material such as aluminum or silver. The data line 171 mainly extends in the vertical direction and crosses the gate line 121. The plurality of branches 173 of the data line 171 are positioned on one of the pair of ohmic contacts 163 and 165 and extends to the gate electrode 123 to extend the source electrode 173 of the thin film transistor. To achieve. One end portion 179 of the data line 171 transfers an image signal from the outside to the data line 171. The drain electrode 175 of the thin film transistor is separated from the data line 171 and positioned above the ohmic contact 165 opposite to the source electrode 173 with respect to the gate electrode 123. In addition, a conductive capacitor conductor 177 is formed on the same layer as the data line 171 and electrically connected to the pixel electrode 191 and overlaps the gate line 121 as described above.

The data line 171 and the drain electrode 175 are preferably formed of a single film made of aluminum or an aluminum alloy, but may be formed of two or more layers. In the case of forming more than two layers, it is preferable that one layer is made of a material having a low resistance and the other layer is made of a material having a low contact resistance with other materials, especially IZO or ITO. Examples thereof include Al (or Al alloy) / Cr or Al (or Al alloy) / Mo (or Mo alloy), and the like. In an embodiment of the present invention, the data line 171 and the drain electrode 175 may be formed of chromium. And a double film of the lower conductive film 701 and the upper conductive film 702 of aluminum-neodymium alloy.

A passivation layer 180 made of silicon nitride or an organic material having excellent planarization characteristics or an inorganic material having a dielectric constant of 4.0 or less and deposited by chemical vapor deposition on the data line 171 and the drain electrode 175 and the semiconductor 150 that is not covered by the passivation layer 180. ) Is formed.

In the passivation layer 180, contact holes 185 and 189 respectively exposing the drain electrode 175 and the end portion 179 of the data line 171 are formed, respectively, and the gate line 121 together with the gate insulating layer 140. A contact hole 182 is formed that exposes the end portion 125 of the. Here, the contact holes 182, 185, and 189 are boundary lines between the drain electrodes 175, the gate lines 121, and the end portions 125 and 179 of the data lines 171, respectively, which are used as connecting portions connected to other conductive layers. And the upper layers 202 and 702 of the end portions 125 and 179 of the drain electrode 175 and the gate line 121 and the data line 171 in the contact holes 182, 185 and 189. ), The gate line 121 and the lower films 201 and 701 of the data line 171 having excellent contact characteristics with the ITO or IZO formed later can be secured in a large area. At this time, the gate insulating layer 140 remains without being cut under and around the drain electrode 175 and the end portion 179 of the data line 171 and is exposed through the contact hole 189. As a result, a profile of another conductive layer after connecting to the drain electrode 175 and the end portion 179 of the data line 171 can be formed smoothly.

A pixel electrode 191 is formed on the passivation layer 180 to be electrically connected to the drain electrode 175 through the contact hole 185 and positioned in the pixel region surrounded by the gate line 121 and the data line 171. have. Further, on the passivation layer 180, the gate contact auxiliary member 192 connected to the end portion 125 of the gate line 121 and the end portion 179 of the data line 171 through the contact holes 182 and 189, respectively. ) And a data contact assistant member 199 are formed. Here, the transparent electrode 191 and the contact auxiliary members 192 and 199 are made of indium tin oxide (ITO) or indium zinc oxide (IZO), which are transparent conductive materials.

In this structure, the pixel electrode 191, the gate contact auxiliary member 192, and the data contact auxiliary member 199 may have end portions 125 and 179 of the drain electrode 175, the gate line 121, and the data line 171, respectively. Contacting the lower layers 201 and 701 of the C-type) can minimize the contact resistance at the contact portion where the conductive layers of the different layers contact each other. In addition, since there is no undercut under the end portions 125 and 179 of the drain electrode 175, the gate line 121, and the data line 171, the pixel electrode 191, the gate contact auxiliary member 192, and the data contact. The auxiliary member 199 can be prevented from being disconnected due to the step, and their profile can be secured gently. As a result, in the subsequent module process, the driving integrated circuit connected to the gate contact auxiliary member 192 and the data contact auxiliary member 199 may be stably mounted, thereby improving reliability of the contact portion.

Next, a method of manufacturing the thin film transistor array panel for a liquid crystal display according to the first exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2 and FIGS. 3A to 10.

3A, 4A, 5A, and 7A are layout views of a thin film transistor array panel in which an intermediate process of manufacturing a thin film transistor array panel for a liquid crystal display device according to a first embodiment of the present invention is performed according to a process sequence thereof, and FIG. 3B is FIG. 3A. 4b is a cross-sectional view taken along the line IVb-IVb 'in FIG. 4a, and is a cross-sectional view showing the next step in FIG. 3b, and FIG. 5b is a Vb- in FIG. 5a. 4B is a cross-sectional view illustrating the next step of FIG. 4B as shown along the line Vb ′, and FIG. 6 is a cross-sectional view illustrating the next step of FIG. 5B as shown along the line Vb-Vb ′ in FIG. 5A. FIG. 7B is a cross-sectional view illustrating the next step of FIG. 6 taken along the line VIIb-VIIb ′ in FIG. 7A, and FIG. 8 is a cross-sectional view of a mask in the method of manufacturing a thin film transistor array panel according to the first exemplary embodiment of the present invention. Slit Pattern and Drain Electrode FIG. 9 is a cross-sectional view illustrating an alignment relationship thereof, and FIG. 9 is a cross-sectional view illustrating the next step of FIG. 7B as shown in FIG. 7A along the line VIIb-VIIb ', and FIG. 9 is a cross-sectional view illustrating the next step of FIG. 9 as a cutaway view.

First, as shown in FIGS. 3A and 3B, by using a target including Al-Nd containing 2 at% of Nd in the lower conductive film 201 of chromium and an aluminum alloy metal on the substrate 110. The upper conductive film 202 is sequentially stacked and patterned by sputtering to a thickness of about 2,500 Å to form a plurality of gate lines 121 in a tapered structure having an inclination angle in a range of 20 to 80 °.

Next, as shown in FIGS. 4A and 4B, three layers of a gate insulating layer 140 made of silicon nitride, a semiconductor layer made of amorphous silicon, and a doped amorphous silicon layer are successively laminated, and the semiconductor layer is formed by a patterning process using a mask. The doped amorphous silicon layer is formed on the gate insulating layer 140 facing the gate electrode 125 to form the doped amorphous silicon layer 160 with the semiconductor 150. Here, the gate insulating film 140 is preferably formed by stacking silicon nitride in a thickness of about 2,000 to 5,000 Pa at a temperature range of 250 to 1500 ° C.

Next, as shown in FIGS. 5A to 5B, the lower conductive film 701 made of molybdenum, molybdenum alloy, chromium, or the like is about 500 kPa, and at least 2 at% of the metal of aluminum or aluminum alloy having low resistance. The upper conductive film 702 was sequentially stacked by sputtering to a thickness of about 2,500 에서 at a temperature of about 150 ° C. using an Al-Nd alloy target including Nd, and then patterned by a photo process using a mask. A plurality of data lines 171 and a plurality of drain electrodes 175 that cross the gate line 121 are formed. Each data line 171 includes a source electrode 173 extending to the upper portion of the doped amorphous silicon layer 160. The drain electrode 175 is separated from the data line 171 and faces the source electrode 173 around the gate electrode 123. Here, both the upper layer 702 and the lower layer 701 may be etched by wet etching, the upper layer 702 may be etched by wet etching, and the lower layer 701 may be etched by dry etching, and the lower layer 701 may be etched. ) Is a molybdenum or molybdenum alloy film may be patterned with the upper film 702 in one etching condition. At this time, the storage capacitor conductor 177 is also formed together.

Subsequently, portions of the doped amorphous silicon layer 160 that are not covered by the data line 171 and the drain electrode 175 are removed, so that each of the doped amorphous silicon layers 160 is formed around the gate electrode 123. The resistive contact members 163 and 165 are separated, while the portion of the semiconductor 150 underneath is exposed. Subsequently, it is preferable to perform oxygen plasma to stabilize the exposed part surface of the semiconductor 150.

Next, as shown in FIG. 6, an inorganic insulating film such as silicon nitride or an organic insulating film having a low dielectric constant is stacked to form a protective film 180, and a photosensitive film 210 is coated on top thereof by a spin coating method.

Thereafter, the photosensitive film 210 is irradiated with light through the mask 300 and then developed to form photosensitive film patterns 212 and 214 as shown in FIG. 7B. In this case, the second portion of the second region C1 corresponding to the end portion 179 of the storage capacitor conductor 177, the drain electrode 175, and the data line 171 among the photoresist patterns 212 and 214 ( 214 has a thickness thinner than the first portion 212 of the first region A1, and all of the photoresist layers are formed in the third portion of the third region B1 corresponding to the end portion 125 of the gate line 121. Remove Here, the ratio of the thickness of the photosensitive film 214 remaining in the second region C1 to the thickness of the photosensitive film 212 remaining in the first region A1 is adjusted according to the process conditions in the etching process described later.

As such, there may be various methods of varying the thickness of the photoresist layer according to the position. In order to control the light transmittance of the second region C1, a slit or lattice-shaped pattern is mainly formed or a translucent film is used. do.

In this case, the line width of the pattern located between the slits or the interval between the patterns, that is, the width of the slits, is preferably smaller than the resolution of the exposure machine used for exposure, and in the case of using a translucent film, the transmittance is different in order to control the transmittance when fabricating a mask. A thin film having a thickness or a thin film may be used.

When the light is irradiated to the photosensitive film through such a mask, the polymers are completely decomposed at the part directly exposed to the light, and the polymers are not completely decomposed because the amount of light is small at the part where the slit pattern or the translucent film is formed. In the area covered by, the polymer is hardly decomposed. Subsequently, when the photoresist film is developed, only a portion where the polymer molecules are not decomposed is left, and a portion where the light is irradiated may have a photoresist film having a middle thickness than the portion that is not irradiated with light at all. In this case, if the exposure time is extended, all molecules are decomposed, so it should not be so.

The thin photoresist 214 may be exposed to light using a photoresist film made of a reflowable material, and then exposed and exposed to a conventional mask that is divided into a part that can completely transmit light and a part that cannot completely transmit light. It can also be formed by letting a part of the photosensitive film flow to the part which does not remain by making it low.

The mask 300 used in the method of manufacturing the thin film transistor array panel according to the first exemplary embodiment of the present invention uses a mask in which a slit pattern is formed in the second region C1. At this time, the slit pattern has a linear shape, the width of the slit pattern is preferably in the range of 0.8-2.0㎛, in order to uniformly develop the photosensitive film thickness of the second portion 214 is formed in the second region (C1) Slit patterns are preferably arranged at different widths and intervals, which will be described in detail with reference to the drawings.

FIG. 8 is a view illustrating an alignment relationship between the slit pattern 310 and the drain electrode 175 as a wiring in the second region in which the slit pattern is formed to control light transmittance, and among the second regions C1. The slit pattern 311 disposed in the a region c11 in which the drain electrode 175 overlaps is precisely different from the slit pattern 310 disposed in the b region c12 in which the drain electrode 175 does not overlap. Has a narrower width. This is to develop the photosensitive film of the second portion 214 to a uniform thickness by making the amount of light passing through the a region c11 smaller than the amount of light passing through the b region c12. Because in the region a c11, there is a drain electrode 175 made of metal, and since the reflected light is generated by the drain electrode 175 during exposure, the amount of light irradiation is increased in the photosensitive film overlapping with the drain electrode 175. As a result, the photoresist pattern remains at an uneven thickness even in a portion corresponding to the second region C1. In order to prevent such a problem, in the embodiment of the present invention, the width d2 of the slit pattern 310 of the b region c12 is changed to the a region in order to make the dose of light irradiated to the photosensitive film uniform in the second region C1. It is formed to be wider in the range of about 1-1.5 times larger than the width d1 of the slit pattern 311 of (c12) to partially adjust the amount of light transmitted to uniform the amount of light irradiated to the photosensitive film in the second region (C1). The thickness of the second portion 214 is uniformly formed.

Here, although the light transmission amount is adjusted by adjusting only the widths of the slit patterns 310 and 311, the distance between the slit patterns 310 and 311 may be adjusted.

At this time, when the second portion 214 exposes a part of the storage capacitor conductor 177, the drain electrode 175, and the data line 171, the second insulating layer 214 may prevent the gate insulating layer 140 from being etched thereunder. use. Of course, since the end portion 125 of the gate line 121 is also used as a contact portion, the photoresist layer may be left in a middle thickness in the corresponding third region B1.

At this time, the slit patterns (310, 311) is preferably in the range of 0.8-2.0 ㎛ and have a straight shape, in the exposure step is disposed in parallel with one side of the drain electrode 175, at least two slit patterns 310 The mask 300 is aligned to be outside the boundary of the drain electrode. In addition, it is preferable to align the mask so that one of the slit patterns 310 overlaps the boundary line of the drain electrode 175.

Of course, the method of arranging the slit pattern in the same manner as the wiring may be applied to the development of the photosensitive film 214 having an intermediate thickness on the upper portion of the end portion 179 of the storage capacitor conductor 177 and the data line 171. Can be.

Subsequently, using the photoresist patterns 212 and 214 as an etching mask, etching is performed on the passivation layer 180 and the gate insulating layer 140 which are lower layers thereof. In this case, the gate insulating layer 140 and the passivation layer 180 should be removed in the third region B1, and at least the gate insulating layer 140 should remain in the second region C1. The photosensitive film 214 having an intermediate thickness is left in the region C1.

First, as shown in FIG. 9, the passivation layer 180 or the gate insulating layer 140 is etched using the photoresist patterns 212 and 214 as a mask. In this case, the passivation layer 180 is completely removed in the third region B1. Part of the photoresist layer may remain in the second region C1. In this case, the etching may be a dry etching method, and the etching may be performed under the same etching conditions with respect to the passivation layer 180 and the photoresist layers 212 and 214. This is to facilitate etching when the thickness of the gate insulating layer 140 remaining in the third region B1 is to be thinner than the passivation layer 180. In addition, leaving the thickness of the gate insulating layer 140 remaining in the third region B1 to be thinner than the passivation layer 180 may prevent the gate 125 from exposing the end portion 125 of the gate line in the third region B1 in a subsequent etching process. Even if the insulating layer 140 is completely removed, the protection layer 180 is removed in the second region C1 and the gate insulating layer 140 is not etched so that the under cut does not occur under the end portion 179 of the data line 171. This is to avoid. As shown in the drawing, a portion of the gate insulating layer 140 may be etched in the third region B1. In this case, when the photoresist film thickness of the second portion 214 is not uniform, the protective film 180 may be unevenly exposed and etched in the second region C1, so that the etching process cannot be stably performed, and the process can be performed with uniform reproducibility. Although it cannot be managed, the thickness of the second portion 214 is uniformly formed as in the present invention, so that when the protective film 180 is removed from the third region B1, the second portion in the second region C1 is removed. When removing the 214, the protective layer 180 may be prevented from appearing. Subsequently, the second portion 214 of the photoresist film remaining in the second region C1 is completely removed through the ashing process, so that the drain electrode 175, the storage capacitor conductor 177 and the data in the second region C1. The passivation layer 180 positioned on the end portion 179 of the line 171 is exposed. In this case, when the thickness of the second portion 214 is uneven in the process of developing the photoresist film, it is difficult to completely remove the second portion 214 in the ashing process, which burdens the subsequent etching process. In an embodiment, by uniformly developing the second portion 214, the etching process may be stably secured and the manufacturing process may be maintained with uniform reproducibility.

Subsequently, as shown in FIG. 10, the passivation layer 180 and the gate insulating layer 140 are removed from the second and third regions C1 and B1 exposed by using the first portion 212 of the remaining photoresist layer as an etching mask. The contact holes 185, 187, 189, and 182 exposing the drain electrode 175, the conductor 177 for the storage capacitor, and the end portions 179, 125 of the data line 171 and the gate line 121 are completed. . In this case, the etching may be performed by dry etching, and the etching may be performed under the same etching conditions with respect to the gate insulating layer 140 and the passivation layer 180. Subsequently, aluminum front etching is performed to remove the upper layers 202 and 702 of the aluminum alloy exposed through the contact holes 182, 185, 187 and 179. This is to minimize the contact resistance between the drain electrode 175, the conductor 177 for the storage capacitor or the gate line 121 and the end portions 125, 179 of the data line 171 and the ITO and IZO formed thereafter. to be.

Next, as shown in FIGS. 1 and 2, the ITO or IZO film is laminated and patterned using a mask to contact the pixel electrode 191 and the contact hole connected to the drain electrode 175 through the contact hole 185. The gate contact auxiliary member 192 and the data contact auxiliary member 199 connected to the end portion 125 of the gate line 121 and the end portion 179 of the data line 171 through 182 and 189, respectively. Form each. At this time, since the undercut does not occur at the lower portion of the pixel electrode 191, the gate contact auxiliary member 192, and the data contact auxiliary member 199, particularly, the pixel electrode 191 and the data contact auxiliary member 189 do not occur. The member 189 can be prevented from being disconnected, the profile of the contact portion can be formed smoothly, and the contact portion is sufficiently in contact with the lower layer 701 having a low contact resistance with the IZO or ITO film at the contact portion, thereby reducing the contact resistance of the contact portion. It can be minimized.

The structure of the thin film transistor array panel according to the exemplary embodiment of the present invention includes a conductive film made of aluminum or an aluminum alloy in which the gate line 121 and the data line 171 have low resistance, and at the same time, the contact portion, in particular, the data line and the pixel electrode 191. Contact resistance can be minimized and can be applied to a large screen high-definition liquid crystal display device. In addition, when the gate driving integrated circuit or the data driving integrated circuit is mounted to connect the gate line 121 and the data line 171, the profile of the contact portion may be gentle to ensure reliability of the contact portion.

As described above, the structure of the contact portion may be applied to a thin film transistor array panel manufactured using five masks, but the same may be applied to a thin film transistor array panel for liquid crystal display devices manufactured using four masks. . In a manufacturing method using a four-sheet mask, different layers are patterned into one photoresist pattern using a photoresist pattern including a portion having an intermediate thickness in order to reduce manufacturing costs. This will be described in detail with reference to the drawings.

First, a unit pixel structure of a thin film transistor array panel manufactured using four masks according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 13 to 15.

FIG. 11 is a layout view of a thin film transistor array panel for a liquid crystal display according to an exemplary embodiment of the present invention, and FIGS. 12 and 13 are along the XII-XII 'line and the XIII-XIII' line of the thin film transistor array panel shown in FIG. 11, respectively. It is sectional drawing cut out.

As shown in Figs. 11 to 13, the structure of the thin film transistor array panel for the liquid crystal display device according to the present embodiment is generally the same as the structure of the thin film transistor array panel for the liquid crystal display device shown in Figs.

However, unlike the thin film transistor array panel illustrated in FIGS. 1 and 2, the thin film transistor array panel according to the present exemplary embodiment includes a plurality of storage electrode lines 131 formed on the insulating substrate 110, and the gate line 121 is disposed on the gate line 121. There is no extension. The storage electrode line 131 is made of the same material as the gate line 121, is substantially parallel to the gate line 121, and is electrically separated from the gate line 121. The storage electrode line 131 receives a voltage such as a reference voltage and faces each other around the plurality of drain electrodes 175 and the gate insulating layer 140 connected to the plurality of pixel electrodes 191 to form a plurality of storage capacitors. . The storage electrode line 131 may be omitted when the storage capacitor generated due to the overlap between the pixel electrode 191 and the gate line 121 is sufficient.

In addition, a plurality of linear semiconductors 152 and a plurality of ohmic contacts 163 and 165 are provided.

The linear semiconductor 152 has substantially the same planar shape as the plurality of data lines 171 and the plurality of drain electrodes 175 except for the channel portion of the thin film transistor between the source electrode 173 and the drain electrode 175. That is, in the channel region C, the data line 171 and the drain electrode 175 are separated from each other, but the linear semiconductor 171 is connected to each other without disconnection to form a channel of the thin film transistor. The ohmic contacts 163 and 165 have substantially the same shape as the data line 171 and the drain electrode 175, respectively.

In addition, the contact hole 185 exposing the drain electrode 175 is larger than the drain electrode 175 to expose the boundary line of the drain electrode 175, and the pixel electrode 191 is the lower layer 701 of the drain electrode 175. And the gate insulating layer 140 adjacent thereto. In this case, the gate insulating layer 140 remains around the drain electrode 175 so that the pixel electrode 191 has a gentle profile at the contact portion.

Although the transparent IZO is mentioned as an example of the material of the pixel electrode 191, it may be formed of a transparent conductive polymer or the like. In the case of a reflective liquid crystal display, an opaque conductive material may be used.

Then, the manufacturing method according to the second embodiment of the present invention for manufacturing the thin film transistor array panel for the liquid crystal display device having the structure of FIGS. 11 to 13 using four masks is described in detail with reference to FIGS. 11 to 13 and 14a. This will be described with reference to FIG. 23C.

FIG. 14A is a layout view of a thin film transistor array panel in a first step of manufacturing according to a second embodiment of the present invention, and FIGS. 14B and 14C are cut along the lines XIVb-XIVb 'and XIVc-XIVc', respectively, in FIG. 14A. 15A and 15B are cross-sectional views taken along the lines XIVb-XIVb 'and XIVc-XIVc' in FIG. 14A, respectively, and are cross-sectional views in the next steps of FIGS. 14B and 14C, and FIG. 16A is FIGS. 15A and 15B. 16B and 16C are cross-sectional views taken along the XVIb-XVIb 'line and the XVIc-XVIc' line in FIG. 16A, respectively. FIGS. 17A, 18A, 19A, 17B, and 18B. 19b is a cross-sectional view taken along the XVIIb-XVIIb 'line and the XVIIc-XVIIc' line in FIG. 17A, respectively, illustrating the following steps in the order of processing, and FIG. 20A is the next to FIG. 19A and 19B. FIG. 20B and a layout view of a thin film transistor array panel at the step. 20C is a cross-sectional view taken along the lines XXb-XXb 'and XXc-XXc' in FIG. 20A, respectively, and FIGS. 21A, 22A, 23A, and 21B, 22B, and 23B are lines XXb-XXb 'and XXc in FIG. 20A, respectively. 20B and 20C show the following steps in the order of processing as a cross-sectional view taken along the line -XXc '.

First, as shown in FIGS. 14A to 14C, 2 at% of the lower conductive film 201 made of molybdenum or molybdenum alloy or chromium having low contact resistance with ITO or IZO, and aluminum or aluminum alloy having low specific resistance The upper conductive film 202 formed by sputtering a target of an Al-Nd alloy including Nd of sequentially formed was sequentially formed, and then patterned by photolithography and etching processes to form the plurality of gate lines 121 and the plurality of storage electrode lines 131. To form.

Next, as shown in FIGS. 15A and 15B, the gate insulating layer 140, the amorphous silicon layer 150, and the doped amorphous silicon layer 160 are each about 1,500 kPa to about 5,000 kPa, using chemical vapor deposition. Continuous deposition is at a thickness of 500 kPa to about 2,000 kPa, from about 300 kPa to about 600 kPa. Subsequently, the lower layer 701 and the upper layer 702 are sequentially deposited in a thickness of 1,500 mV to 3,000 mV by sputtering or the like, and then the photoresist layer 310 is formed on the thickness of 1 m to 2 m. Apply with

Thereafter, the photosensitive film 310 is irradiated with light through a photomask and then developed, and as shown in FIGS. 16B and 16C, the photosensitive film including the first portion 312 and the second portion 314 having different thicknesses. Patterns 312 and 314 are formed. In this case, the second portion 314 located in the channel region C2 of the thin film transistor is smaller than the first portion 312 positioned in the data region A2, and the photoresist 310 portion of the other region B2 is formed. Remove all or have a very small thickness.

In this case, it is preferable to form different intervals or widths of the slit patterns in order to develop the photosensitive film thickness of the second portion 314 uniformly.

Subsequently, etching is performed on the photoresist pattern 314 and the underlying layers, that is, the conductor layer 170, the doped amorphous silicon layer 160, and the amorphous silicon layer 150. In this case, the data line and the lower layers thereof remain in the data region A2, only the semiconductor layer remains in the channel portion C2, and the upper three layers 170, 160, and 150 remain in the remaining portion B2. ) Are removed to expose the gate insulating layer 140.

First, as shown in FIGS. 17A and 17B, the exposed conductor layer 170 of the other portion B2 is removed to expose the underlying doped amorphous silicon layer 160. In this process, either a dry etching method or a wet etching method may be used. In this case, the conductor layer 170 may be etched and the photoresist patterns 312 and 314 may be hardly etched. However, in the case of dry etching, since it is difficult to find a condition in which only the conductor layer 170 is etched and the photoresist patterns 312 and 314 are not etched, the photoresist patterns 312 and 314 may also be etched together. In this case, the thickness of the second portion 314 is thicker than that of the wet etching so that the second portion 314 is removed in this process so that the lower conductive layer 170 is not exposed.

The conductive film including Mo or MoW alloy, Al or Al alloy, or Ta among the conductive films of the conductor layer 170 may be either dry etching or wet etching. However, since Cr is not easily removed by the dry etching method, only wet etching may be used if the lower layer 701 is Cr. In the case of wet etching in which the lower layer 701 is Cr, CeNHO ₃ may be used as an etchant, and in the case of dry etching in which the lower layer 701 is Mo or MoW, a mixed gas of CF ₄ and HCl or CF A mixed gas of ₄ and O ₂ can be used, and in the latter case, the etching ratio to the photoresist film is almost the same.

In this way, as shown in FIGS. 17A and 17B, only the conductor layer of the channel portion C2 and the data region A2, that is, the conductor pattern 178 for the source / drain remains, and the conductor layer 170 of the other portion B2. ) Are removed to reveal the underlying doped amorphous silicon layer 160. The remaining conductor pattern 178 has the same shape as the data line 171 except that the source and drain electrodes 173 and 175 are connected without being separated. In addition, when dry etching is used, the photoresist patterns 312 and 314 are also etched to a certain thickness.

Then, as shown in FIGS. 18A and 18B, the exposed doped amorphous silicon layer 160 of the other portion B2 and the amorphous silicon layer 150 thereunder are dried together with the second portion 314 of the photoresist film. Simultaneously remove by etching. In this case, the photoresist pattern 312 and 314, the doped amorphous silicon layer 160, and the amorphous silicon layer 150 (the amorphous silicon layer and the doped amorphous silicon layer have almost no etching selectivity) are simultaneously etched and gated. The insulating layer 140 should be performed under a condition that is not etched. In particular, the insulating layer 140 may be etched under conditions in which the etching ratios of the photoresist patterns 312 and 314 and the amorphous silicon layer 150 are substantially the same. For example, by using a mixed gas of SF ₆ and HCl or a mixed gas of SF ₆ and O ₂ , the two films can be etched to almost the same thickness. When the etch ratios of the photoresist patterns 312 and 314 and the amorphous silicon layer 150 are the same, the thickness of the second portion 314 is equal to the sum of the thicknesses of the amorphous silicon layer 150 and the doped amorphous silicon layer 160. Or less than that.

This removes the second portion 314 of the channel portion C2 to reveal the source / drain conductor pattern 178, as shown in FIGS. 18A and 18B, and the doped amorphous silicon of the other portion B2. The layer 160 and the amorphous silicon layer 150 are removed to expose the gate insulating layer 140 underneath. Meanwhile, since the first portion 312 of the data area A2 is also etched, the thickness becomes thinner. In this step, the linear semiconductor 152 is completed. Reference numeral 168 denotes the doped amorphous silicon layer pattern under the source / drain conductor pattern 178, respectively.

Subsequently, ashing of the photoresist film remaining on the surface of the source / drain conductor pattern 178 of the channel part C2 is removed.

Next, as illustrated in FIGS. 19A and 19B, the source / drain conductor pattern 178 of the channel portion C2 and the source / drain doped amorphous silicon layer pattern 168 below are etched and removed. In this case, the etching may be performed only by dry etching with respect to both the source / drain conductor pattern 178 and the doped amorphous silicon layer pattern 168, and the source / drain conductor pattern 178 may be wet-etched. , The doped amorphous silicon layer pattern 168 may be performed by dry etching. In the former case, it is preferable to perform the etching under the condition that the etching selectivity of the source / drain conductor pattern 178 and the doped amorphous silicon layer pattern 168 is large, which is difficult to find the etching end point when the etching selectivity is not large. This is because it is not easy to adjust the thickness of the semiconductor pattern 152 remaining in the channel portion C2. For example, the source / drain conductor pattern 178 may be etched using a mixed gas of SF ₆ and O ₂ . In the latter case of alternating wet and dry etching, the sides of the wet-etched source / drain conductor pattern 178 are etched, but the dry-doped doped amorphous silicon layer pattern 168 is hardly etched so that it is stepped. Is made. Examples of the etching gas used to etch the doped amorphous silicon layer pattern 168 and the semiconductor pattern 152 include the aforementioned mixed gas of CF ₄ and HCl or mixed gas of CF ₄ and O ₂ . Using CF ₄ and O ₂ may leave the semiconductor pattern 152 with a uniform thickness. In this case, as shown in FIG. 19B, a portion of the semiconductor 152 may be removed to reduce the thickness, and the second portion 314 of the photoresist pattern may also be etched to a certain thickness at this time. At this time, the etching must be performed under the condition that the gate insulating layer 140 is not etched, and the photoresist pattern is formed so that the first portion 312 is etched so that the data line 171 and the drain electrode 175 are not exposed. Of course, thick is preferable.

In this case, as shown in FIGS. 16A, 19A, and 19B, the data line 171 and the drain electrode 175 are separated, and the ohmic contacts 163 and 165 below the data line 171 and the drain electrode 175. ) Is divided and completed.

Finally, the photoresist first portion 312 remaining in the data area A2 is removed. However, removal of the first portion 312 may be made after removing the conductive portion 178 for the channel portion C2 source / drain and before removing the doped amorphous silicon layer pattern 168 thereunder.

As mentioned earlier, wet and dry etching can be alternately used or only dry etching can be used. In the latter case, since only one type of etching is used, the process is relatively easy, but it is difficult to find a suitable etching condition. On the other hand, in the former case, the etching conditions are relatively easy to find, but the process is more cumbersome than the latter.

After forming the data line 171 and the drain electrode 175 in this manner, the remaining photoresist pattern 312 is removed, and silicon nitride is deposited by a CVD method, or an organic insulating layer having a low dielectric constant is laminated to form the protective film 180. To form. Subsequently, after the photoresist film 410 is applied to the upper part by spin coating, the photoresist film 410 is irradiated with light through a mask and then developed to form the photoresist patterns 412 and 414 as shown in FIGS. 20B and 20C. do. In this case, among the photoresist patterns 412 and 414, the second region C3, that is, the second portion 414 positioned above the end portion 179 of the drain electrode 175 and the data line 171, is the gate line 121. The photoresist of the third region B3 has a thickness thinner than that of the first portion 412 located in the first region A3 except for the third region B3 corresponding to the end portion 125 of FIG. Here, the photoresist 414 remaining in the second region C3 may be the same or thinner than the passivation layer 180.

In this case, the width or the interval of the slit pattern is adjusted differently so as to develop the second portion 414 in a uniform thickness.

At this time, when the photoresist patterns 412 and 414 are used as etching masks, the protective layer 180 and the gate insulating layer 140, which are lower layers thereof, are etched. In the third region B3, the gate insulating layer 140 and the protective layer ( 180 should be removed, and at least the gate insulating layer 140 should remain in the second region C3.

First, as shown in FIGS. 21A and 21B, the passivation layer 180 or the gate insulation layer 140 is etched using the photoresist patterns 412 and 414 as a mask. In this case, the passivation layer 180 is formed in the third region B3. It must be completely removed, and a part of the photosensitive film may remain in the second region C3. In this case, the thickness of the gate insulating layer 140 remaining in the third region B3 is preferably thinner than the passivation layer 180. As described above, the end portion 179 of the drain electrode 175 and the data line 171 may be formed. This is to prevent undercut from occurring at the bottom. As shown in the drawing, a portion of the gate insulating layer 140 may be etched in the third region B3. Subsequently, the second portion 414 of the photoresist film remaining in the second region C3 is completely removed through the ashing process, thereby discharging the end portion 179 of the drain electrode 175 and the data line 171 in the second region C3. Expose the passivation layer 180 located above.

Subsequently, as shown in FIGS. 22A and 22B, the drain layer 175 and the data line are removed by removing the passivation layer 180 from the second region C3 exposed by using the remaining portion of the first photoresist layer 412 as an etching mask. Complete contact holes 185 and 189 exposing end portion 179 of 171. In this case, the etching may be performed by dry etching, and the etching may be performed under the same etching conditions with respect to the gate insulating layer 140 and the passivation layer 180. In this case, since the gate insulating layer 140 on the end portion 125 of the gate line in the third region B3 has a thickness smaller than that of the passivation layer 180 of the second region C3, the third region B3 In this case, even when the gate insulating layer 140 is completely removed to expose the end portion 125 of the gate line through the contact hole 182, the gate insulating layer 140 may be left in the second region C3.

Then, after removing the photoresist film, as shown in FIGS. 23A and 23B, the upper films 202 and 702 of the aluminum alloy exposed through the contact holes 182, 185 and 189 are removed. This exposes the lower layers 201 and 701 of the end portions 125 and 179 of the drain electrode 175 or the gate line 121 and the data line 171, respectively.

Finally, as illustrated in FIGS. 11 to 13, a pixel electrode 191 connected to the drain electrode 175 by depositing an IZO layer having a thickness of 1500 mm to 500 mm by a sputtering method and patterning by a photolithography process using a mask. ), A gate contact auxiliary member 192 connected to the end portion 125 of the gate line 121, and a data contact auxiliary member 199 connected to the end portion 179 of the data line 171 are formed. The etching solution for patterning IZO uses a chromium etchant that is used to etch a metal layer of chromium (Cr), which does not corrode aluminum and thus prevents corrosion of data lines or gate lines, and the etching solution (HNO ₃ / (NH ₄ ) ₂ Ce (NO ₃ ) ₆ / H ₂ O), and the like.

In the second embodiment of the present invention, the data line 171, the ohmic contacts 163 and 165 and the semiconductor 152 below are formed using a single mask as well as the effects according to the first embodiment. In the process, the data line 171 and the drain electrode 175 may be separated to simplify the manufacturing process.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, in the method of manufacturing the thin film transistor array panel according to the exemplary embodiment of the present invention, a mask in which a slit pattern is formed is used to form a photoresist pattern including a portion having an intermediate thickness. The portion having the intermediate thickness can be formed to have a uniform thickness by forming the photosensitive film and exposing and developing the photosensitive film. This makes it possible to implement and manage the manufacturing process with easy and uniform reproducibility.

1 is a thin film transistor array panel for a liquid crystal display according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view of the thin film transistor array panel illustrated in FIG. 1 taken along the line II-II ′.

3A, 4A, 5A, and 7A are layout views of a thin film transistor array panel in which an intermediate process of manufacturing a thin film transistor array panel for a liquid crystal display device according to a first embodiment of the present invention is shown according to a process sequence thereof;

3B is a cross-sectional view taken along the line IIIb-IIIb ′ in FIG. 3A;

4B is a cross-sectional view taken along the line IVb-IVb ′ in FIG. 4A and is a cross-sectional view showing the next step in FIG. 3B;

FIG. 5B is a cross-sectional view taken along the line Vb-Vb ′ in FIG. 5A and is a cross-sectional view showing the next step in FIG. 4B;

FIG. 6 is a cross-sectional view taken along the line Vb-Vb 'of FIG. 5A and illustrating the next step of FIG. 5B;

FIG. 7B is a cross-sectional view taken along the line VIIb-VIIb ′ of FIG. 7A and illustrating the next step of FIG. 6;

8 is a cross-sectional view illustrating an alignment relationship between a slit pattern of a mask and a drain electrode in a method of manufacturing a thin film transistor array panel according to a first exemplary embodiment of the present invention.

FIG. 9 is a cross-sectional view taken along the line VIIb-VIIb ′ of FIG. 7A and illustrating the next step of FIG. 8;

FIG. 10 is a cross-sectional view taken along the line VIIb-VIIb ′ of FIG. 7A and illustrating the next step of FIG. 9;

11 is a layout view of a thin film transistor array panel for a liquid crystal display according to a second exemplary embodiment of the present invention.

12 and 13 are cross-sectional views of the thin film transistor array panel illustrated in FIG. 13 taken along lines XII-XII 'and XIII-XIII',

14A is a layout view of a thin film transistor array panel in a first step of manufacturing according to the second embodiment of the present invention;

14B and 14C are cross-sectional views taken along the lines XIVb-XIVb ′ and XIVc-XIVc ′ in FIG. 14A, respectively.

15A and 15B are cross-sectional views taken along the lines XIVb-XIVb 'and XIVc-XIVc' in FIG. 14A, respectively, and are cross-sectional views taken in the next steps of FIGS. 14B and 14C,

16A is a layout view of a thin film transistor array panel in the next steps of FIGS. 15A and 15B.

16B and 16C are cross-sectional views taken along lines XVIb-XVIb 'and XVIc-XVIc', respectively, of FIG. 16A.

17A, 18A, 19A and 17B, 18B, and 19B are cross-sectional views taken along the lines XVIb-XVIb 'and XVIc-XVIc' in FIG. 16A, respectively, illustrating the following steps in the order of the process. ,

20A is a layout view of a thin film transistor array panel in the next step of FIGS. 19A and 19B.

20B and 20C are cross-sectional views taken along the lines XXb-XXb 'and XXc-XXc' of FIG. 20A, respectively.

21A, 22A, 23A and 21B, 22B, and 23B are cross-sectional views taken along the lines XXb-XXb 'and XXc-XXc' in FIG. 20A, respectively, and show cross-sectional views of the following steps in the order of the process. to be.

Claims (7)

In a mask in which a plurality of slit patterns are formed in any area in order to adjust the transmittance of light, The mask includes a first portion in which slits are arranged at regular intervals, a second portion in which slits are arranged wider than the first portion, When exposing the film formed on the first region and the second region having different reflectivity with the mask, And if the reflectivity of the first region is greater than that of the second region, the first portion corresponds to the first region and the second portion corresponds to the second region. Forming a gate line including a gate electrode on the insulating substrate, Forming a gate insulating film on the gate line; Forming a semiconductor on the gate insulating film, Forming a data line intersecting the gate line and including a source electrode and a drain electrode positioned opposite the source electrode to the gate electrode; Forming a passivation layer covering the data line and the drain electrode; Patterning the passivation layer to form a first contact hole exposing the drain electrode and the gate insulating layer adjacent to a boundary between the drain electrode and Forming a pixel electrode on the passivation layer to contact the drain electrode and the upper surface of the gate insulating layer through the contact hole; The contact hole may be formed by a photolithography process using a mask, and the mask may include a first region corresponding to the data line and the semiconductor, and a plurality of slit patterns formed therein and a second region corresponding to the contact hole. And a third region corresponding to an end portion of the gate line, wherein the slit pattern includes a first portion corresponding to the drain electrode and a second portion corresponding to the gate insulating layer, and a gap between the slits of the first portion A method of manufacturing a thin film transistor array panel narrower than an interval of slits of the second portion. In claim 2, The first region may not transmit light, the third region may transmit light completely, and the second region may transmit less light than the third region. In claim 3, The photoresist pattern exposed and developed using the mask in the photolithography process is positive, and the photoresist pattern corresponds to the data line, the first portion corresponding to the semiconductor, and the contact hole and has a thickness smaller than the first portion. And a third portion corresponding to an end portion of the gate line and having a thickness smaller than that of the second portion. In claim 4, The photoresist pattern may further include a fourth portion corresponding to an end portion of the data line and having a thickness smaller than that of the first portion. In claim 2, The gate line or the data line is formed of a lower conductive layer of chromium, molybdenum or molybdenum alloy and an upper conductive layer of aluminum or aluminum alloy. In claim 6, And removing the upper conductive layer before the pixel electrode forming step.