KR20060053497A - Method for manufacturing thin film transistor substrate - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor substrate for a display device, the method comprising: forming a gate wiring including a gate line and a gate electrode connected thereto on an insulating substrate. Steps; Forming a gate insulating film covering the gate wiring; Forming a semiconductor layer pattern on the gate insulating film; Forming an ohmic contact layer pattern on the semiconductor layer pattern; Forming a data line including a source electrode and a drain electrode formed on the ohmic contact layer and made of the same layer, and a data line connected to the source electrode, wherein the separation of the source electrode and the drain electrode is performed. A first wet etching process using a photosensitive film pattern and a second wet etching process using a second photosensitive film pattern coated with an additional photoresist film to cover the data wiring exposed by the first wet etching process. It is done. Accordingly, in the process of forming the channel region of the thin film transistor through the photolithography process using the photoresist pattern, an additional photoresist is coated to minimize the reduction of the line width of the data line due to the wet etching, thereby suppressing the occurrence of defects. A method of manufacturing a thin film transistor substrate for a display device can be provided.

Description

Method for manufacturing thin film transistor substrate {METHOD FOR MANUFACTURING THIN FILM TRANSISTOR SUBSTRATE}

1 is a schematic layout view of a thin film transistor substrate manufactured according to an embodiment of the present invention;

FIG. 2 is a cross-sectional view of a thin film transistor substrate taken along line II-II of FIG. 1;

3 to 11 are cross-sectional views sequentially illustrating each step of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

10: insulated substrate 22: gate line

24: gate pad 26: gate electrode

30 gate insulating film 40 semiconductor layer

50 resistive contact layer 62 data line

65 source electrode 66 drain electrode

68: data pad 70: protective film

82: pixel electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a thin film transistor substrate for a display device, and more particularly, to suppress that the line width of a data line is narrower than that of a semiconductor layer and an ohmic contact layer in a photolithography process using a photoresist pattern. Accordingly, the present invention relates to a method of manufacturing a thin film transistor substrate for a display device, in which defects are minimized.

In general, a thin film transistor substrate (TFT) is used as a circuit board for independently driving each pixel in a liquid crystal display (LCD), an organic electroluminescence (EL) display, and the like. The thin film transistor substrate is provided with scan signal wirings or gate wirings for transmitting scan signals and image signal lines or data wirings for transferring image signals. The thin film transistor may include a thin film transistor connected to a gate wiring and a data wiring, a pixel electrode connected to the thin film transistor, a gate insulating film covering and insulating the gate wiring, and a protective film covering and insulating the thin film transistor and the data wiring.

The thin film transistor includes a semiconductor layer forming a gate electrode and a channel, which are part of a gate wiring, a source electrode and a drain electrode, which are part of a data wiring, a gate insulating film, a protective film, and the like. The thin film transistor is a switching device that transfers or blocks an image signal transmitted through a data line to a pixel electrode according to a scan signal transmitted through a gate line.

Here, the channel region, the source electrode and the drain electrode of the thin film transistor are formed through the photoresist pattern formed through the photo process and the etching process using the same. However, in this manufacturing process, the data lines are exposed twice to wet etching. Therefore, since the line width of the data line has a narrower width than that of the underlying ohmic contact layer and the semiconductor layer, the ohmic contact layer and the semiconductor layer protrude to both sides in the longitudinal direction of the data line and remain.

Accordingly, there is a problem in that the characteristics of the thin film transistor may be degraded or defects such as crosstalk or vertical staining may occur. In addition, in order to secure a process margin due to such a defect and to prevent light leakage, the black matrix region of the color filter substrate facing the thin film transistor substrate must be widened, thus adversely affecting the aperture ratio.

In particular, this problem is more prominent in the process of manufacturing a thin film transistor substrate using a four-sheet mask. This is because the wet etching process may be performed twice in order to form the channel region, the source electrode, and the drain electrode by using the photoresist pattern formed through the slit exposure when using the four masks.

Accordingly, an object of the present invention is to minimize the reduction in the line width of the data line due to wet etching by coating an additional photoresist in the process of forming the channel region of the thin film transistor through a photolithography process using the photoresist pattern. The present invention provides a method of manufacturing a thin film transistor substrate for a display device, which suppresses the occurrence of the problem.

According to the present invention, there is provided a method of manufacturing a thin film transistor substrate for a display device, comprising the steps of: forming a gate wiring including a gate line and a gate electrode connected thereto on an insulating substrate; Forming a gate insulating film covering the gate wiring; Forming a semiconductor layer pattern on the gate insulating film; Forming an ohmic contact layer pattern on the semiconductor layer pattern; Forming a data line including a source electrode and a drain electrode formed on the ohmic contact layer and made of the same layer, and a data line connected to the source electrode, wherein the separation of the source electrode and the drain electrode is performed. A first wet etching process using a photosensitive film pattern and a second wet etching process using a second photosensitive film pattern coated with an additional photoresist film to cover the data wiring exposed by the first wet etching process. The manufacturing method of the thin film transistor substrate for display apparatuses is achieved.

Here, the first photoresist pattern includes a first portion positioned between the source electrode and the drain electrode, a second portion having a thickness thicker than the first portion, and a third portion having a thickness thinner than the first portion. It is desirable to.

Here, the thickness of the third portion is preferably close to zero.

In addition, the data wiring of the third portion may be removed in the first wet etching process, and the data wiring of the first portion may be removed in the second wet etching process to separate and complete the source electrode and the drain electrode. Do.

In addition, the additional photosensitive film is preferably formed by a slit coating method of applying a photosensitive material using a slit nozzle.

According to the method of manufacturing a thin film transistor substrate for a display device, in the process of forming a channel region of the thin film transistor through a photolithography process using a photoresist pattern, an additional photoresist is coated on the data line exposed in the first wet etching process. By covering it, it is possible to suppress further reduction in the line width of the data wiring in the second wet etching process.

Hereinafter, a liquid crystal display panel according to an exemplary embodiment of the present invention will be described with reference to the accompanying drawings. In the accompanying drawings, a thin film transistor substrate for a display device using an amorphous silicon (a-Si) thin film transistor (TFT) formed by a four-sheet mask process is schematically illustrated.

First, a structure of a thin film transistor substrate formed by a method of manufacturing a thin film transistor substrate for a display device according to an exemplary embodiment of the present invention will be described with reference to FIG. 1.

A plurality of gate lines 22 and a plurality of storage electrode lines 28 are formed on the insulating substrate 10 in parallel with the gate lines 22.

A portion of the gate line 22 branches to form the gate electrode 26, and a gate pad 24 is formed at one end of the gate line 22. The gate line 22 includes all of the gate line 22, the gate electrode 26, the gate pad 24, and the like.

A plurality of data lines 62 are formed on the gate line 22 and the storage electrode line 28 to be insulated from each other. A data line 62, a source electrode 65 branched from the data line 62, a drain electrode 66 facing the source electrode 65, a data pad 68 formed at one end of the data line 62, and the like. It is called data wiring including all. In the case where the sustain electrode line 28 is formed, the conductor 64 for the storage capacitor is formed on the same layer as the data line.

In the region defined by the intersection of the gate line 22 and the data line 62, a plurality of pixel electrodes 82 are formed and electrically connected to the gate line 22, the data line 62, and the pixel electrode 82. A plurality of connected thin film transistors are formed.

FIG. 2 is a cross-sectional view taken along line II-II of the thin film transistor substrate illustrated in FIG. 1. Hereinafter, a thin film transistor substrate will be described in detail with reference to FIGS. 1 and 2.

First, gate wirings 22, 24, and 26 are formed on an insulating substrate 10 made of an insulating material such as glass, quartz, ceramic, or plastic. Such gate wiring can be formed in multiple layers to compensate for the shortcomings of each metal or alloy and to obtain the desired physical properties. In one example, a double layer using aluminum or an aluminum alloy as a lower layer and chromium, molybdenum, molybdenum-tungsten or molybdenum-tungsten nitride as the upper layer is formed. The lower layer uses aluminum or aluminum alloy with low specific resistance to prevent signal resistance due to wiring resistance, and the upper layer uses chemicals to compensate for the shortcomings of aluminum or aluminum alloy where corrosion resistance by chemicals is weak and easily oxidized to cause disconnection. It is to use chromium, molybdenum, molybdenum-tungsten or molybdenum-tungsten nitride which are highly corrosion-resistant to chemicals. In recent years, molybdenum (Mo), aluminum (Al), titanium (Ti), tungsten (W) and the like have been spotlighted as wiring materials.

In addition, the storage electrode line 28 is formed on the insulating substrate 10 in parallel with the gate line 22. The storage electrode line 28 may also be formed in a multilayer like the gate lines 22, 24, and 26. The storage electrode line 28 overlaps the conductor 64 for the storage capacitor connected to the pixel electrode 82 to be described later to form a storage capacitor which improves the charge retention capability of the pixel. The pixel electrode 82 and the gate line to be described later will be described. If the holding capacity generated by the overlap of (22) is sufficient, it may not be formed. It is common to apply the same voltage to the sustain electrode line 28 as the common electrode (not shown) of the upper substrate (not shown) to be opposed to the thin film transistor substrate.

A gate insulating film 30 made of silicon nitride (SiNx) is formed on the gate wirings 22, 24, 26, and the storage electrode line 28 to form the gate wirings 22, 24, 26, and the storage electrode line 28. Cover.

A semiconductor layer 40 made of a semiconductor such as hydrogenated amorphous silicon is formed on the gate insulating layer 30, and an n-type impurity such as phosphorus (P) is heavily doped on the semiconductor layer 40. An ohmic contact layer 50 made of silicon is formed.

The data lines 62, 64, 65, 66, and 68 are formed on the ohmic contact layer 50. Such data wirings, like the gate wirings 22, 24 and 26, may be formed in multiple layers to compensate for the disadvantages of each metal or alloy and to obtain desired physical properties. For example, the data line may be formed of a triple layer of molybdenum (Mo), aluminum (Al), and molybdenum (Mo).

The data line is formed in a vertical direction and has a data line 62 having an end portion 68 of a data line to which an image signal from the outside is applied, a source electrode 65 of a thin film transistor which is a branch of the data line 62, and And a data line portion 62, 68, 65 connected to an end of the data line 62 and made of a data pad 68 for receiving an image signal from the outside and transmitting the image signal to the data line 62. A drain electrode 66 of the thin film transistor, which is separated from the line portions 62, 68, and 65, and is located opposite to the source electrode 65 with respect to the gate electrode 26 or the channel portion E of the thin film transistor. Also included is a conductor 64 for a storage capacitor located above the electrode line 28. When the sustain electrode line 28 is not formed, the conductor 64 for the storage capacitor is also not formed.

The ohmic contact layer 50 lowers the contact resistance between the semiconductor layer 40 at the bottom thereof and the data lines 62, 64, 65, 66, 68 thereon, and the data lines 62, 64, 65. , 66, 68). That is, the ohmic contact layer 55 of the data line portion is the same as the data line portions 62, 68, and 65, and the ohmic contact layer 56 for the drain electrode is the same as the drain electrode 66.

The semiconductor layer 40 has the same shape as the data lines 62, 64, 65, 66, and 68 and the ohmic contacts 55 and 56 except for the channel portion E of the thin film transistor. Specifically, the thin film transistor semiconductor layer 40 is slightly different from the rest of the data lines 62, 64, 65, 66, 68 and the ohmic contacts 55, 56. That is, the data line parts 62, 68, 65, in particular, the source electrode 65 and the drain electrode 66 are separated from the channel part E of the thin film transistor, and the ohmic contact layer 55 and the drain electrode of the data line part are separated. The resistive contact layer 56 is also separated, but the thin film transistor semiconductor layer 40 is connected here without being disconnected to create a channel of the thin film transistor.

On the data lines 62, 64, 65, 66 and 68, an a-Si: C: O film or a-Si: O: F film (low dielectric constant CVD) deposited by silicon nitride or plasma enhanced chemical vapor deposition (PECVD) method Film) or an organic insulating film is formed. The protective film 70 has contact holes 76, 78, 72 exposing the drain electrode 66, a part of the data pad 68 and the conductor 64 for the storage capacitor, and also together with the gate insulating film 30. It has a contact hole 74 that exposes a portion of the gate pad 24.

On the passivation layer 70, a pixel electrode 82 that receives an image signal from the thin film transistor and generates an electric field together with the common electrode of the upper plate is formed. The pixel electrode 82 is made of a transparent conductive material such as ITO or indium tin oxide (IZO), and is physically and electrically connected to the drain electrode 66 through the contact hole 76 to receive an image signal. The pixel electrode 82 also overlaps the neighboring gate line 22 and the data line 62 to increase the aperture ratio, but may not overlap. In addition, the pixel electrode 82 is also connected to the storage capacitor conductor 64 through the contact hole 72 to transmit an image signal to the storage capacitor conductor 64. On the other hand, contact auxiliary members 86 and 88 are formed on the gate pad 24 and the data pad 68 through the contact holes 74 and 78, respectively. These contact auxiliary members 86 and 88 complement the adhesion between the end portions 24 and 68 and the external circuit device and protect the gate pad 24 and the data pad 68, but are not essential. Their application is optional.

According to an embodiment of the present invention, a method of manufacturing a thin film transistor substrate for a display device having the structure of FIG. 2 will be described in detail as follows.

First, as shown in FIG. 3, a gate metal layer is deposited on the insulating substrate 10, and then includes a gate line 22, a gate pad 24, a gate electrode 26, and the like through a photolithography process. After the gate wirings and the storage electrode lines 28 are formed, the gate insulating film 30, the semiconductor layer 40, and the ohmic contact layer 50 made of silicon nitride are respectively 1,500 kV to 5,000 kV, using chemical vapor deposition. The stack is successively laminated to a thickness of 500 kPa to 2,000 kPa, 300 kPa to 600 kPa, and then the data metal layer 600 is deposited by sputtering or the like to form a data line. Then, a photosensitive film 900 is coated on the data metal layer 600. The overall thickness of this photosensitive film 900 has an overall thickness of approximately 1 µm to 2 µm.

Thereafter, the photosensitive film 900 is irradiated with light through a mask and then developed. As shown in FIG. 4, the first photosensitive film pattern 912 for forming the data wires 62, 64, 65, 66, and 68 is formed. 914 is formed. In this case, among the first photoresist patterns 912 and 914, the channel portion E of the thin film transistor, that is, the first portion 914 located between the source electrode 65 and the drain electrode 66, may be the data wiring portion C, That is, the thickness is smaller than the second portion 912 located at the portion where the data lines 62, 64, 65, 66, and 68 are to be formed, and the photosensitive film of the other portion D is removed so that the third portion is almost zero. It is in a close state.

At this time, the ratio of the thickness of the photoresist film 914 remaining in the channel portion E and the thickness of the photoresist film 912 remaining in the data wiring portion C should be different depending on the process conditions in the etching process described later. The thickness of the first portion 914 is preferably equal to or less than 1/2 of the thickness of the second portion 912. In the present invention, it is most preferable to form the thickness of the first portion 914 as thin as possible.

As such, there may be various methods of exposing the channel portion E, that is, the first portion 914 to be thinner than the second portion 912 by using a mask, and the light transmission amount of the channel portion E. In order to control this, a slit or lattice pattern is formed or a translucent film is used.

In this case, it is preferable that the line width of the pattern located between the slits or the interval between the patterns, that is, the width of the slits, is smaller than the resolution of the exposure machine used for exposure. The thin film may have a thin film or a thin film having a different thickness.

When the light is irradiated to the photoresist film 900 through such a mask, the polymers are completely decomposed in the part directly exposed to the light, and the polymers are not completely decomposed because the amount of light is small in the part where the slit pattern or the translucent film is formed. In the part covered by the light shielding film, the polymer is hardly decomposed. Subsequently, when the photoresist film 900 is developed, only a portion where the polymer molecules are not decomposed remains, and a photoresist film 914 having a thickness thinner than a portion that is not irradiated with light may be left in the central portion irradiated with little light. In this case, if the exposure time is too long, all polymer molecules are decomposed, so it should not be so.

Subsequently, the first photoresist patterns 912 and 914 and the underlying layers, that is, the data metal layer 600, the ohmic contact layer 50, and the semiconductor layer 40 are etched. In this case, the data lines 62, 64, 65, 66, and 68 and the films under the data lines remain intact, and only the semiconductor layer 40 remains in the channel portion E. In the portion D, all three layers 600, 50, and 40 are removed to expose the gate insulating layer 30.

First, as shown in FIG. 5, the exposed data metal layer 600 of the other portion D is removed to expose the underlying ohmic contact layer 50. In this process, both a dry etching method and a wet etching method may be used. In this case, the data metal layer 600 may be etched, and the first photoresist pattern 912 and 914 may be etched. However, in the case of dry etching, it is difficult to find a condition in which only the data metal layer 600 is etched and the first photoresist pattern 912 and 914 are not etched. In the present invention, the data metal layer 600 is removed by wet etching. This step is called a first wet etching process. However, when the data metal layer 600 is removed by wet etching, the data metal layer 600 under the first photoresist patterns 912 and 914 is undercut.

In this way, as shown in Fig. 5, only the data metal layer of the channel portion E and the data wiring portion D, i.e., the data wiring layer 67 for the source / drain and the conductor 64 for the storage capacitor, is left. ), All of the data metal layer 600 is removed to reveal the resistive contact layer 50 underneath. The remaining data wiring layers 67 and 64 have the same shape as the data wirings 62, 64, 65, 66 and 68 except that the source and drain electrodes 65 and 66 are connected without being separated.

Next, as shown in FIG. 6, the exposed ohmic contact layer 50 of the other portion D and the semiconductor layer 40 below it are simultaneously removed by a dry etching method. In this case, the first photoresist pattern 912 and 914, the ohmic contact layer 50, and the semiconductor layer 40 (the semiconductor layer and the ohmic contact layer have almost no etching selectivity) are simultaneously etched and the gate insulating layer 30 is etched. Is carried out under conditions that are not etched. Therefore, the first photoresist pattern is also thinned as a whole, and in some cases, the photoresist of the first portion 914 may be removed.

Next, as shown in FIG. 7, an additional photoresist film is coated to cover the data line 67 exposed due to the first wet etching process described above. When the photosensitive material is applied to the entire surface of the substrate by the slit coater method of applying the photosensitive material by using the slit-shaped nozzle, the photosensitive material applied to the relatively high portion where the first photosensitive film patterns 912 and 914 are formed is the third part. That is, it flows down to the other part (D). The photosensitive material is applied by adjusting the speed of the slit coating so that the additional photoresist film thus formed has a height to cover the data line 67 exposed by the first wet etching process. On the other hand, some of the photoresist remains in the first portion 914 may form an additional photoresist here. In this way, an additional photoresist film is added to the first photoresist patterns 912 and 914 to form second photoresist patterns 922, 924 and 926.                     

Next, as shown in FIG. 8, the photoresist film and the additional photoresist film of the channel portion E are removed through a photoresist etch back process. At this time, the photoresist C, that is, the photoresist film of the second part 922 and the additional photoresist film of the other part D, that is, the third part 926, are also etched and thinned. In this way, the photoresist film on the channel portion E is removed to expose the source / drain wiring layer 67, and the semiconductor layer 40 is completed in this step.

Subsequently, ashing of the photoresist film remaining on the surface of the source / drain wiring layer 67 of the channel portion E is removed through ashing.

Next, as shown in FIG. 9, the source / drain wiring layer 67 of the channel portion E is removed to complete the source electrode 65 and the drain electrode 66. At this time, all of the data wires 62, 64, 65, 66, and 68 are completed. The source / drain wiring layer 67 may be removed by a wet etching method or a dry etching method. However, in the present invention, the source / drain wiring layer 67 may be removed through wet etching, and the second wet etching process may be performed. This is called. As in the case of the first wet etching process, undercutting occurs in the process of removing the source / drain wiring layer 67, but the etching solution in the other portion (D), that is, the third portion, is caused by an additional photosensitive film. Exposed to the data wires 62, 64, 65, 66, 68 are prevented from being etched and undercut.

Therefore, the line widths of the data lines 62, 64, 65, 66, and 68 may be reduced in the process of forming the channel portion E of the thin film transistor.

Next, as shown in FIG. 9, the ohmic contact layer 50 for the source / drain is etched away. At this time, etching is performed by dry etching with respect to the ohmic contact layer 50 unlike the source / drain wiring layer 67. When the wet etching and the dry etching are alternately performed, the side surfaces of the source / drain wiring layer 67 to be wet etched are etched, but the ohmic contact layer 50 to be dry etched is hardly etched, thus making a step shape. Examples of the etching gas used for etching the ohmic contact layer 50 and the semiconductor layer 40 can with a mixed gas of the mixed gas of CF ₄ and HCl and CF ₄ and O _2, the CF ₄ and O ₂ When used, the semiconductor layer 40 can be left in a uniform thickness. In this case, a portion of the semiconductor layer 40 may be removed to reduce the thickness, and the second portion 912 and the third portion of the second photoresist pattern may also be etched to a certain thickness at this time. At this time, the etching must be performed under the condition that the gate insulating film 30 is not etched, and the second portion 912 is etched so that the data lines 62, 64, 65, 66, and 68 underneath are not exposed. Of course, it is preferable that the thickness is thick.

In this way, the source electrode 65 and the drain electrode 66 are separated, thereby completing the data wires 62, 64, 65, 66, and 68 and the ohmic contacts 55 and 56 thereunder.

Then, the second photosensitive film pattern remaining in the data wiring portion C is removed.

Next, as shown in FIG. 10, a silicon nitride, an a-Si: C: O film, or an a-Si: O: F film is grown by chemical vapor deposition (CVD) or an organic insulating film is applied to the protective film 70. To form.

Subsequently, the protective film 70 is etched together with the gate insulating film 30 to expose the drain electrode 66, the end portion 24 of the gate line, the end portion 68 of the data line, and the conductor 64 for the storage capacitor, respectively. Contact holes 76, 74, 78, 72 are formed.

Lastly, as shown in FIG. 2, a pixel electrode connected to the drain electrode 66 and the storage capacitor conductor 64 by depositing and photo-etching an ITO layer or an IZO layer having a thickness of 400 kV to 500 kV. 82, contact auxiliary members 86 and 88 connected to the gate pad 24 and the data pad 68, respectively.

On the other hand, as a gas used in the pre-heating process before laminating ITO or IZO, it is preferable to use nitrogen, which is the metal film 24 exposed through the contact holes 72, 74, 76, and 78. This is to prevent the metal oxide film from being formed on the upper portions of 64, 66 and 68.

Referring to the operation and effects of the manufacturing method of the thin film transistor substrate for a display device according to the embodiment of the present invention, in the process of forming the channel region of the thin film transistor through a photolithography process using a photosensitive film pattern, By covering the data line exposed in the first wet etching process by coating an additional photoresist film, the line width of the data line in the second wet etching process may be further reduced.

As described above, according to the present invention, in the process of forming a channel region of the thin film transistor through a photolithography process using a photoresist pattern, an additional photoresist is coated to minimize the reduction in the line width of the data line due to wet etching. It is possible to provide a method of manufacturing a thin film transistor substrate for a display device which suppresses occurrence of defects caused by the defect.

Claims (5)

In the method for manufacturing a thin film transistor substrate for a display device, Forming a gate wiring including a gate line and a gate electrode connected to the insulating substrate; Forming a gate insulating film covering the gate wiring; Forming a semiconductor layer pattern on the gate insulating film; Forming an ohmic contact layer pattern on the semiconductor layer pattern; Forming a data line including a source electrode and a drain electrode formed on the ohmic contact layer and formed of the same layer, and a data line connected to the source electrode; Separation of the source electrode and the drain electrode may include a first wet etching process using a first photoresist pattern and a second photoresist pattern coated with an additional photoresist layer to cover the data wiring exposed by the first wet etching process. A method of manufacturing a thin film transistor substrate for a display device, which is performed through a second wet etching process. The method of claim 1, The first photoresist pattern may include a first portion positioned between the source electrode and the drain electrode, a second portion having a thickness thicker than the first portion, and a third portion having a thickness thinner than the first portion. A method of manufacturing a thin film transistor substrate for a display device. The method of claim 2, And the thickness of the third portion is almost zero. The method of claim 2, Removing the data wires of the third portion in the first wet etching process and removing the data wires of the first portion in the second wet etching process to separate and complete the source electrode and the drain electrode. A method of manufacturing a thin film transistor substrate for a display device. The method of claim 1, And the additional photosensitive film is formed by a slit coating method in which a photosensitive material is applied using a slit-shaped nozzle.

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