KR20030013151A - Fabricating method of thin film transistor plate - Google Patents

Abstract

PURPOSE: A TFT substrate fabricating method is provided to simultaneously form spacers with contact holes via the patterning of the contact holes with respect to an organic insulating film, thereby removing photoetching steps for forming the spacers. CONSTITUTION: A TFT substrate fabricating method includes the steps of forming gate wires including gate lines and gate electrodes on a substrate, forming a gate insulating film covering the gate wires, forming a semiconductor pattern on the gate insulating film, forming data wires including data lines, and source/drain electrodes on the gate insulating film and the semiconductor pattern, forming an organic insulating film(70) with a protrusion pattern of a first thickness for serving as spacers(71) and contact holes exposing the drain electrodes on the semiconductor pattern, all parts except the protrusion pattern and the contact holes being of a second thickness, and pixel electrodes(82) formed on the organic insulating film to be connected to the drain electrodes(66) via the contact holes.

Description

The manufacturing method of a thin film transistor substrate {FABRICATING METHOD OF THIN FILM TRANSISTOR PLATE}

The present invention relates to a method for manufacturing a thin film transistor substrate, and more particularly, to a method for manufacturing a thin film transistor substrate used in a liquid crystal display device.

The liquid crystal display is one of the most widely used flat panel display devices, and includes two substrates on which a plurality of electrodes for generating an electric field are formed, and a liquid crystal layer interposed between the two substrates.

An electrical signal is applied to the liquid crystal display to rearrange liquid crystal molecules of the liquid crystal layer, thereby controlling the amount of light transmitted to display an image.

A plurality of gate lines and a plurality of data lines cross each other to define a plurality of pixel regions on one substrate of the liquid crystal display, and each pixel region is connected to a switching element and a switching element electrically connected to the gate line and the data line. The pixel electrode is formed.

On the other hand, in order to increase the aperture ratio for improving the luminance of the panel, an organic insulating film having a low dielectric constant is used. In this case, the parasitic capacitance between the gate line, the data line, and the pixel electrode can be reduced, so that the pixel electrode has a gate line and data. It is possible to form so as to overlap a line, and can improve an aperture ratio. In addition, a patterned spacer is used to uniformly maintain a cell gap, which is a gap between two substrates.

However, when a pattern is formed on the organic insulating layer or a patterned spacer is formed, it is difficult to pursue a process simplification because the photolithography process using a mask must be performed separately.

An object of the present invention is to simplify the manufacturing process of a thin film transistor substrate.

1 is a layout view of a thin film transistor substrate according to a first exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view of the thin film transistor substrate taken along the cutting line II-II ′ shown in FIG. 1.

3A is a layout view of a substrate in a first manufacturing step for manufacturing a thin film transistor substrate according to the first embodiment of the present invention;

3B is a cross-sectional view of the substrate along the cutting line IIIb-IIIb 'of FIG. 3A,

4A is a layout view of a substrate in the next manufacturing step of FIG. 3A,

4B is a cross-sectional view of the substrate along the cutting line IVb-IVb ′ of FIG. 4A;

FIG. 5A is a layout view of a substrate in a subsequent manufacturing step of FIG. 4A,

5B is a cross-sectional view of the substrate along the cutting line Vb-Vb ′ of FIG. 5A;

FIG. 6A is a layout view of a substrate in a subsequent manufacturing step of FIG. 5A;

FIG. 6B is a cross-sectional view of the substrate along the cutting line VIb-VIb ′ of FIG. 6A;

FIG. 7 is a cross sectional view of the substrate in an intermediate fabrication step between FIGS. 5B and 6B;

8 is a layout view of a thin film transistor substrate according to a second exemplary embodiment of the present invention.

9 and 10 are cross-sectional views of the thin film transistor substrate taken along the cutting lines VIII-VIII and VIII-VIII shown in FIG.

11A is a layout view of a substrate in a first manufacturing step for manufacturing a thin film transistor substrate according to a second embodiment of the present invention;

11B and 11C are cross-sectional views of the substrate taken along the cutting line VIB-XIB 'of FIG. 11A;

FIG. 12A is a layout view of a substrate in a subsequent manufacturing step of FIG. 11A,

12B and 12C are cross-sectional views of the substrate taken along the cut lines XIIb-XIIb 'and XIIc-XIIc' of FIG. 12A;

13A through 17A and 13B through 17B are layout views of a substrate in an intermediate manufacturing step between FIGS. 11A and 12A and an intermediate manufacturing step between FIGS. 11B and 12B,

FIG. 18A is a layout view of a substrate in a subsequent manufacturing step of FIG. 13A,

18B and 18C are cross-sectional views of the substrate along the cutting lines Xb-Xb 'and XC-XC' of FIG. 18A, and FIG.

19A and 19B are layout views of a substrate in an intermediate fabrication step between FIGS. 12A and 18A and an intermediate fabrication step between FIGS. 12B and 18B,

20 is a layout view of a thin film transistor substrate according to a third exemplary embodiment of the present invention.

FIG. 21 is a cross-sectional view of the substrate taken along the cutting line VI-XI ′ of FIG. 20.

In order to solve this problem, in the present invention, the operation of forming a pattern on the organic insulating layer and the operation of forming the spacer are performed through a single photolithography process.

In detail, in the method for manufacturing a thin film transistor substrate according to the present invention, after forming a gate wiring including a gate line and a gate electrode on the substrate, a gate insulating film covering the gate wiring is formed. Subsequently, after the semiconductor pattern is formed on the gate insulating film, a data line including a data line, a source electrode, and a drain electrode is formed on the gate insulating film and the semiconductor pattern. Subsequently, a contact hole exposing the protruding pattern having a first thickness and the drain electrode is formed on the semiconductor pattern, and other portions other than the protruding pattern and the contact hole form an organic insulating layer pattern having a second thickness, and then the organic insulating layer pattern A pixel electrode connected to the drain electrode through the contact hole is formed thereon.

Here, in order to form the organic insulating film pattern, after forming a photosensitive organic insulating film covering the exposed entire surface of the substrate including the data wiring, selectively expose the photosensitive organic insulating film, without exposing the first portion where the spacer is to be formed The entire surface of the second portion where the contact hole is to be formed is exposed, the portions other than the first and second portions are partially exposed, and then the selectively exposed organic insulating film is developed.

At this time, the selective exposure of the organic insulating film is performed in which a non-exposed area is positioned in a first portion of the organic insulating layer, an exposure region is positioned in a second portion of the organic insulating layer, and a selective transmission region having a predetermined transmittance is positioned in the third portion. You can proceed using a mask. The selective transmission region of the mask may be formed with a slit pattern or a transflective pattern.

The selective exposure of the organic insulating film may be formed using a first mask that exposes the second portion of the organic insulating film and a second mask that exposes the third portion of the organic insulating film with a predetermined transmittance.

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a layout view of a thin film transistor substrate according to a first exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view of the thin film transistor substrate taken along the cutting line II-II ′ of FIG. 1.

Gate wirings 22, 24, and 26 formed of a low resistance metal material, for example, aluminum, molybdenum, chromium, and titanium, are formed on the insulating substrate 10. The gate wires 22, 24, and 26 are connected to the gate line 22 extending in the horizontal direction, the gate pad 24 connected to the end of the gate line 22 to receive a gate signal from the outside, and to transfer the gate signal to the gate line. And a gate electrode 26 of the thin film transistor connected to the gate line 22.

The gate wirings 22, 24, and 26 may be formed in a double layer or more structure in addition to the single layer structure. When the gate wirings 22, 24, and 26 are formed in a double layer structure, at least one of the two layers may be formed of a metal material having low resistance.

On the insulating substrate 10, a gate insulating film 30 made of an insulating material, for example, silicon nitride, covers the gate wirings 22, 24, and 26.

A semiconductor pattern 42 made of a semiconductor material, for example, amorphous silicon, is formed on the gate insulating layer 30 so as to overlap the gate electrode 26, and a semiconductor material doped with impurities is formed on the semiconductor pattern 42, for example, Ohmic contact layers 55 and 56 made of amorphous silicon doped with a high concentration of n-type impurities are formed.

On the ohmic contact layers 55 and 56 and the gate insulating layer 30, a metal material having excellent contact properties with the semiconductor layer and low resistance, for example, a data line 62 made of molybdenum series such as molybdenum or molybdenum alloy, 64, 65, 66 are formed.

The data lines 62, 64, 65, and 66 are connected to the ends of the data line 62 and the data line 62 formed in the vertical direction, and receive data from the outside and transfer the data pads to the gate line ( 64, a source electrode 65 protruding from the data line 62 and contacting the one ohmic contact layer 55 to form a part of the thin film transistor, and the other ohmic contact layer corresponding to the source electrode 65. And a drain electrode 66 in contact with 56 to form part of the thin film transistor.

An organic insulating pattern 70 made of an organic insulating material such as acrylic resin or BCB (BenzoCycloButane) is formed on the exposed front surface of the substrate including the data lines 62, 64, 65, and 66. In this case, the organic insulating layer pattern 70 may include a spacer 71 protruding at a height of 4.5 to 5.5 μm from the TFT, a first contact hole 72 exposing a part of the drain electrode 66, and a data pad. It has a second contact hole 74 exposing 64 and a third contact hole 76 exposing the gate pad 24 together with the gate insulating film 30, except for these parts 2-3 over the entire surface. It is formed flat at the height of 탆.

The pixel electrode 82, the auxiliary data pad 84, and the auxiliary gate pad 86 made of IZO or ITO are formed on the passivation layer 70. The pixel electrode 82 is electrically connected to the drain electrode 66 through the first contact hole 72 to receive an image signal from the data line 62. In addition, the auxiliary gate pad 84 and the auxiliary data pad 86 are electrically connected to the data pad 24 and the gate pad 64 through the second and third contact holes 74 and 76.

Next, a method of manufacturing the thin film transistor substrate according to the first embodiment of the present invention will be described with reference to FIGS. 1 and 2 and FIGS. 3A to 7B.

First, as shown in FIGS. 3A and 3B, a metal material layer having a low resistance characteristic, for example, an aluminum based layer is deposited on the substrate 10, and patterned by a photolithography process to form the gate line 22, Gate wirings 22, 24, and 26 including the gate pads 24 and the gate electrodes 26 are formed.

Next, as shown in FIGS. 4A and 4B, a gate insulating film 30 made of an insulating material, for example, silicon nitride, which covers the gate wirings 22, 24, and 26 is deposited on the substrate 10.

Next, the semiconductor layer and the semiconductor layer doped with impurities are sequentially stacked on the gate insulating layer 30, and then the semiconductor layer and the semiconductor layer doped with impurities are patterned by a photolithography process to form the ohmic contact layer pattern 52. The semiconductor pattern 42 is formed.

Next, as illustrated in FIGS. 5A and 5B, after depositing a metal material layer having an excellent contact property with a semiconductor layer and low resistance, for example, a molybdenum-based layer, on the entire surface of the substrate, a photolithography process is performed. Patterning is performed to form data wires 62, 64, 65, and 66 including a data line 62, a data pad 64, a source electrode 65, and a drain electrode 66.

Subsequently, the island-like ohmic contact layer 52 integrally formed using the source electrode 65 and the drain electrode 66 as a mask is etched to contact the source electrode 65 with the ohmic contact layer 55 and the drain electrode ( 66 into a resistive contact layer 56 in contact with it.

Next, as shown in FIGS. 6A and 6B, the first contact hole 72 and the data covering the entire surface of the substrate and exposing a portion of the spacer 71 and the drain electrode 66 protruding from the TFT. An organic insulating layer pattern 70 having a second contact hole 74 exposing the pad 64 and a third contact hole 76 exposing the gate pad 24 is formed along with the gate insulating layer 30.

The organic insulating layer pattern 70 may be formed through one photolithography process using one mask. This will be described with reference to FIG. 7 as follows.

First, an organic insulating layer L made of a photosensitive organic insulating material is coated on the exposed entire surface of the substrate including the data lines 62, 64, 65, and 66. The photosensitive organic insulating material may be prepared by mixing the photosensitive material with an organic insulating material such as acrylic resin or BCB.

Subsequently, light is irradiated to the photosensitive organic insulating layer L through a mask (not shown) having a partially different transmittance. At this time, in order to control the amount of light transmission, a slit or lattice pattern, or a mask in which the translucent film is partially patterned is used. In this case, the line width of the pattern located between the slits, or the interval between the patterns, that is, the width of the slits, is preferably smaller than the resolution of the exposure apparatus used for exposure. A thin film having a thickness or a thin film may be used.

At this time, in the photosensitive organic insulating layer L, the exposure area of the mask where all the light is exposed is positioned in the portion C where the first, second and third contact holes 72, 74, and 76 are to be formed. The non-exposed area of the mask is positioned in the portion A where the spacer 71 is to be formed, and the other portion B uses a mask so that the slit pattern or the translucent pattern is located.

When light is irradiated onto the photosensitive organic insulating layer L through the mask, the polymer is completely decomposed in the portion C corresponding to the exposure area of the mask, and in the portion B corresponding to the slit pattern or translucent film of the mask. Since the amount of irradiation is small, the polymer is decomposed to an appropriate thickness, for example, only about half of the thickness of the organic insulating film, and the polymer is hardly decomposed at the portion A corresponding to the unexposed region of the mask. If you increase the exposure time at this time, all the molecules are decomposed, so it should not be so.

As described herein, instead of using one mask, as another embodiment, two masks may be used to perform double exposure on the organic insulating film.

To this end, a first exposure process using a first mask for exposing the organic insulating portion C on which the first, second and third contact holes 72, 74, and 76 are to be formed, and the organic insulating layer on which the spacer is to be formed After the second exposure process using the second mask for exposing the remaining portions B and C except for the portion A is performed, the organic insulating layer pattern 70 may be formed by developing. At this time, it is preferable to adjust the exposure amount so that the organic insulating film can be exposed by an appropriate thickness without being completely decomposed in the second exposure process.

Developing the organic insulating film that is selectively exposed as described above leaves only the portion where the polymer molecules are not decomposed, and an organic insulating layer having a thickness thinner than the portion that is not irradiated with light is left in the central portion irradiated with less light. The organic insulating film pattern 70 as shown can be obtained.

In the above-described embodiment, the organic insulating layer pattern 70 is formed by using a positive photosensitive organic insulating material that is decomposed when developed in contact with light, and is removed. The organic insulating layer pattern 70 may be formed using a negative flat photosensitive organic insulating material in which only a portion of the portion remains. In this case, the non-exposed region of the mask is positioned in the organic insulating portion C on which the first, second, and third contact holes 72, 74, and 76 are to be formed, and the portion in which the spacer 71 is to be formed (A). ), The exposure area of the mask is positioned, and the other part B uses the mask so that the slit pattern of the mask is located or the translucent pattern is located.

Next, the third insulating hole 76 exposing the gate pad 24 is formed by etching the gate insulating layer 30 positioned below the organic insulating layer pattern 70 as a mask.

Thereafter, in order to increase the light transmittance of the organic insulating layer pattern 70, the operation of curing the organic insulating layer pattern may be further performed.

Next, as shown in FIGS. 1 and 2, the IZO layer or the ITO layer is deposited, and then patterned by a photolithography process to contact the drain electrode 66 through the first contact hole 72. The auxiliary data pad 84 and the auxiliary gate pad 86 are formed to contact the data pad 64 and the gate pad 24 through the pixel electrode 82, the second and third contact holes 74 and 76, respectively. do.

Subsequently, a subsequent process is performed to complete the manufacture of the thin film transistor substrate.

As described above, in the thin film transistor substrate according to the first exemplary embodiment of the present invention, the spacer is processed through a photolithography process for forming contact holes in the organic insulating layer without a separate photolithography process. Do.

FIG. 8 is a layout view of a thin film transistor substrate according to a second exemplary embodiment of the present invention, and FIGS. 9 and 10 are cross-sectional views taken along cut lines VII- ′ and VII- ′, respectively.

Gate wirings 22, 24, 26, and 28 formed of a low resistance metal material, for example, aluminum, molybdenum, chromium, and titanium, are formed on the insulating substrate 10. The gate lines 22, 24, 26, and 28 are connected to the gate lines 22 and the ends of the gate lines 22 extending in the horizontal direction and receive gate signals from the outside and transfer the gate pads 24 to the gate lines. And the gate line portions 22, 24, and 26 including the gate electrode 26 of the thin film transistor connected to the gate line 22, and the storage electrode 28 for the storage capacitor parallel to the gate line 22. Doing.

The storage electrode 28 overlaps with the conductor pattern 68 for the storage capacitor connected to the pixel electrode 82 to be described later to form a storage capacitor which improves the charge retention capability of the pixel. The pixel electrode 82 and the gate line to be described later will be described. If the holding capacity generated by the overlap of (22) is sufficient, it may not be formed.

The gate wirings 22, 24, 26, and 28 may be formed in a double layer or more structure in addition to the single layer structure. When the gate wirings 22, 24, 26, and 28 are formed in a double layer structure, at least one of the two layers is advantageously formed of a metal material having low resistance.

On the insulating substrate 10, a gate insulating film 30 made of an insulating material, for example, silicon nitride, covers the gate wirings 22, 24, 26, and 28.

Semiconductor patterns 42 and 48 made of a semiconductor material, for example, amorphous silicon, are formed on the gate insulating layer 30, and semiconductor materials, for example, doped with impurities, are doped on the semiconductor patterns 42 and 48. Resistive contact layer patterns 55, 56 and 58 made of amorphous silicon are formed.

On the ohmic contact layer patterns 55, 56, and 58, a data material 62, 64, 65, 66, and 68 made of a metal material having excellent contact characteristics with the semiconductor layer and low resistance, for example, molybdenum series, is formed. Formed.

The data lines 62, 64, 65, 66, and 68 are formed in the vertical direction and connected to the data line 62 and the data line 62 crossing the gate line 22 to apply a gate signal from the outside. The data pad 64 and the data line 62 which receive and transfer the gate line to the source line 65 and protrude from the data line 62 to contact the one ohmic contact layer 55 to form a part of the thin film transistor. A sustain positioned over the data line portions 62, 64, 65, 66 and the sustain electrode 28, including the drain electrode 66 correspondingly contacting the other ohmic contact layer 56 to form part of the thin film transistor. The conductor pattern 68 for capacitors is included.

The semiconductor patterns 42 and 48 include a semiconductor pattern 42 for a thin film transistor and a semiconductor pattern 48 for a storage capacitor, which are regions between the source electrode 65 and the drain electrode 66, that is, the channel region of the thin film transistor. Except for the above, the data lines 62, 64, 65, 66, 68 and the ohmic contact layer patterns 55, 56, 58 have the same shape. That is, the semiconductor capacitor pattern 48 for the storage capacitor is the same as the conductor pattern 68 for the storage capacitor and the contact layer pattern 58 for the storage capacitor, whereas the semiconductor pattern 42 for the thin film transistor has the data line 62 described later. ), The same as the data line portions 62, 64, 65, 66 formed by the data pad 64, the source electrode 65, and the drain electrode 66, but between the source electrode 65 and the drain electrode 66. It further includes a region defined as a channel of the thin film transistor located.

Here, the ohmic contact layer patterns 55, 56, and 58 serve to lower the contact resistance between the lower semiconductor patterns 42 and 48 and the upper data lines 62, 64, 65, 66, and 68. And the same shape as that of the data wirings 62, 64, 65, 66, and 68. At this time, one ohmic contact layer pattern 55 is in contact with the integral data line 62, the data pad 64 and the source electrode 65, and the other ohmic contact layer pattern 56 is connected to the drain electrode ( 66, and another contact layer pattern 58 is in contact with the conductor pattern 68 for the storage capacitor.

An organic insulating pattern 70 made of an organic insulating material such as acrylic resin or BCB (BenzoCycloButane) is formed on the exposed front surface of the substrate including the data lines 62, 64, 65, and 66. In this case, the organic insulating layer pattern 70 may include a spacer 71 protruding at a height of 4.5 to 5.5 μm from the TFT, a first contact hole 72 exposing a part of the drain electrode 66, and a data pad. A fourth contact hole exposing the third contact hole 76 exposing the gate pad 24 and the fourth contact hole exposing the conductor pattern 68 for the storage capacitor together with the second contact hole 74 exposing the 64 and the gate insulating film 30. (78), and except these parts, it is formed flat at the height of 2-3 micrometers over the whole surface.

The pixel electrode 82, the auxiliary gate pad 84, and the auxiliary data pad 86 made of IZO or ITO are formed on the organic insulating layer pattern 70. The pixel electrode 82 contacts the drain electrode 66 and the conductive pattern 68 for a storage capacitor through the first and fourth contact holes 72 and 78. The auxiliary data pad 84 and the auxiliary gate pad 86 are in contact with the data pad 24 and the gate pad 64 through the second and third contact holes 74 and 76.

Next, a method of manufacturing the thin film transistor substrate according to the second exemplary embodiment of the present invention will be described with reference to FIGS. 11A through 19B and FIGS. 8, 9, and 10.

First, as shown in FIGS. 11A, 11B, and 11C, a metal material layer having a low resistance characteristic, for example, an aluminum based layer is deposited on the substrate 10, and patterned by a photolithography process to form a gate line ( 22, the gate wirings 22, 24, 26, 28 including the gate pad 24, the gate electrode 26, and the conductor pattern 28 for a storage capacitor are formed.

Next, a gate insulating film 30 made of an insulating material, for example, silicon nitride, which covers the gate wirings 22, 24, 26, and 28 is deposited on the substrate 10.

12A, 12B, and 12C, a semiconductor layer, a semiconductor layer doped with impurities, and a metal layer for data wiring are successively deposited on the gate insulating layer 30, and the multilayer is patterned by a photolithography process. Semiconductor pattern 42, 48, ohmic contact layer patterns 55, 56, and 58, and data pad 64, source electrode 65, drain electrode 66, and storage electrode 68 for a storage capacitor. Data wirings 62, 64, 65, 66, 68 are formed. The metal layer for data wiring is preferably formed of a metal material layer having excellent contact characteristics with the semiconductor layer and having low resistance, for example, molybdenum series.

The ohmic contact layer patterns 55, 56, and 58 having the same pattern are in contact with the lower end of the data wires 62, 64, 65, 66, and 68, and the ohmic contact layer patterns 55, 56, and 58 are in contact with the bottom of the data line 62, 64, 65, 66, and 68. The semiconductor patterns 42 and 48 including the thin film transistor semiconductor pattern 42 and the storage capacitor semiconductor pattern 48 are in contact with each other. The thin film transistor semiconductor pattern 42 is the same as the data line parts 62, 64, 65, and 66, and further includes a region defined as a channel of the thin film transistor positioned between the source electrode 65 and the drain electrode 66. Include.

The data lines 62, 64, 65, 66, and 68, the ohmic contact layers 55, 56, and 58, and the semiconductor patterns 42 and 48 may be formed using only one mask. This will be described with reference to FIGS. 13A to 17B.

First, as shown in FIGS. 13A and 13B, the semiconductor layer 40 and the semiconductor layer 50 doped with impurities are successively deposited on the gate insulating film 30 using chemical vapor deposition. Subsequently, the data wiring metal layer 60 is deposited.

Next, as shown in FIGS. 14A and 14B, a photosensitive film is coated on the data wiring metal layer 60, and then irradiated with light through a mask (not shown), followed by development to develop the photosensitive film patterns 112 and 114. Form. In this case, the photoresist patterns 112 and 114 may have a first portion 112 of the photoresist layer positioned at the data line portion A between the channel portion C of the thin film transistor, that is, between the source electrode 65 and the drain electrode 66. It is formed to be thicker than the second portion 114 of the positioned photosensitive film, and the other portion (B) is formed so as not to remain. The ratio of the thickness of the first portion 112 of the photosensitive film of the second portion 114 of the photosensitive film should be different depending on the process conditions in the etching process, which will be described later, but the thickness of the second portion 114 is determined by the first portion 112. It is preferable to make into 1/2 or less of thickness.

As such, photoresist patterns having partially different thicknesses are formed using one mask having partially different transmittance. In order to control the light transmission, a slit or lattice pattern or a mask with a translucent film is used. In this case, the line width of the pattern located between the slits, or the interval between the patterns, that is, the width of the slits, is preferably smaller than the resolution of the exposure apparatus used for exposure. A thin film having a thickness or a thin film may be used.

When the photosensitive film is irradiated with light through such a mask, the polymers are completely decomposed at the portion (C) directly exposed to the light, and the polymers are completely decomposed because the amount of light is less at the portion (B) corresponding to the slit pattern or the translucent film. The polymer is hardly decomposed in the part A covered by the light shielding film. In this case, if the exposure time is extended, all molecules are decomposed, so it should not be so.

When the selective exposed photoresist is developed, only portions where polymer molecules are not decomposed remain, and a photoresist having a thickness thinner than a portion that is not irradiated with light is left in the central portion irradiated with little light.

Next, as shown in FIGS. 15A and 15B, the exposed metal layer 60 of the other portion B is etched using the photoresist patterns 112 and 114 as a mask, and the semiconductor layer doped with impurities below Expose (50).

In this way, only the metal layer patterns 67 and 68 in the channel portion C and the data wiring portion A remain, and the metal layer in the other portion B is removed, and the semiconductor layer 50 doped with impurities located thereunder is removed. ) Is revealed. The metal layer pattern 68 is a conductor pattern for a storage capacitor, and the metal layer pattern 67 is a data wiring metal layer in which the source electrode 65 and the drain electrode 66 are not separated yet and exist in an integrated state.

Next, as shown in FIGS. 16A and 16B, the semiconductor layer 50 doped with the exposed impurities of the other portion B and the semiconductor layer 40 thereunder together with the second portion 114 of the photoresist film. Simultaneously removed by dry etching. The etching is performed under the condition that the photoresist patterns 112 and 114, the semiconductor layer 50 and the semiconductor layer 40 doped with impurities are simultaneously etched and the gate insulating film 30 is not etched. At this time, it is preferable to etch under the condition that the etching ratios of the photoresist patterns 112 and 114 and the semiconductor layer 40 are almost the same. For example, by using a mixed gas of SF ₆ and HCl or a mixed gas of SF ₆ and O ₂ , the two films can be etched to almost the same thickness.

When the etch ratios of the photoresist patterns 112 and 114 and the semiconductor layer 40 are the same, the thickness of the second portion 114 of the photoresist layer is the sum of the thicknesses of the semiconductor layer 40 and the semiconductor layer 50 doped with impurities. It must be less than or equal to

In this way, the second portion 114 of the photoresist film positioned in the channel portion C is removed to expose the metal layer pattern 67 of the channel portion C, and the semiconductor layer 50 doped with impurities in the other portion B. And the semiconductor layer 40 is removed to expose the gate insulating layer 30 thereunder. On the other hand, since the first portion 112 of the photosensitive film of the data wiring portion A is also etched, the thickness becomes thin.

In this step, the semiconductor patterns 42 and 48 including the thin film transistor semiconductor pattern 42 and the storage capacitor semiconductor pattern 48 are completed.

The ohmic contact layer 57 is formed on the thin film transistor semiconductor pattern 42 in the same pattern as the semiconductor pattern 42. The ohmic contact layer 58 is also formed on the semiconductor capacitor 48 for the storage capacitor. It is formed in the same pattern as 48).

Subsequently, residues of the second portion of the photoresist film remaining on the surface of the metal layer pattern 67 of the channel portion C are removed by ashing.

Next, as shown in FIGS. 17A and 17B, the metal layer pattern 67 positioned in the channel portion C and the ohmic contact layer pattern 57 thereunder, using the first portion 112 of the remaining photoresist pattern as a mask. ) Etch the part.

In this case, a portion of the semiconductor pattern 42 may be removed to reduce the thickness, and the first portion 112 of the photoresist pattern may also be etched to a certain thickness. At this time, the etching must be performed under the condition that the gate insulating layer 30 is not etched, and the first portion 112 of the photoresist pattern is etched to expose the lower data lines 62, 64, 65, 66, and 68. It is preferable to thicken the photosensitive film pattern so that there is no.

In this way, the source electrode 65 and the drain electrode 66 are separated from the metal layer pattern 67 to complete the data line 62, the source electrode 65, and the drain electrode 68. The patterns 55, 56 and 58 are completed.

18A, 18B, and 18C, the first portion 112 of the photoresist pattern remaining on the substrate is removed through ashing.

Next, the first contact hole 72 exposing a portion of the drain electrode 66, the spacer 71 protruding from the TFT, and the second contact hole exposing the data pad 64. 74 and an organic insulating film pattern 70 having a third contact hole 76 exposing the gate pad 24 and a fourth contact hole 78 exposing the conductor pattern 68 for the storage capacitor together with the gate insulating film 30. ).

The organic insulating layer pattern 70 may be formed through one photolithography process using one mask. This will be described with reference to FIGS. 19A and 19B as follows.

First, an organic insulating layer L made of a photosensitive organic insulating material is coated on the exposed entire surface of the substrate including the data lines 62, 64, 65, 66, and 68. The photosensitive organic insulating material may be prepared by mixing the photosensitive material with an organic insulating material such as acrylic resin or BCB.

Subsequently, light is selectively irradiated onto the photosensitive organic insulating layer L through a mask (not shown) having a partially different transmittance. At this time, in order to adjust the amount of light transmission, a mask having a partially different transmittance is used as described in the process of describing the thin film transistor substrate according to the first embodiment of the present invention.

At this time, in the photosensitive organic insulating layer L, the exposure area of the mask in which all the light is exposed in the portion C in which the first, second, third and fourth contact holes 72, 74, 76, and 78 will be formed. In this position, the non-exposed region of the mask is positioned in the portion A where the spacer 71 is to be formed, and the other portion B uses a mask so that the slit pattern of the mask is positioned or the translucent pattern is positioned.

When the light is irradiated onto the photosensitive organic insulating layer L through the mask, the polymer is completely decomposed in the portion C corresponding to the exposure area of the mask, and in the portion B corresponding to the slit pattern or translucent film of the mask. Since the amount of irradiation is small, the polymer is decomposed to an appropriate thickness, for example, only about half of the thickness of the organic insulating film, and the polymer is hardly decomposed at the portion A corresponding to the unexposed region of the mask. If you increase the exposure time at this time, all the molecules are decomposed, so it should not be so.

Here, instead of using one mask, as another embodiment, two masks may be used to perform double exposure on the organic insulating film.

To this end, a first exposure process using a first mask that exposes the organic insulating portion C on which the first, second, third and fourth contact holes 72, 74, 76, and 78 are to be formed, and the spacer After the second exposure process using the second mask for exposing the remaining portions (B, C) except for the organic insulating portion (A) to be formed, respectively, proceeds, and then develops to form the organic insulating layer pattern (70). . At this time, it is preferable to adjust the exposure amount so that the organic insulating film can be exposed by an appropriate thickness without being completely decomposed in the second exposure process.

When the selective exposure of the organic insulating film is developed, only the portion where the polymer molecules are not decomposed remains, and an organic insulating film having a thickness thinner than the portion not irradiated with light is left in the central portion irradiated with little light. The organic insulating film pattern 70 as shown can be obtained.

In the above-described embodiment, the organic insulating layer pattern 70 is formed by using a positive photosensitive organic insulating material that is decomposed when developed in contact with light, and is removed. The organic insulating layer pattern 70 may be formed by using the negative photosensitive organic insulating material in which only a portion thereof remains. In this case, the non-exposed area of the mask is positioned in the organic insulating portion C on which the first, second, third and fourth contact holes 72, 74, 76, and 78 are to be formed, and the spacer 71 is disposed. In the portion A to be formed, the exposure area of the mask is positioned, and in the other portion B, the mask is used so that the slit pattern of the mask is located or the translucent pattern is located.

Next, the third insulating hole 76 exposing the gate pad 24 is formed by etching the gate insulating layer 30 positioned below the organic insulating layer pattern 70 as a mask.

Thereafter, in order to increase the light transmittance of the organic insulating layer pattern 70, the operation of curing the organic insulating layer pattern may be further performed.

Next, again, as shown in FIGS. 8, 9, and 10, the IZO layer or the IZO layer is deposited, and then patterned by a photolithography process through the first and fourth contact holes 72 and 78. The data pad 64 and the gate pad 24 through the pixel electrode 82 and the second and third contact holes 74 and 76 in contact with the drain electrode 66 and the conductor pattern 68 for the storage capacitor. Auxiliary data pads 84 and auxiliary gate pads 86 that contact each other are formed.

Subsequently, a subsequent process is performed to complete the manufacture of the thin film transistor substrate.

As described above, in the thin film transistor substrate according to the second exemplary embodiment of the present invention, the spacer is processed through a photolithography process for forming contact holes in the organic insulating layer without a separate photolithography process. Do. In addition, since the data wiring and the semiconductor layer are formed at the same time by using one mask, it is more advantageous in simplifying the process.

The present invention is applicable to manufacturing thin film transistor substrates of various structures.

19 is a layout view of a thin film transistor substrate according to a third exemplary embodiment of the present invention, and FIG. 20 is a cross-sectional view of the thin film transistor substrate taken along the cutting line VIII-V ′ shown in FIG. 19.

The thin film transistor substrate according to the third embodiment of the present invention has a structure in which liquid crystal molecules are oriented vertically with respect to the upper and lower substrates in order to widen the viewing angle, and a predetermined opening pattern or protrusions are formed on the pixel electrode and the common electrode thereof. Branch represents the lower substrate used for the liquid crystal display device.

Gate wirings 121, 122, and 123 including the gate line 121, the gate electrode 122, and the gate pad 123, the storage capacitor line 124, and the storage electrodes 125, 126, and 127 on the substrate 110. ) And storage capacitor wirings 124, 125, 126, 127, 128, and 129 including the sustain electrode connection portions 128 and 129.

The gate insulating film 130 covers the gate wirings 121, 122, 123 and the storage capacitor wirings 124, 125, 126, 127, 128, and 129.

The semiconductor layer 141 and the pair of ohmic contacts 152 and 153 are formed on the gate insulating layer 130. In addition, on the gate insulating layer 130, the ohmic contact layer 153 corresponding to the source electrode 162 and the source electrode 162 connected to the data line 161 and the data line 161 to contact the ohmic contact layer 152. ), Data lines 161, 162, 163, and 164 including a drain electrode 163 and a data pad 164 are formed.

The organic insulating layer pattern 70 covers the entire exposed surface of the substrate including the data lines 161, 162, 163, and 164. The organic insulating layer pattern 70 may include a spacer 171 protruding at a height of 4.5 to 5.5 μm from the TFT, a first contact hole 172 exposing a part of the drain electrode 163, and a data pad ( A second contact hole 174 exposing 164 and a third contact hole 173 exposing the gate pad 123 together with the gate insulating film 130, except for these portions, 2 to 3 μm over the entire surface It is formed flat at the height of.

The data and gate pads are formed on the organic insulating layer pattern 170 through the pixel electrode 82 and the second and third contact holes 174 and 173, which contact the drain electrode 163 through the first contact hole 172. Auxiliary data and auxiliary gate pads 187 and 188 in contact with 164 and 123 are formed. In this case, the pixel electrode 180 is divided into two first and second small regions 181 and 182 disposed side by side and one middle region 183 disposed below the first electrode. And the second regions 181 and 182 are connected through the first connector 185, and the second small region 182 and the middle region 183 are connected through the second and third connectors 184 and 185. It has a pattern.

A liquid crystal display device is manufactured by attaching a thin film transistor substrate having such a structure to an upper substrate on which a common electrode (not shown) having an opening pattern as shown by a dotted line in FIG. 19 is bonded. In such a liquid crystal display, the pattern of the pixel electrode 180 and the opening pattern of the common electrode (shown as dotted lines) divide and align the liquid crystal to realize a plurality of liquid crystal domains in one pixel area, thereby realizing a wide viewing angle. Do.

The manufacturing process of the thin film transistor substrate according to the third embodiment of the present invention is different except that the pattern shapes of the respective structures are different and the storage capacitor wirings 124, 125, 126, 127, 128, and 129 must be further formed. It is the same as the manufacturing process of the thin film transistor according to the first embodiment of the present invention.

That is, the gate wirings 121, 122, 123 and gate wirings 124, 125, 126, 127, and 128 including the gate line 121, the gate electrode 122, and the gate pad 123 on the insulating substrate 110. 129 is formed, and a gate insulating film 130 covering these wirings is formed. Next, the semiconductor layer 141 and the ohmic contact layer are formed, and the data wires 161 and 162 including the data line 161, the source electrode 162, the drain electrode 163, and the data pad 164 are formed thereon. After the 163 and 164 are formed, the ohmic contact layer is separated using the source electrode 163 and the drain 164 as a mask. Subsequently, a first contact hole 72 exposing a portion of the spacer 71 and the drain electrode 66 protruding from the thin film transistor TFT on the front surface of the substrate including the data lines 161, 162, 163 and 164. After forming the organic insulating film pattern 170 having the second contact hole 74 exposing the data pad 64 and the third insulating hole 76 exposing the gate pad 24 together with the gate insulating film 30, Data and gate pads 164 through the pixel electrode 180 and the second and third contact holes 173 and 174 contacting the drain electrode 164 through the first contact hole 172 on the organic insulating layer pattern 170. And auxiliary data and auxiliary gate pads 187 and 188 in contact with 123.

In this case, the organic insulating layer pattern 170 is formed by the same process as the method for manufacturing the thin film transistor substrate according to the first and second embodiments of the present invention.

In the present invention, since the contact hole is formed at the same time as the contact hole is formed through the process of patterning the contact hole in the organic insulating film, the photolithography process for forming the spacer, for example, photosensitive film coating, photosensitive film exposure and development all processes The manufacturing process of the thin film transistor substrate can be simplified.

Claims (5)

Forming a gate wiring including a gate line and a gate electrode on the substrate, Forming a gate insulating film covering the gate wiring; Forming a semiconductor pattern on the gate insulating layer; Forming a data line including a data line, a source electrode, and a drain electrode on the gate insulating layer and the semiconductor pattern; Forming an organic insulating pattern having a second thickness on the semiconductor pattern and a contact hole exposing the drain electrode, wherein portions other than the protrusion pattern and the contact hole have a second thickness; Forming a pixel electrode connected to the drain electrode through the contact hole on the organic insulating layer pattern Method of manufacturing a thin film transistor substrate comprising a. In claim 1, Forming the organic insulating layer pattern, Forming a photosensitive organic insulating layer covering an exposed entire surface of the substrate including the data line; Selectively exposing the photosensitive organic insulating layer, without exposing a first portion where the spacer is to be formed, exposing a second portion where the contact hole is to be formed, and exposing a portion other than the first and second portions. Doing; Developing the selectively exposed organic insulating layer Method of manufacturing a thin film transistor substrate comprising a. In claim 2, In the selective exposure of the organic insulating layer, a non-exposed region is positioned at a first portion of the organic insulating layer, an exposure region is positioned at a second portion of the organic insulating layer, and a selective transmission region having a predetermined transmittance is positioned at the third portion. The manufacturing method of a thin film transistor board which advances using the mask to make. In claim 3, The selective transmission region of the mask is a manufacturing method of a thin film transistor substrate in which a slit pattern or a transflective pattern is formed. In claim 2, The selective exposure of the organic insulating layer is performed using a first mask that exposes a second portion of the organic insulating layer and a second mask that exposes a third portion of the organic insulating layer with a predetermined transmittance. .