KR100740927B1 - Thin film transistor panels for liquid crystal display and methods for manufacturing the same - Google Patents

Abstract

A data line including a data line, a light blocking film which is a branch of the data line, and a data pad connected to an end portion of the data line is formed on the insulating substrate as a single layer or a double layer, and the edge portion on the substrate covers the data line. To form a red, green, blue color filter. Next, an organic insulating layer covering the data line and the color filter is formed and patterned to form a first contact hole exposing the data line. Subsequently, a semiconductor layer, a gate insulating film, and a gate conductive layer are sequentially stacked on the organic insulating film, and a photosensitive film is coated thereon. Subsequently, a photoresist pattern is formed by a photolithography process using a mask having a partially different transmittance, and the three-layer film is etched using the mask as an etch mask to complete a semiconductor pattern connected to the data line through the first contact hole, and the gate line and the gate A gate wiring including a gate electrode connected to a line and a gate pad connected to an end portion of the gate line and a gate insulating layer pattern thereunder are completed. Subsequently, high concentration impurities are implanted into the semiconductor pattern using the gate wiring as a mask to form source and drain regions on both sides of the gate electrode, and metals capable of silicide formation are deposited, annealed and removed to source and drain regions. Switch to the electrodes for drain and drain respectively. Subsequently, a passivation layer covering the gate wiring and the semiconductor pattern and having a second contact hole exposing the drain electrode is formed, and a pixel electrode connected to the drain electrode through the second contact hole is formed thereon.

Color filter, mask, photoresist, coupling capacitance, self matching

Description

Thin film transistor substrate for liquid crystal display device and manufacturing method thereof {THIN FILM TRANSISTOR PANELS FOR LIQUID CRYSTAL DISPLAY AND METHODS FOR MANUFACTURING THE SAME}

1 is a layout view of a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view of the thin film transistor substrate of FIG. 1 taken along the line II-II '.

3A is a layout view of a thin film transistor substrate in a first step of manufacturing a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention.

3B is a cross-sectional view taken along line IIIb-IIIb 'of FIG. 3A.

4A is a layout view of a thin film transistor substrate in a second step of manufacturing in accordance with an embodiment of the invention,

4B is a cross-sectional view taken along the line IVb-IVb 'of FIG. 4A.

5A is a layout view of a thin film transistor substrate in a third step of manufacturing according to an embodiment of the present invention;

5B is a cross-sectional view taken along the line Vb-Vb ′ in FIG. 5A.

6A is a layout view of a thin film transistor substrate in a fourth step of manufacturing in accordance with an embodiment of the invention,

FIG. 6B is a cross-sectional view taken along line VIb-VIb ′ in FIG. 6A.

FIG. 7 is a cross-sectional view taken along line VIb-VIb ′ in FIG. 6A and shows the next step in FIG. 5B.

8 and 9 are cross-sectional views taken along the line VIb-VIb 'at 6a, respectively, illustrating the next steps of FIG.

FIG. 10 is a cross-sectional view taken along line VIb-VIb ′ at 6a and sequentially illustrates the next step of FIG. 9;

11A is a layout view of a thin film transistor substrate in a fifth step of manufacturing in accordance with an embodiment of the invention,

FIG. 11B is a cross-sectional view taken along the line XIb-XIb ′ of FIG. 11A;

12A is a layout view of a thin film transistor substrate in a sixth step manufactured according to an embodiment of the present invention;

FIG. 12B is a cross-sectional view taken along the line XIIb-XIIb ′ in FIG. 12A.

The present invention relates to a method for manufacturing the thin film transistor substrate for a liquid crystal display device.

The liquid crystal display is one of the most widely used flat panel display devices. The liquid crystal display includes two substrates on which electrodes are formed and a liquid crystal layer interposed therebetween, thereby rearranging the liquid crystal molecules of the liquid crystal layer by applying a voltage to the electrode. Device to display an image by adjusting the amount of transmitted light.

Among the liquid crystal display devices, a liquid crystal display device having a thin film transistor for switching the voltage applied to the electrode and having electrodes formed on each of the two substrates is used. One of the two substrates includes a thin film transistor and a pixel electrode. In general, the other substrate is formed with a color filter and a black matrix.

In order to improve the luminance of such a liquid crystal display device, it is important to secure a high aperture ratio of the panel. At this time, the most important factor for reducing the aperture ratio is to secure the distance between the data line and the pixel electrode due to the parasitic capacitance due to the coupling effect generated between the data line and the pixel electrode and the line width of the black matrix due to misalignment of the two substrates. In order to solve this problem, a method of providing an organic insulating material having a low dielectric constant between the data line and the pixel electrode or forming a color filter on the same substrate as the thin film transistor has been proposed.

However, in the manufacturing method of the liquid crystal display device, in the latter case, a low-cost color filter manufacturing process is performed after an expensive thin film transistor manufacturing process, and the defects in the color filter process adversely affect the final yield. It can increase the cost. In addition, in the former case, there is a problem that the storage capacitance formed between the gate line and the pixel electrode cannot be sufficiently secured.

SUMMARY OF THE INVENTION The technical problem to be solved by the present invention is to secure an aperture ratio and to improve process yield, and to minimize parasitic capacitance between the signal wiring and the gate electrode and the drain electrode of the pixel electrode or the thin film transistor. It is to provide a substrate and a manufacturing method thereof.

Another object of the present invention is to provide a method of manufacturing a new liquid crystal display device, which can minimize manufacturing costs.

In order to achieve this problem, in the present invention, a color filter is formed before the thin film transistor and a data line is formed below the color filter to be used as a light blocking film that blocks light incident to the black matrix and the thin film transistor, and partially different thicknesses. The semiconductor pattern and the gate wiring are formed together using a photoresist pattern having an etch mask to simplify the process.

In addition, in order to achieve the above object, in the present invention, the silicide forming process and the ion doping process are formed by self alignment.

First, a data line including a data line is formed on an insulating substrate, and a red, green, and blue color filter is formed thereon, and has a first contact hole for exposing the data line, and an insulating film covering the data line and the color filter. To form. Subsequently, a semiconductor pattern connected to the data line through the first contact hole, a gate insulating film pattern, and a gate wiring including the gate line and the gate electrode are sequentially formed on the insulating film, and the second wiring has a second contact hole that exposes the semiconductor pattern. A protective film covering the semiconductor pattern is formed. Subsequently, a pixel wiring including a pixel electrode connected to the semiconductor pattern is formed on the passivation layer through the second contact hole.

The gate line, the gate insulating layer pattern, and the semiconductor pattern may be formed by a photolithography process using one mask. At this time, in order to form a gate wiring, a semiconductor pattern, and a gate insulating film pattern, a semiconductor layer, a gate insulating film, and a gate conductive layer are sequentially deposited on the insulating film, and a photosensitive film is coated on the gate conductive layer. Subsequently, the photosensitive film is exposed and developed through a mask to remove the first portion corresponding to the gate wiring, the second portion corresponding to the semiconductor pattern having a thickness thinner than the first portion and not covering the gate wiring, and the photosensitive film is removed. And a third portion positioned at a portion other than the second portion. First, the gate conductive layer under the third portion, the gate insulating layer under the third portion, and the semiconductor layer under the same are etched to complete a semiconductor pattern and to remove the photoresist pattern on the second portion. Subsequently, the gate conductive layer and the gate insulating film under the substrate are etched using the photosensitive film pattern of the first portion to complete the gate wiring and the gate insulating film pattern, and the remaining photosensitive film pattern is removed.

In this case, the gate line and the gate insulating layer pattern may be formed in the same shape.

The mask used in the photolithography process includes a first part where light cannot be transmitted completely, a second part where light can be partially transmitted, and a third part where light can be completely transmitted, and the photoresist pattern is a positive photoresist film. The first, second, and third portions of are preferably aligned to correspond to the first, second, and third portions of the photosensitive film pattern during the exposure process.

The second portion of the mask preferably includes a pattern that is smaller in size than the resolution of the light source used in the translucent film or the exposure step, and the second portion of the photosensitive film pattern may be formed through reflow.

After the gate wiring forming step, the method may further include forming a source region and a drain region on both sides of the gate electrode by implanting high concentration impurities into the semiconductor pattern using the gate wiring as a mask. In addition, after the source region and the drain region forming step, a metal material capable of forming silicide is deposited on the substrate, and an annealing process is performed to form source and drain electrodes formed of silicide on the source and drain regions. The method may further include removing the substance.

The gate wiring further includes a gate pad connected to the gate line to receive a signal from the outside, and the data wiring further includes a data pad connected to the data line to receive a signal from the outside, and the protective layer and the insulating layer include the gate pad and the data. Forming auxiliary gate pads and auxiliary data pads having third and fourth contact holes exposing the pads and connected to the gate pads and the data pads through the third and fourth contact holes, and having the same layer as the pixel electrode. It may further include.

Further, in the data line forming step, a light blocking film positioned in a portion corresponding to the semiconductor layer pattern or the gate line may be further formed by branching of the data line or independent wiring separated from the data line.

At this time, the insulating film is preferably formed of an organic insulating film.

In the thin film transistor substrate for a liquid crystal display device according to the present invention, data wirings including data lines extending in one direction are formed on an insulating substrate, and red, green, and blue color filters are formed on pixels on the substrate. An insulating film covering the data line and the color filter and having a first contact hole for exposing the data line is formed on the substrate, and a semiconductor pattern connected to the data line through the first contact hole is formed on the insulating film. A gate wiring including a gate electrode and a gate electrode connected to the gate line and the gate line defining the pixel by crossing the gate insulating layer pattern and the data line and overlapping the semiconductor pattern is sequentially formed on the semiconductor pattern. A passivation film having a second contact hole exposing the semiconductor pattern covers the gate wiring and the semiconductor pattern not covered by the gate wiring, and a pixel electrode connected to the semiconductor pattern is formed in the pixel on the passivation layer through the second contact hole.

Here, the edges of the red, green, and blue color filters preferably cover the edges of the data lines, and the insulating film is preferably made of an organic insulating material.

The semiconductor pattern includes source and drain regions positioned on both sides of the channel region and the channel region below the gate electrode and doped with high concentration impurities and connected to the data lines and the pixel electrodes, respectively. The part may further include a source and drain electrode made of silicide.

The source and drain electrodes are formed on the semiconductor layer not covered by the gate electrode, and the gate wiring and the gate insulating layer pattern may be formed in the same shape. In addition, the semiconductor pattern except for the source and drain regions may be formed in the same shape as the gate wiring.

The gate wiring further includes a gate pad connected to the gate line to receive a signal from the outside, and the data wiring further includes a data pad connected to the data line to receive a signal from the outside, and the protective layer and the insulating layer include the gate pad and the data. And an auxiliary gate pad and an auxiliary data pad having third and fourth contact holes exposing the pads and connected to the gate pad and the data pad through the third and fourth contact holes and formed of the same layer as the pixel electrode. It may include.

In addition, the data line may further include a light blocking film which is separated from the branch or data line of the data line and positioned in a portion corresponding to the semiconductor layer pattern or the gate line. The data line and the gate line may be made of aluminum, an aluminum alloy, or copper. It is preferable that it is formed of a single layer of a copper alloy or silver or silver alloy or a multilayer film including a conductive film made of chromium or molybdenum or molybdenum alloy or chromium nitride or molybdenum with excellent contact properties.

Next, a thin film transistor substrate for a liquid crystal display device and a method of manufacturing the same according to embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. do.

As described above, in the present invention, a color filter is formed before the thin film transistor, and a data line is formed below the color filter to be used as a black matrix, thereby securing an aperture ratio and ensuring an improved process yield and sufficiently low parasitic capacitance. In addition, the semiconductor pattern and the gate wiring are formed together using a photosensitive film pattern having a partly different thickness as an etching mask to simplify the manufacturing process.

First, the structure of a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.

1 is a layout view of a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view of the thin film transistor substrate illustrated in FIG. 1 taken along the line II-II ′.

First, a lower layer 201 made of copper or a copper alloy or aluminum or an aluminum alloy and an upper layer 201 made of chromium or molybdenum or molybdenum alloy or chromium nitride or molybdenum nitride are included on the lower insulating substrate 100. The data wiring is formed. The data line is connected to the data line 20 and the data line 20 extending in the vertical direction so that the data pad 24 and the data line 20 receive an image signal from the outside and transmit the image signal to the data line 20. And a light blocking film 21 for blocking light incident from the lower portion of the substrate 100 to the semiconductor pattern 52 of the thin film transistor which is subsequently formed. Here, the light blocking film 21 also has a function of a black matrix to block the light leaking, and may be formed of a disconnected wiring separated from the data line 20, and may have a shape similar to that of the gate line 70 formed thereafter. It may be formed to extend.

Although the data wiring is formed of a double layer, copper or copper alloy or aluminum (Al) or aluminum alloy (Al alloy), molybdenum (Mo) or molybdenum-tungsten (MoW) alloy, chromium (Cr), tantalum (Ta), It may also be formed from a single film made of a conductive material such as silver or a silver alloy. Here, considering that the pixel wirings 80, 82, and 84 formed thereafter are indium tin oxide (ITO), the lower layer 201 may be formed of a material having a low resistance of aluminum, aluminum alloy, or copper (Cu). Although the upper layer 202 is formed of chromium, which is a material having good contact properties with other materials, when the pixel wirings 80, 82, and 84 are indium zinc oxide (IZO), a single layer of aluminum or an aluminum alloy is formed. It is preferable to make it, and in consideration of the contact property with IZO and ITO, it is preferable to form it as a single film of copper or a copper alloy or silver or a silver alloy.

In the upper pixel of the lower insulating substrate 100, color filters 31, 32, and 33 of red (R), green (G), and blue (B), whose edges cover the data lines 20 and 21, are formed, respectively. have. Here, the color filters 31, 32, and 33 may be formed to overlap each other on the data lines 20 and 21, and it is preferable to use a material whose color characteristics do not change due to the manufacturing temperature of the thin film transistor of 350 ° C. or higher. .

Above the data lines 20, 21, 24 and color filters 31, 32, 33 are made of a material having a low dielectric constant of 3.0 or less, such as bisbenzocyclobutene (BCB) or perfluorocyclobutene (PFCB), and excellent heat resistance of 380 ° C or higher. An organic insulating film 40 is formed. In the organic insulating layer 40, contact holes 42 and 44 are formed to expose the data line 20 and the data pad 24, respectively.

A semiconductor pattern 52 made of a semiconductor such as hydrogenated amorphous silicon is formed on the organic insulating layer 40, and a gate insulating layer pattern 62 made of silicon oxide, silicon nitride, or the like is formed on the semiconductor pattern 52. Formed.

On the gate insulating layer pattern 62, aluminum (Al) or aluminum alloy (Al alloy), molybdenum (Mo) or molybdenum-tungsten (MoW) alloy, chromium (Cr), tantalum (Ta), copper (Cu) or copper alloy Gate wiring made of a metal such as (Cu alloy) or a conductor is formed. The gate line is connected to the scan signal line or the gate line 70 and the gate line 70 which extend in the horizontal direction and cross the data line 20 to define the unit pixel, and receive a scan signal from the outside to receive the gate line ( A gate pad 72 to be transferred to 70 and a gate electrode 71 of the thin film transistor that is part of the gate line 70. Here, the gate line 70 overlaps with the pixel electrode 80 to be described later to form a sustain capacitor which improves the charge retention ability of the pixel, and the sustain is generated by the overlap of the pixel electrode 80 and the gate line 70 to be described later. If the capacitance is not sufficient, a sustain electrode for the storage capacitor may be formed.

The gate wirings 70, 71, and 72 may be formed of a single film such as copper, aluminum, or an aluminum alloy having low resistance, like the data wirings 20, 21, and 24, but may be formed of a double layer or a triple layer. . In the case of forming more than two layers, it is preferable that one layer is made of a material having a low resistance and the other layer is made of a material having good contact properties with other materials.

Here, the gate wirings 70, 71, and 72 are formed in the same shape as the lower gate insulating film pattern 62.

In addition, the semiconductor pattern 52 not covered by the gate wirings 70, 71, and 72 has a source electrode 501 made of silicide having low resistance and doped with high concentration impurities on both sides of the gate electrode 71. A drain electrode 502 is formed, and a channel region 500 is formed in the lower semiconductor pattern 52 of the gate electrode 71. In this case, the source electrode 501 of the semiconductor pattern 52 is connected to the data line 20 through the contact hole 42 and the semiconductor pattern 52 except for the source and drain electrodes 501 and 502. The silver has the same shape as the gate insulating film pattern 62 and the gate wirings 70, 71, and 72.

A passivation layer 90 is formed on the substrate 100 to cover the gate wirings 70, 71, and 72, and to cover the source and drain electrodes 501 and 502. Here, the protective film 90 is made of a material having low dielectric constant and excellent heat resistance, such as bisbenzocyclobutene (BCB) or perfluorocyclobutene (PFCB), and is planarized. The protective film 90 is formed with a contact hole 92 exposing the drain electrode 502 and contact holes 96 and 94 exposing the gate pad 72 and the data pad 24, respectively.

The pixel electrode 80 connected to the drain electrode 112 is formed in the upper pixel of the passivation layer 90 through the contact hole 92. The pixel electrode 80 receives an image signal from the thin film transistor and generates an electric field together with the electrode of the upper plate. In the same layer as the pixel electrode 80, the auxiliary gate pad 82 and the auxiliary data pad 84, which are connected to the gate pad 72 and the data pad 24 through the contact holes 96 and 94, respectively, are formed. Formed. These are not essential to complement the adhesion between the pads 72 and 24 and external circuit devices and to protect the pads, and their application is optional. Here, the pixel electrode 80 also overlaps with the neighboring gate line 70 and the data line 20 to increase the aperture ratio, and may not overlap. The pixel wirings 80, 82, and 84 are made of a transparent conductive material such as ITO or IZO.

In the liquid crystal display according to the exemplary embodiment of the present invention, since the gate line 70 and the data line 20 replace the functions of the black matrix, the black matrix does not need to be formed on the upper substrate facing the lower substrate 100. . Therefore, it is not necessary to consider the alignment error of the upper substrate and the lower substrate 100 can improve the aperture ratio. In addition, an organic insulating film 40 and a protective film 90 having a low dielectric constant are formed between the data line 20 and the pixel electrode 80, so that the coupling capacitance generated between them can be minimized. It is possible to improve the properties and at the same time eliminate the need to space between them, ensuring the maximum aperture ratio.

In addition, the light blocking layer 21 and the gate electrode 71 are formed above and below the channel region 500 of the semiconductor pattern 52 to block light incident to the channel region 500, and to source and drain the thin film transistor. By using as the electrode (501, 502) made of silicide, the light leakage current was minimized, and the contact resistance was minimized.

In addition, the gate electrode 71 and the source and drain electrodes 501 and 502 are formed to be self-aligned to minimize parasitic capacitance of the thin film transistor, such as stitch or flicker. Pixel defects can be minimized.

Next, a method of manufacturing a substrate for a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 3A to 12B and FIGS. 1 and 2.

First, as shown in FIGS. 3A to 3B, a conductive material having a low resistance such as aluminum or an aluminum alloy or copper or a copper alloy or silver or a silver alloy and other materials such as chromium or molybdenum or titanium or chromium nitride or molybdenum nitride or the like In particular, a conductive material having excellent contact properties with ITO is deposited by a method such as sputtering, and then dry or wet etched by a photolithography process using a mask, and the lower layer 201 and the upper layer 202 on the lower insulating substrate 100. A data line including a data line 20, a data pad 24, and a light blocking film 21 formed of the same is formed.

As described above, considering that the pixel wirings 80, 82, and 84 formed thereafter are indium tin oxide (ITO), the lower layer of aluminum or aluminum alloy or copper (Cu) or copper alloy or silver or silver alloy ( 201) and a top film 202 of chromium or molybdenum or titanium or chromium nitride or molybdenum nitride, but when the pixel wirings 80, 82, and 84 are indium zinc oxide (IZO), a single film of aluminum or an aluminum alloy is formed. If the copper or copper alloy or silver or silver alloy has excellent contact properties with IZO and ITO, it may be formed as a single film of copper or copper alloy or silver to simplify the manufacturing process.

Subsequently, as shown in FIGS. 4A and 4B, photosensitive materials including pigments of red, green, and blue are sequentially applied and patterned by a photo process using a mask to sequentially turn red, green, and blue color filters 31, 32, and 33. Form. In this case, it is preferable to use a heat-resistant material that does not change color characteristics even at a temperature of 350 ° C. or higher, and the red, green, and blue color filters 31, 32, and 33 are formed using three masks, but the manufacturing cost It can also be formed by using one mask while moving to reduce the. In addition, using a laser transfer method or a print method can be formed without using a mask, thereby minimizing the manufacturing cost. At this time, as shown in the figure. The edges of the red, green, and blue color filters 31, 32, and 33 are preferably overlapped with the data lines 20, 21.

Subsequently, as shown in FIGS. 5A and 5B, the organic insulating layer 40 is formed using an organic material having a low dielectric constant of 3.0 or less on the lower insulating substrate 100 and excellent in heat resistance and planarization characteristics of 350 ° C. or higher. do. Such organic materials include BCB (bisbenzocyclobutene) or PFCB (perfluorocyclobutene) and the like, and materials having photosensitivity may be used. Subsequently, the organic insulating layer 40 is patterned by a photolithography process using a mask to form contact holes 42 and 44 exposing the data line 20 and the data pad 24, respectively. In this case, the contact holes 42 and 44 may be formed by dry etching.

Next, as shown in FIGS. 6A and 6B, the gate insulating film pattern 62 on the semiconductor pattern 52 and the semiconductor pattern 52 and the gate wirings 70, 71, and 72 on the gate insulating film pattern 62 are formed. In turn, it forms by the photo process using one mask. In this case, a part of the semiconductor pattern 52 is connected to the data line 20 through the contact hole 42. Here, in order to form the semiconductor pattern 52 and the gate insulating film pattern 62 and the gate wirings 70, 71, and 72 having a different shape from each other by a photolithography process using one mask, photoresist patterns having partially different thicknesses may be used. Should be used as an etch mask. This will be described in detail with reference to FIG. 7.

As shown in FIG. 7, the semiconductor layer 50, the gate insulating film 60, and the gate wiring conductive layer 75 are sequentially stacked, and a photosensitive film is formed on the gate wiring conductive layer 75 to a thickness of 1 μm to 2 μm. Apply.

Thereafter, light is irradiated onto the photoresist film through a photolithography process using a mask and then developed to form the photoresist patterns 312 and 314 as shown in FIG. 7. At this time, the first portion 312 of the photoresist patterns 112 and 114 corresponding to the gate wiring portion A is formed to have a thickness greater than that of the second portion 314 corresponding to the semiconductor pattern portions A and B. Remove all remaining photoresist. At this time, the ratio of the thickness of the first portion 312 and the thickness of the second portion 314 should be different depending on the process conditions in the etching process to be described later, the thickness of the second portion 314 first It is preferable to set it as 1/2 or less of the thickness of 312, for example, it is good that it is 4,000 Pa or less.

As such, there may be various ways of varying the thickness of the photoresist film according to the position. Here, two methods are presented for the case of using the positive photoresist film.

The first is to control the dose of light by forming a slit or lattice-shaped pattern or placing a translucent film in a pattern smaller than the resolution of the exposure machine, for example, the B region of the mask 1000.

When the light is irradiated to the photosensitive film through the mask 1000, the degree of decomposition of the polymers is different depending on the amount or intensity of light to be irradiated. At this time, when the polymers in the part corresponding to the C region completely exposed to light are completely decomposed, when the exposure is completed, the amount of light passing through the B region in which the slit or translucent film is formed is smaller than that of the part completely exposed to the light. In the portion corresponding to the region B, the photosensitive film is not completely decomposed. The longer exposure time decomposes all the molecules, so it should be avoided.

When the photoresist is developed, only the first portion 312 in which molecules are not decomposed as shown in FIG. 7 remains, and the second portion 314 irradiated with less light has only a portion thinner than the first portion 312. The photosensitive film is almost removed in the portion corresponding to the C region which is completely exposed to light.

The next method is to use reflow of the photoresist film. In other words, when exposed using a conventional mask that is divided into a part that can completely transmit light and a part that cannot fully transmit light, it is irradiated with light as in a normal case, and a part where polymers are decomposed and a part that is not This development results in a conventional photoresist pattern with no photoresist or a certain thickness. The photoresist pattern may be reflowed to flow to a portion where there is no remaining photoresist to form a thin film to form a new photoresist pattern.

Through this method, photoresist patterns having different thicknesses are formed according to positions.

First, the semiconductor pattern 52 is completed by etching the gate wiring conductive layer 75, the lower gate insulating layer 60, and the semiconductor layer 50 using the photoresist patterns 312 and 314 as an etching mask. In this case, all of the three layer films 75, 60, and 50 may be patterned by dry etching, the conductive layer 75 for gate wiring may be patterned by wet etching, and the gate insulating layer 60 and the semiconductor layer 50 may be dry etching. It can also be patterned. Here, the photoresist pattern 314 is not completely removed. Subsequently, the second portion 314 is completely removed, and an ashing process using oxygen may be added to completely remove the photoresist residue of the second portion 314.

In this way, the photoresist pattern 312 remains.

Next, the gate wiring conductive layer 75 and the lower gate insulating film 60 are etched using the photoresist pattern 312 as an etching mask, and as shown in FIG. 9, the gate insulating film is formed on the semiconductor pattern 52. The pattern 62 and the gate wirings 70, 71, and 72 are completed. The patterning of the gate insulating film 60 is preferably performed by dry etching. In this case, the etching selectivity of the gate insulating film 60 and the semiconductor pattern 52 is preferably 10 or more.

Finally, the first portion 314 of the photoresist pattern is removed.

Here, the gate wirings 70, 71, and 72 are made of a low conductive material such as chromium or molybdenum or titanium or chromium nitride or molybdenum nitride, such as an electrically conductive material having excellent contact properties with ITO and an aluminum or aluminum alloy or a copper or copper alloy. The conductive material having a resistance may be formed as a multilayer, but when the pixel wirings 80, 82, and 84 formed thereafter are indium zinc oxide (IZO), they may be formed as a single layer of aluminum or an aluminum alloy. , Copper or a copper alloy or silver or a silver alloy may be formed of a single film of copper when the contact characteristics with IZO and ITO are excellent.

Next, as shown in FIG. 10, a high concentration impurity containing phosphorus is implanted into the semiconductor pattern 52 by a method such as ion shower, plasma doping, or ion implantation to form the channel region 500 in the semiconductor pattern 52. ) And a source region 501 and a drain region 502 located at both sides of the channel region 500. In this case, the portion to be connected to the data line 20 becomes the source region 501.

Subsequently, as shown in FIGS. 11A and 11B, a metal material capable of silicide formation, such as nickel, chromium, or molybdenum, is deposited at a thickness of about 200 to 500 kPa, annealed at about 250 ° C. for 1 hour, and the metal material is entirely covered. The source electrode 501 and the drain electrode of the source region 501 and the drain region 502 of the semiconductor pattern 52 which are not etched and covered by the gate wirings 70, 71, and 72 are made of silicide having low resistance. 502).

12A and 12B, a protective film 90 is formed using an organic material having a low dielectric constant and excellent in heat resistance and planarization characteristics, and is patterned by a photolithography process using a mask to form a drain electrode 502. Contact holes 92 are formed, and contact holes 96 and 94 are exposed to expose the gate pad 72 and the data pad 24, respectively. The passivation layer 90 may be formed of BCB, PFCB, or a photosensitive material.

1 and 2, a pixel connected to the drain electrode 502 through the contact hole 92 by laminating and patterning a transparent conductive material IZO or ITO on the lower insulating substrate 100. The electrode 80 is formed. At this time, the auxiliary gate pad 82 and the auxiliary data pad 84 which are respectively connected to the gate pad 72 and the data pad 24 through the contact holes 96 and 94 are also formed.

In the manufacturing method of the liquid crystal display according to the exemplary embodiment of the present invention, the color filters 31, 32, and 33, which are low cost processes, are formed before the thin film transistors, so that the occurrence of defects in the color filter process does not affect the final yield. Therefore, manufacturing cost can be minimized. In addition, the manufacturing process of the color filter and the manufacturing process of the thin film transistor can be performed in a separate manufacturing line to maximize the manufacturing efficiency. That is, after ordering or completing a substrate having a color filter coated with the organic insulating layer 40, the thin film transistor array substrate manufacturing process using three or less masks may be performed in a separate process.

In addition, the gate line 70 and the data line 20 are formed of a low resistance conductive material such as copper or a copper alloy or aluminum or an aluminum alloy, so that the gate line 70 and the data line 20 can be easily applied to a method for manufacturing a liquid crystal display device having a high definition large screen.

In addition, the gate wirings 70, 71, and 72 are formed on the planarized organic insulating layer 40 to minimize the possibility of disconnection of the wirings. In addition, the data lines 20, 21, and 24 are also formed on the substrate 100 and covered with a relatively thick and excellent insulating layer 40, thereby minimizing the possibility of disconnection or erosion of the data lines. In addition, a relatively thick organic insulating film 40 and a passivation film 90 are formed between the data line 20, the gate line 70, and the pixel electrode 80, and the short circuits of these 20, 70, and 80 are formed. Can be prevented.

In addition, the thickness of the upper insulating substrate can be minimized by forming only a common electrode facing the pixel electrode 80 to form an electric field on the upper insulating substrate, and there is no material limitation, thereby reducing manufacturing costs and openings in the common electrode. The liquid crystal display may also be easily applied to a patterned vertical alignment (PVA) type liquid crystal display device.

In addition, in the liquid crystal display and the manufacturing method thereof according to the embodiment of the present invention, by using only five masks in total, the manufacturing process may be simplified and the manufacturing cost may be minimized.

In addition, the manufacturing method of the thin film transistor substrate for a liquid crystal display device can be applied to the manufacturing method of the liquid crystal display device in which the common electrode and pixel electrode which face in parallel mutually are formed in the same board | substrate.

In the manufacturing method according to the exemplary embodiment of the present invention, the organic insulating layer 40 may be formed and then completed using three masks. The data line 20 and the pixel electrode 80 may be formed of a silicide source and drain. Is directly connected to the reference electrodes 801 and 802.

As described above, in the thin film transistor substrate for the liquid crystal display device and the manufacturing method thereof according to the embodiment of the present invention, by forming the color filter before the thin film transistor, the aperture ratio can be secured and the process yield can be improved. In addition, the manufacturing process of the color filter and the thin film transistor array may be performed in separate manufacturing lines, thereby maximizing manufacturing efficiency. By using the wiring as a black matrix and forming a semiconductor pattern and a gate wiring together, manufacturing costs can be minimized. In addition, the data wiring, the pixel electrode, and the gate wiring are sufficiently insulated to minimize parasitic capacitance and short circuit occurring therebetween, and a light blocking film and a gate electrode are formed on the upper and lower portions of the thin film transistor to minimize the light leakage current. The gate electrode, the source electrode, and the drain electrode are formed by self matching, so that the parasitic capacitance of the thin film transistor can be minimized, so that the image quality can be improved by ensuring the image quality uniformity even in a large area.

Claims (22)

Forming a data line including a data line on the insulating substrate; Forming red, green, and blue color filters on the substrate to cover the edges of the data lines; Forming an insulating film having a first contact hole exposing the data line and covering the data line and the color filter; A photolithography process using a mask is formed on the insulating layer to form a semiconductor pattern connected to the data line through the first contact hole, a gate insulating layer pattern is formed on the semiconductor pattern, and a gate is formed on the gate insulating layer pattern. Forming a gate wiring comprising a line and a gate electrode, Forming a passivation layer having a second contact hole exposing the semiconductor pattern and covering the gate wiring and the semiconductor pattern; and Forming a pixel wiring on the passivation layer, the pixel wiring including a pixel electrode connected to the semiconductor pattern through the second contact hole; Method of manufacturing a thin film transistor substrate for a liquid crystal display device comprising a. delete In claim 1, The gate wiring, the semiconductor pattern and the gate insulating film pattern forming step, Sequentially depositing the semiconductor layer, the gate insulating layer, and the gate conductive layer on the insulating layer; Applying a photoresist film on the gate conductive layer, Exposing the photosensitive film through the mask; The photosensitive film is developed to remove a first portion corresponding to the gate wiring, a second portion corresponding to the semiconductor pattern having a thickness thinner than the first portion, and not covered by the gate wiring, and the photosensitive film is removed. And forming a photoresist pattern including a third portion positioned at a portion other than the second portion, Etching the gate conductive layer under the third portion, the gate insulating layer below the semiconductor layer, and the semiconductor layer under the third portion to complete the semiconductor pattern; Removing the photoresist pattern of the second portion; Etching the gate conductive layer and the gate insulating layer below the substrate by using the photoresist pattern of the first portion as a mask to complete the gate wiring and the gate insulating layer pattern; Removing the remaining photoresist pattern Method of manufacturing a thin film transistor substrate for a liquid crystal display device comprising a. In claim 3, The gate wiring and the gate insulating film pattern is formed in the same shape manufacturing method for a thin film transistor substrate for a liquid crystal display device. In claim 4, The mask used in the photolithography process includes a first portion through which light cannot be transmitted completely, a second portion through which light can be partially transmitted, and a third portion through which light can be completely transmitted, and the photoresist pattern is a positive photoresist film. The first, second, and third portions of the mask may be aligned to correspond to the first, second, and third portions of the photoresist pattern during the exposure process. In claim 5, And a second portion of the mask comprises a translucent film or a pattern smaller in size than a resolution of a light source used in the exposing step. In claim 5, And a second portion of the photoresist pattern is formed through reflow. In claim 1, After the gate wiring forming step, And forming a source region and a drain region in the semiconductor pattern on both sides of the gate electrode by ion implanting a high concentration of impurities into the semiconductor pattern using the gate wiring as a mask. Manufacturing method. In claim 8, After forming the source region and the drain region, Depositing a metal material capable of forming silicide on the substrate; Performing an annealing process to change the source and drain regions into source and drain electrodes made of silicide; and The method of claim 1, further comprising removing the metal material. In claim 1, The gate line further includes a gate pad connected to the gate line to receive a signal from the outside, and the data line further includes a data pad connected to the data line to receive a signal from the outside, The passivation layer and the insulating layer have third and fourth contact holes exposing the gate pad and the data pad, Forming an auxiliary gate pad and an auxiliary data pad on the same layer as the pixel electrode and connected to the gate pad and the data pad through the third and fourth contact holes. Manufacturing method. In claim 1, In the data line forming step, a thin film transistor substrate for a liquid crystal display device further comprising forming a light blocking layer on a portion corresponding to the semiconductor layer pattern or the gate wiring by branching of the data line or independent wiring separated from the data line. Way. In claim 1, And said insulating film is formed of an organic insulating film. A data line including a data line extending in one direction on the insulating substrate; Red, green, and blue color filters formed on the pixels on the substrate to cover the edges of the data lines; An insulating film covering the data line and the color filter and having a first contact hole exposing the data line; A semiconductor pattern formed on the insulating layer and connected to the data line through the first contact hole; A gate insulating layer pattern formed on the semiconductor pattern; A gate line formed on the gate insulating layer pattern and including a gate line crossing the data line to define the pixel and a gate electrode connected to the gate line and overlapping the semiconductor pattern; A protective film covering the gate wiring and the semiconductor pattern not covered by the gate wiring, and having a second contact hole exposing the semiconductor pattern; A pixel wiring formed on the pixel on the passivation layer and including a pixel electrode connected to the semiconductor pattern through the second contact hole; Thin film transistor substrate for a liquid crystal display device comprising a. delete In claim 13, The insulating film is a thin film transistor substrate for a liquid crystal display device made of an organic insulating material. In claim 13, The semiconductor pattern may include a source region and a drain electrode disposed at both sides of the channel region below the gate electrode and the channel region, each of which is doped with high-concentration impurities or made of silicide and connected to the data line and the pixel electrode, respectively. Thin-film transistor substrate for liquid crystal display devices containing. The method of claim 16, And the source and drain electrodes are formed on the semiconductor layer not covered by the gate electrode. The method of claim 17, The thin film transistor substrate for a liquid crystal display device of which the gate wiring and the gate insulating film pattern are formed in the same shape. The method of claim 18, The semiconductor pattern except for the source and drain electrodes is formed in the same shape as the gate wiring. In claim 13, The gate line further includes a gate pad connected to the gate line to receive a signal from the outside, and the data line further includes a data pad connected to the data line to receive a signal from the outside, The passivation layer and the insulating layer have third and fourth contact holes exposing the gate pad and the data pad, And an auxiliary gate pad and an auxiliary data pad connected to the gate pad and the data pad through the third and fourth contact holes and formed in the same layer as the pixel electrode. In claim 13, And the data line further comprises a light blocking layer which is separated from the data line or the branch of the data line and positioned in a portion corresponding to the semiconductor layer pattern or the gate line. In claim 13, The data wiring and the gate wiring include a single film of aluminum or aluminum alloy or copper or copper alloy or silver or silver alloy, or a conductive film made of chromium or molybdenum or molybdenum alloy or chromium nitride or molybdenum with excellent contact properties with ITO. A thin film transistor substrate for liquid crystal display devices formed of a multilayer film.

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