KR20050009039A - Thin film transistor array panel, manufacturing method thereof, and liquid crystal display including the same - Google Patents

Abstract

PURPOSE: A thin film transistor display panel, a method for manufacturing the same, and a liquid crystal display device including the same are provided to prevent light leakage and improve a contrast ratio by removing matrices for light blocking, and improve an aperture ratio. CONSTITUTION: A plurality of gate lines are formed on an insulation substrate(110). A gate insulating layer(140) is formed on the gate lines. A semiconductive layer(151) is formed on the gate insulating layer. A plurality of data lines(171) and drain electrodes(175) are formed on the semiconductive layer. A passivation layer(180) is formed on the data lines and drain electrodes. Color filters(230R,230G,230B) are formed on the passivation layer. Pixel electrodes(190) are formed on the color filters and are electrically connected with the drain electrodes. A channel light blocking layer is formed on a channel part(154) of the semiconductive layer, wherein red, green, and blue filters are laminated on the channel blocking layer. An edge light blocking layer is formed at a peripheral part of a pixel area where the pixel electrodes are formed, wherein other red, green, and blue filters are laminated on the edge light blocking layer.

Description

A thin film transistor array panel, a method of manufacturing the same, and a liquid crystal display including the same {THIN FILM TRANSISTOR ARRAY PANEL, MANUFACTURING METHOD THEREOF, AND LIQUID CRYSTAL DISPLAY INCLUDING THE SAME}

The present invention relates to a thin film transistor array panel, a method of manufacturing the same, and a liquid crystal display including the same.

The liquid crystal display is one of the most widely used flat panel display devices. The liquid crystal display includes two display panels on which a field generating electrode is formed and a liquid crystal layer interposed therebetween. It is a display device which controls the transmittance | permeability of the light which passes through a liquid crystal layer by rearranging.

Among the liquid crystal display devices, a liquid crystal display device including a thin film transistor for forming an electrode on each of two display panels and switching a voltage applied to the electrode is used. One of the two display panels includes a pixel electrode and a thin film transistor for switching a voltage applied thereto, and a gate line and a data line for transmitting a signal to the thin film transistor (hereinafter referred to as a thin film transistor display panel), and the other display panel includes a pixel electrode. It is common to provide a common electrode facing and a color filter of red (R), green (G), and blue (B).

In order to improve the brightness of such a liquid crystal display device, securing a high aperture ratio is an important problem. To this end, the color filter is placed on the same substrate as the thin film transistor to minimize the process margin between the two substrates and at the same time, to increase the aperture ratio by superimposing the pixel electrode with the signal line (hereinafter referred to as a color filter on array structure). This has been presented.

In this case, a black matrix for blocking light for blocking light flowing into a portion where the thin film transistor is located is formed on the upper substrate above the thin film transistor. The light blocking black matrix formed on the upper substrate is formed in correspondence with the portion where the thin film transistors of the thin film transistor array panel are located, and when the two substrates are assembled, some of the light is not blocked by the misalignment. In order to prevent a defect and to block the light which flows obliquely, it is formed with a larger area than the channel part of a thin film transistor. However, since there are steps at both ends of the light blocking black matrix, light leakage occurs due to irregular alignment of the liquid crystals located therein.

In addition, there is a problem that the aperture ratio is reduced by the light blocking black matrix formed in a larger area than the channel portion of the thin film transistor.

SUMMARY OF THE INVENTION The present invention provides a thin film transistor array panel in which light leakage defects are removed and an aperture ratio is increased, a method of manufacturing the same, and a liquid crystal display including the same.

1 is a layout view of a thin film transistor array panel according to an exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along the line II-II 'of FIG. 1,

3A, 4A, 5A, and 6A are layout views at an intermediate stage in the method of manufacturing the thin film transistor array panel according to the exemplary embodiment shown in FIGS. 1 and 2, and FIG. 3B is a IIIb-IIIb ′ line of FIG. 3A. 4B is a sectional view at the next step of FIG. 3B, FIG. 5B is a sectional view at the next step of FIG. 4B, FIG. 6B is a sectional view at the next step of FIG. 5B,

FIG. 7 is a layout view of a thin film transistor array panel in which a color filter is formed in a pixel region on a passivation layer and a channel light blocking layer is formed on a channel portion of a semiconductor layer of a thin film transistor. All of them are

8 is a cross-sectional view taken along the lines VIIIa-VIIIa ', VIIIb-VIIIb', and VIIIc-VIIIc 'of FIG. 7, respectively.

9 is a cross-sectional view at the next step of FIG. 8,

10 is a sectional view at the next step of FIG. 9,

11 is a layout view of a thin film transistor array panel according to another exemplary embodiment of the present invention.

12 is a cross-sectional view taken along the line XII-XII ′ of FIG. 11,

13A and 16A are layout views at an intermediate stage in a method of manufacturing a thin film transistor array panel according to another exemplary embodiment of the present invention, and FIG. 13B is a cross-sectional view taken along the line XIIIb-XIIIb ′ of FIG. 13A, and FIG. 13A is a cross sectional view at the next step of FIG. 15, FIG. 15 is a sectional view at the next step of FIG. 14, FIG. 16B is a sectional view at a next step of FIG. 15,

17 is a layout view of a thin film transistor array panel according to another exemplary embodiment of the present invention.

18 is a cross-sectional view of a liquid crystal display according to an exemplary embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

110: substrate 121, 129: gate line

124: gate electrode 140; Gate insulating film

151 and 154 semiconductor 161 and 165 resistive contact members

171, 179: data line 173: source electrode

175: drain electrode 180: protective film

181, 182, 185: contact hole 190: pixel electrode

81, 82: contact auxiliary member

A thin film transistor array panel according to the present invention includes an insulating substrate, a gate line formed on the insulating substrate, a gate insulating film formed on the gate line, a semiconductor layer formed on the gate insulating film, and a data line formed on the semiconductor layer. And a drain electrode, a passivation layer formed on the data line and the drain electrode, a color filter formed on the passivation layer, and a pixel electrode formed on the color filter and electrically connected to the drain electrode. A channel light blocking layer in which a red filter, a green filter, and a blue filter are stacked is formed on the channel portion of the layer, and the edge light difference in which a red filter, a green filter, and a blue filter are stacked at the periphery of the pixel region where the pixel electrode is formed. It is preferable that a single layer is formed.

In addition, the channel light blocking layer is preferably formed to be smaller than or equal to the area of the channel portion of the semiconductor layer.

In addition, it is preferable that each of the red filter, the blue filter, and the blue filter stacked on the channel portion of the semiconductor layer is thinner than the color filter formed in most of the pixel region.

In addition, the method of manufacturing a thin film transistor array panel according to the present invention may include forming a gate line, a data line, and a thin film transistor on an insulating substrate, forming a passivation layer, and forming a color filter in a pixel area on the passivation layer. A channel light blocking layer in which a red filter, a green filter, and a blue filter are stacked is formed on the channel portion of the semiconductor layer of the transistor, and a red filter, a green filter, and a blue filter are stacked on the periphery of the pixel region where the pixel electrode is formed. The method may further include forming an edge light blocking layer, and forming a pixel electrode electrically connected to the thin film transistor on the color filter and the channel light blocking layer.

The forming of the channel light blocking layer may include forming a red filter in the red pixel area on the passivation layer, and forming a red filter having a channel shape on the channel part of the thin film transistor in the green pixel area and the blue pixel area, respectively. And forming a green filter in a green pixel area on the passivation layer, and forming a channel-shaped green filter on the channel part of the thin film transistor in the red pixel area and the blue pixel area, respectively, in the blue pixel area on the passivation layer. And forming a filter and forming a channel-shaped blue filter on the channel portion of the thin film transistor in the red pixel region and the green pixel region, respectively.

In addition, each of the red filter, the green filter, and the blue filter of the channel light blocking layer and the edge light blocking layer may be thinner than the red filter, the green filter, and the blue filter formed in the pixel area.

In addition, each of the red filter, the green filter, and the blue filter of the channel light blocking layer and the edge light blocking layer may be formed using a slit photomask.

In addition, the liquid crystal display according to the present invention is formed on a first substrate, a gate line formed on the first substrate, a gate insulating film formed on the gate line, a semiconductor layer formed on the gate insulating film, and formed on the semiconductor layer. A data line and a drain electrode, a passivation layer formed on the data line and the drain electrode, a color filter formed on the passivation layer, and a pixel electrode formed on the color filter and electrically connected to the drain electrode. The channel light blocking layer in which the red filter, the green filter, and the blue filter are stacked is formed on the channel portion of the semiconductor layer, and the red filter, the green filter, and the blue filter are stacked at the periphery of the pixel region where the pixel electrode is formed. A thin film transistor array panel on which an edge light blocking layer is formed; An upper display panel including a second substrate positioned above the first substrate and spaced apart from the first substrate, and a common electrode formed on the second substrate; It is preferable to include a liquid crystal layer formed between the thin film transistor array panel and the upper display panel.

Then, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

Hereinafter, a thin film transistor array panel and a method of manufacturing the same according to an embodiment of the present invention will be described in more detail with reference to the accompanying drawings.

1 is a layout view of a thin film transistor array panel according to an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along the line II-II ′ of FIG. 1.

First, the structure of a thin film transistor array panel for a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.

In the thin film transistor array panel according to the exemplary embodiment of the present invention, the gate line 121 extending in one direction is formed on the transparent insulating substrate 110. A portion of the gate line 121 or a branched portion is used as the gate electrode 124 of the thin film transistor.

In order to increase the storage capacitance of the pixel, a portion of the gate line 121 is extended to a wide width, which overlaps with the storage capacitor conductor 177 connected to the pixel electrode 190 to be described later. To form. If the storage capacity is not sufficient, a separate storage electrode line may be added.

A gate insulating layer 140 formed of silicon nitride, silicon oxide, or the like is formed on the substrate 110 to cover them 121 and 124.

A semiconductor layer 151 made of amorphous silicon without doping impurities is formed in a predetermined region of the gate insulating layer 140. The semiconductor layer 151 extends along the data line 171 under the data line 171 to be described later, and is linearly formed under the drain electrode 175 to be described later.

In addition, ohmic contacts 161 and 165 including amorphous silicon or silicide doped with impurities are formed on the semiconductor layer 151. The ohmic contacts 161 and 165 are islands facing the portion of the linear portion 161 around the linear portion 161 and the gate electrode 124 extending along the data line 171 together with the semiconductor layer 151. It consists of a mold 165. The island portion 165 is formed at a predetermined distance away from the linear portion 161, and they have the same planar pattern as the semiconductor layer 151 except for a predetermined region of the semiconductor layer 151. The predetermined region of the semiconductor layer 151 is a channel portion 154 that forms a channel of the thin film transistor.

A data line 171 is formed on the gate insulating layer 140 and the linear portion ohmic contact layer 161 to cross the gate line 121 to define a pixel area. The data line 171 is branched and has a source electrode 173 overlapping the semiconductor layer 151. One end 179 of the data line is formed wider than the width of the data line 171 to receive a signal transmitted from a data driving circuit (not shown).

The drain electrode 175 facing the source electrode 173 at a predetermined distance from the island-type ohmic contact layer 165 facing the gate electrode 124 and partially overlapping the gate electrode 124 and the semiconductor layer 151. Is formed.

In the same layer as the data line 177, a conductor pattern 177 is formed to overlap the protrusion of the gate line 121 to form a storage capacitor.

A passivation layer 180 made of an insulating material such as silicon oxide or silicon nitride is formed on the semiconductor layer 151 that is not covered by the data lines 171 and 173 and the drain electrode 175. The passivation layer 180 protects the exposed semiconductor layer 151 and prevents the pigment from diffusing from the color filters 230R, 230G, and 230B described below to the layer in contact with the color filters 230R, 230G, and 230B. . In this case, the passivation layer 180 is not essential when forming the color filters 230R, 230G, and 230B, and is selected as necessary.

The red filter 230R, the green filter 230G, and the blue filter 230B are formed in the direction parallel to the data line 171 along the pixel column formed on the gate insulating layer 140 and partitioned by the data line 171. Stretched. The red filter 230R, the green filter 230G, and the blue filter 230B are alternately formed in the pixel column.

Here, the red filter 230R, the green filter 230G, and the blue filter 230B are not formed at the ends of the gate line 121 or the data line 171 which are connected to the external circuit.

The color filters 230R, 230G, and 230B are located above the data line 171, but do not completely cover the data line.

As shown in FIGS. 1 and 2, a red filter 230R is formed in most of the red pixel region R, and a channel light blocking layer is formed on the channel portion 154 of the semiconductor layer of the red pixel region R. 55) is formed. The channel light blocking layer 55 is formed by stacking a red filter 230R, a green filter 230G, and a blue filter 230B.

Conventionally, a black matrix for blocking light for blocking light flowing into a portion where a thin film transistor is located is formed on an upper substrate above the thin film transistor. However, in this case, since there are steps at both ends of the light blocking black matrix, light leakage occurs due to irregular alignment of the liquid crystals located therein. In order to prevent this, in one embodiment of the present invention, the channel light blocking layer 55 is formed on the channel portion 154 of the semiconductor layer of the thin film transistor array panel so that both ends of the light blocking black matrix formed on the upper substrate are formed. Prevents light leakage due to steps. Steps exist at both ends of the light blocking layer, but the light leakage is insignificant as compared with the light leakage caused by the step between the light blocking black matrix of the upper substrate and the thin film transistor of the lower substrate.

Each of the red filter 230R, the green filter 230G, and the blue filter 230B constituting the channel light blocking layer 55 is preferably thinner than the color filter formed in most of the pixel region. This is because if the thickness of each color filter constituting the channel light blocking layer 55 is the same as the thickness of each color filter formed in most of the pixel areas, the thickness of the channel light blocking layer 55 is thicker than the cell gap of the liquid crystal display device. This is because it is difficult to control the cell gap.

The channel light blocking layer 55 may be formed to be smaller than or equal to the area of the channel portion 154 of the semiconductor layer.

Conventionally, when assembling the upper and lower substrates, the light blocking black matrix is formed to have a larger area than the channel portion 154 of the thin film transistor in order to prevent defects in which some light is not blocked due to a misalignment. Decreased. However, in one embodiment of the present invention, since the channel light blocking layer 55 is formed to be smaller than or equal to the area of the channel portion 154 of the semiconductor layer, the aperture ratio is increased.

18, the edge light blocking layer 58 having the red filter 230R, the green filter 230G, and the blue filter 230B stacked on the periphery of the pixel region where the pixel electrode to be described later is formed. Is formed.

The pixel electrode 190 is formed on the color filters 230R, 230G, and 230B. The pixel electrode 190 is physically and electrically connected to the drain electrode 175 through the contact hole 185 formed over the color filters 230R, 230G, and 230B and the passivation layer 180 to receive an image signal. In addition, the pixel electrode 190 is also connected to the conductor pattern 177 through the contact hole 183 formed over the color filters 230R, 230G, and 230B and the passivation layer 180 to form a storage capacitor.

A contact auxiliary member 82 is formed on the color filters 230R, 230G, and 230B through one end 179 of the data line and the contact hole 182.

The contact assisting member 82 is connected to one end 179 of the data line through the contact hole 182. The contact assisting member 82 is not essential to serve as a supplement to adhesion to the external circuit device and to protect the ends thereof, and their application is optional.

Next, the method of manufacturing the thin film transistor array panel for the liquid crystal display described above will be described in detail with reference to FIGS. 3A to 8B and FIGS. 1 and 2.

3A, 4A, 5A, and 6A are layout views at an intermediate stage in the method of manufacturing the thin film transistor array panel according to the exemplary embodiment shown in FIGS. 1 and 2, and FIG. 3B is a IIIb-IIIb ′ line of FIG. 3A. 4B is a cross-sectional view at the next step of FIG. 3B, FIG. 5B is a cross-sectional view at the next step of FIG. 4B, and FIG. 6B is a cross-sectional view at the next step of FIG. 5B.

First, as shown in FIGS. 3A and 3B, a metal such as chromium, molybdenum, aluminum, silver, or an alloy thereof is deposited on the transparent insulating substrate 110 by a sputtering method to form a single layer or a plurality of gate metal layers. do. Thereafter, the metal layer is dry or wet etched by a photolithography process using a mask to form gate lines 121 and 124 on the substrate 110. At this time, the sidewalls of the 121 and 124 are formed to be tapered, and the tapered shape allows the layers formed on them to be in close contact with each other.

Next, as shown in FIGS. 4A and 4B, the gate insulating film 140 made of silicon nitride or silicon oxide, the semiconductor such as hydrogenated amorphous silicon, and the amorphous silicon doped at high concentration with n-type impurities such as phosphorus (P) are used. Continuous deposition using chemical vapor deposition and patterning by a photolithography process using a mask, patterning an amorphous silicon layer doped with impurities and an amorphous silicon layer not doped with impurities in order to form ohmic contact with the semiconductor layer 151 thereon. Form layer 164.

Subsequently, as shown in FIGS. 5A and 5B, a conductive layer such as a metal is deposited by a method such as sputtering, and then patterned by a photolithography process using a mask to form a data line 171 and a drain electrode having the source electrode 173. 175 and the conductor pattern 177 are formed.

Next, the ohmic contact layer which is not covered by the source electrode 173 and the drain electrode 175 is etched to expose the semiconductor layer 154 between the source electrode 173 and the drain electrode 175, and the ohmic contact layer 164 is formed. Separate into parts 161 and 165.

Next, as shown in FIGS. 6A to 6B, the protective film 180 is formed by stacking silicon nitride or silicon oxide. Thereafter, a photosensitive organic material including red, green, and blue pigments is sequentially applied on the passivation layer 180, and a red filter 230R, a green filter 230G, and a blue filter 230B are sequentially formed in the pixel region through a photographic process. At the same time, the channel light blocking layer 55 is formed on the channel portion 154 of the semiconductor layer of the thin film transistor, and the red filter 230R, the green filter 230G, and the blue filter are formed at the periphery of the pixel region where the pixel electrode is formed. An edge light blocking layer 58 in which 230B is stacked is formed.

Openings 231 and 232 corresponding to the conductor pattern 177 and the drain electrode 175, respectively, when the red filter 230R, the green filter 230G, and the blue filter 230B are formed by a photo process using a mask. To form.

Thereafter, the passivation layer 180 is etched using a photolithography process using a mask, and the contact holes 183 and 185 exposing the openings 231 and 232 and the contact hole 182 exposing one end of the data line 171 are exposed. ).

Hereinafter, a method of forming the channel light blocking layer 55 will be described in detail.

FIG. 7 is a layout view of a thin film transistor array panel in which a color filter is formed in a pixel area on the passivation layer 180 and a channel light blocking layer 55 is formed on a channel portion 154 of a semiconductor layer of a thin film transistor. (R), the green pixel region G, and the blue pixel region B are all displayed, and FIG. 8 is taken along the lines VIIIa-VIIIa ', VIIIb-VIIIb', and VIIIc-VIIIc 'of FIG. 7, respectively. 9 is a cross-sectional view of the next step of FIG. 8, and FIG. 10 is a cross-sectional view of the next step of FIG. 9.

As shown in FIG. 7, a color filter is formed in the pixel region on the passivation layer 180, and the red filter 230R, the green filter 230G, and the blue filter (on the channel portion 154 of the semiconductor layer of the thin film transistor) A channel light blocking layer 55 in which 230B) is stacked is formed.

As shown in FIG. 8, to form the channel light blocking layer 55, first, a red filter 230R is formed in the red pixel region R on the passivation layer 180, and the green pixel region G and the blue color are formed. The red filter 230R having the shape of the channel portion 154 is formed on the channel portion 154 of the thin film transistor in the pixel region B, respectively. The red filter 230R in the shape of the channel portion 154 formed on the channel portion 154 of the thin film transistors of the green pixel region G and the blue pixel region B, respectively, is better than the red filter 230R formed in the pixel region. Form a thin thickness.

To this end, a red filter 230R having a channel portion 154 formed on the channel portion 154 of the thin film transistors of the green pixel region G and the blue pixel region B is formed using a slit photomask.

As shown in FIG. 9, a green filter 230G is formed in the green pixel region G on the passivation layer 180, and the channels of the thin film transistors of the red pixel region R and the blue pixel region B are formed. The green filter 230G in the shape of the channel portion 154 is formed on the portion 154.

The green filter 230G in the shape of the channel portion 154 formed on the channel portion 154 of the thin film transistors of the red pixel region R and the blue pixel region B, respectively, is smaller than the green filter 230G formed in the pixel region. Form a thin thickness.

To this end, the green filter 230G in the shape of the channel portion 154 formed on the channel portion 154 of the thin film transistors of the red pixel region R and the blue pixel region B is formed using a slit photomask.

10, the blue filter 230B is formed in the blue pixel area B on the passivation layer 180, and the channel of the thin film transistors of the red pixel area R and the green pixel area G is formed. The blue light filter 230B having a channel portion 154 shape is formed on the portion 154 to complete the channel light blocking layer 55.

The blue filter 230B in the shape of the channel portion 154 formed on the channel portion 154 of the thin film transistors of the red pixel region R and the green pixel region G, respectively, is smaller than the blue filter 230B formed in the pixel region. Form a thin thickness.

To this end, the blue filter 230B in the shape of the channel portion 154 formed on the channel portion 154 of the thin film transistors of the red pixel region R and the green pixel region G is formed using a slit photomask.

In an embodiment of the present invention, the channel light blocking layer 55 is formed by forming the red filter, the green filter 230G, and the blue filter 230B in the order of forming the channel light blocking layer 55. It is also possible.

The edge light blocking layer in which the red filter 230R, the green filter 230G, and the blue filter 230B are stacked on the periphery of the pixel region where the pixel electrode is formed in the same order as the channel light blocking layer 55 is formed. 58).

1 and 2, a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO), is deposited on the substrate 110 and etched by a photolithography process using a mask. The pixel electrode 190 connected to the conductor pattern 177 and the drain electrode 175 through the first and second contacts 83 and 185, and the contact auxiliary member 82 connected to one end portion 179 of the data line through the contact hole 182. ).

On the other hand, the thin film transistor array panel can be completed through a manufacturing method according to another embodiment. In this case, the thin film transistor array panel has a structure different from the above embodiment, which will be described in detail with reference to the accompanying drawings.

FIG. 11 is a layout view of a thin film transistor array panel according to another exemplary embodiment. FIG. 12 is a cross-sectional view taken along the line XII-XII ′ of FIG. 11.

13A and 16A are layout views at an intermediate stage in the method of manufacturing the TFT panel according to the exemplary embodiment of the present invention, and FIG. 13B is a cross-sectional view taken along the line XIIIb-XIIIb 'of FIG. 13A, and FIG. It is sectional drawing in the next step of FIG. 13A, FIG. 15 is sectional drawing in the next step of FIG. 14, and FIG. 16B is sectional drawing in the next step of FIG.

First, the structure of the completed thin film transistor array panel will be described in detail with reference to FIGS. 11 and 12. In the thin film transistor array panel according to the exemplary embodiment illustrated in FIGS. 11 and 12, most single layer structures are the same as those of FIGS. That is, the gate line 121 is formed on the insulating substrate 110, the gate insulating layer 140 is formed to cover the gate line 121, and the semiconductor layer 151 and the ohmic contact layer are formed on the gate insulating layer 140. 161 and 165 are formed, and the data line 175 and the drain electrode 175 are formed on the ohmic contact layers 161 and 165, and the passivation layer 180 is formed to cover the 171 and 175. The pixel electrode 190 connected to the drain electrode 175 is formed on the passivation layer 180. Of course, the channel light blocking layer 55 is formed in the same structure as the embodiment shown in FIGS. 1 and 2.

However, the data line 171 and the drain electrode 175 have the same planar pattern as the ohmic contacts 161 and 165, and the semiconductor layer 151 has a channel portion between the source electrode 173 and the drain electrode 175. It has the same planar pattern as the ohmic contacts 161 and 165 except that 154 is connected.

Next, a method of manufacturing a thin film transistor array panel according to another exemplary embodiment illustrated in FIGS. 11 and 12 will be described in detail with reference to the accompanying drawings of FIGS. 3A, 3B, and 13A to 16B.

First, as shown in FIGS. 3A and 3B, a metal such as chromium, molybdenum, aluminum, silver, or an alloy thereof is deposited on the transparent insulating substrate 110 by sputtering to form a single layer or a plurality of gate metal layers. . Thereafter, the metal layer is dry or wet etched by a photolithography process to form gate lines 121 and 124 on the substrate 110. Sidewalls of these 121 and 124 are formed to be tapered during etching, and the tapered shape allows the layers formed thereon to be in close contact with each other.

13A and 13B, an insulating material such as silicon nitride covering the gate lines 121 and 124 is deposited to form a gate insulating layer 140, and then impurities are doped on the gate insulating layer 140. By depositing amorphous silicon that is not doped, amorphous silicon doped with impurities, an amorphous silicon film 150 that is not doped with impurities and an amorphous silicon film 160 that is doped with impurities are sequentially stacked. The amorphous silicon film 150 not doped with impurities is formed of hydrogenated amorphous silicon, and the like, and the amorphous silicon film 160 doped with impurities is heavily doped with an n-type impurity such as phosphorus (P). It is formed of silicon or silicide.

After depositing a metal such as aluminum, silver, chromium, molybdenum or an alloy thereof by sputtering on the amorphous silicon film 160 doped with impurities in succession to form a single layer or a plurality of metal films 170, A photosensitive material is coated on the metal layer 170 to form a photoresist film, and then exposed and developed to form photoresist patterns 52 and 54 having different thicknesses.

As described above, there may be various methods of varying the thickness of the photoresist film according to the position, and the transparent mask and the light blocking area as well as the translucent area may be provided in the exposure mask. Yes. The translucent region is provided with a slit pattern, a lattice pattern, or a thin film having a medium transmittance or a medium thickness. When using the slit pattern, it is preferable that the width of the slits and the interval between the slits are smaller than the resolution of the exposure machine used for the photographic process. Another example is to use a photoresist film that can be reflowed. That is, a thin portion is formed by forming a reflowable photoresist pattern with a normal mask having only a transparent region and a light shielding region and then reflowing so that the photoresist film flows into an area where no photoresist remains.

Given the appropriate process conditions, the lower layers may be selectively etched due to the difference in thickness of the photoresist patterns 52 and 54. Therefore, a plurality of data lines 171 and a plurality of drain electrodes 175 each including a plurality of source electrodes 173 as shown in FIG. 14 are formed through a series of etching steps, and a plurality of protrusions 163 are formed. A plurality of linear semiconductor contacts 161 including a plurality of linear ohmic contact members 161, a plurality of island type ohmic contact members 165, and a plurality of protrusions 154 are formed.

For convenience of description, a portion of the conductor layer 170 positioned at the portion where the wiring is to be formed, the amorphous silicon layer 160 doped with impurities, and the amorphous silicon layer 150 without doping impurities are referred to as the wiring portion A. The portion of the conductor layer 170, the impurity doped amorphous silicon layer 160 and the impurity doped amorphous silicon layer 150 located at the portion where the channel is formed is called a channel portion B, and the channel and wiring portions A portion of the conductor layer 170, the amorphous silicon layer 160 doped with impurities, and the amorphous silicon layer 150 not doped with impurities is located in the other region (C).

One example of the order of forming such a structure is as follows.

First, (1) removing the conductor layer 170, the impurity amorphous silicon layer 160 and the amorphous silicon layer 150 located in the other portion (C), (2) removing the photoresist film 54 located in the channel portion (B). , (3) removing the conductor layer 170 and the impurity amorphous silicon layer 160 located in the channel portion B, and (4) removing the photosensitive film 52 located in the wiring portion A.

Other methods include (1) removing the conductor layer 170 located in the other portion (C), (2) removing the photosensitive film 54 located in the channel portion (B), and (3) impurity amorphous in the other portion (C). Removal of the silicon layer 160 and the amorphous silicon layer 150, (4) removal of the conductor layer located in the channel portion B, (5) removal of the photosensitive film 52 located in the wiring region A, and (6) channel portion. It may proceed in the order of removing the impurity amorphous silicon layer 160 located in (B).

This section describes the first example.

First, as shown in FIG. 14, the conductive layer 170 exposed to the other region C is removed by wet etching or dry etching, and the other portion C of the amorphous silicon layer 160 doped with impurities thereunder. Expose

The data line 171 and the drain electrode 175 are still attached. In the case of using dry etching, the upper portions of the photoresist films 52 and 54 may be cut to a certain thickness.

Next, the amorphous silicon layer 160 doped with impurities in the other portion C and the amorphous silicon layer 150 without dopants under the impurities are removed, and the photoresist film 54 of the channel portion B is removed. It removes to expose the lower conductor 170.

Removal of the photoresist of the channel portion B may be performed simultaneously with or separately from the removal of the amorphous silicon layer 160 doped with impurities in the other region C and the amorphous silicon layer 150 without the impurities. Residue of the photoresist film 54 remaining in the channel region B is removed by ashing. In this step, the semiconductor layer 151 is completed.

Here, when the conductor layer 170 is a material that can be dry etched, the manufacturing process may be performed by continuously dry etching the amorphous silicon layer 160 doped with impurities below and the amorphous silicon layer 150 doped with impurities. In this case, it may or may not be performed in an in-situ manner in which dry etching is sequentially performed on the three layers 170, 160, and 150 in the same etching chamber.

Next, as shown in FIGS. 13A and 15, the conductor 170 positioned in the channel portion B and the amorphous silicon layer 160 doped with impurities are etched and removed. In addition, the photosensitive film 52 of the remaining wiring portion A is also removed.

In this case, the upper portion of the amorphous silicon layer which is not doped with impurities in the channel portion B may be partially removed to reduce the thickness, and the photoresist layer 52 of the wiring portion A may be etched to some extent.

In this way, each of the conductors 174 is completed while being separated into one data line 171 and a plurality of drain electrodes 175, and the amorphous silicon layer 160 doped with impurities also includes the linear ohmic contact layer 161. Completed by dividing into an island-type resistive contact layer 165.

The data lines 171, 173, 179 and the drain electrode 175 may also be formed in a tapered shape like the gate lines 121, 124, and 129 to increase adhesion to the upper layer.

Next, as shown in FIGS. 16A and 16B, the protective film 180 is formed by stacking silicon nitride or silicon oxide so as to cover the semiconductor layer 151 that is not covered by the data lines 171 and 173 and the drain electrode 175. Form.

Thereafter, a photosensitive organic material including red, green, and blue pigments is sequentially applied, and a red filter 230R, a green filter 230G, and a blue filter 230B are sequentially formed through a photographic process, and at the same time, a semiconductor layer of the thin film transistor. A channel light blocking layer 55 is formed on the channel portion 154 of the edge, and a red filter 230R, a green filter 230G, and a blue filter 230B are stacked around the pixel region where the pixel electrode is formed. The light blocking layer 58 is formed. The method of forming the channel light blocking layer 55 and the edge light blocking layer 58 is the same as the method shown in FIGS. 7 to 10.

When the red filter 230R, the green filter 230G, and the blue filter 230B are formed by the photolithography process, the openings 231 and 232 are formed in portions corresponding to the conductor pattern 177 and the drain electrode 175. Form.

Thereafter, the passivation layer 180 is etched by a photolithography process using a mask to expose the openings 231 and 232 and the drain electrodes 175 and the conductor pattern 177 to expose the contact holes 183 and 185 and the data line 171. A contact hole 182 exposing one end portion 179 of the () is formed.

Subsequently, as shown in FIGS. 11 and 12, a transparent conductive material such as ITO or IZO is deposited on the substrate 110, and is etched by a photolithography process using a mask to etch one end of the data line through the contact hole 182. A pixel electrode 190 connected to the conductor pattern 177 and the drain electrode 175 is formed through the contact auxiliary member 82, the contact holes 183 and 185, and the openings 231 and 232 connected to the portion. .

A thin film transistor array panel according to another exemplary embodiment of the present invention is illustrated in FIG. 17. Here, the same reference numerals as in the above-described drawings indicate the same members having the same function.

As shown in FIG. 17, one end portion 129 of the gate line 121 is used to receive a signal transmitted from a gate driving circuit (not shown) and has a width wider than the width of the gate line 121. Can be.

The passivation layer 180 has a plurality of contact holes 181 exposing the end portion 129 of the gate line 121, and the contact hole 181 contacts the end portion 129 of the gate line 121. A plurality of contact auxiliary members 81 are formed. The contact auxiliary member 81 and the contact hole 181 may have a gate driving circuit (not shown) for supplying a signal to the gate line 121 in the form of a chip, such as the display panel 100 or a flexible circuit board (not shown). Required if mounted on On the other hand, when the gate driving circuit is made of a thin film transistor or the like directly on the substrate 110, the contact hole 181 and the contact auxiliary member 81 are not required as in the case of FIGS. 1 and 2.

As shown in FIG. 18, the liquid crystal display according to the exemplary embodiment of the present invention may include the thin film transistor array panel 100, the upper display panel 200, and the thin film transistor array panel 100 and the upper display panel according to the exemplary embodiment. It includes the liquid crystal layer 3 formed between the (200).

The thin film transistor array panel 100 includes a first substrate 110, a gate line 121 formed on the first substrate 110, a gate insulating layer 140 formed on the gate line, and a semiconductor layer formed on the gate insulating layer. 151, the data line 171 and the drain electrode 175 formed on the semiconductor layer, and the passivation layer 180 formed on the data line and the drain electrode. Then, the color filters 230R, 230G and 230B formed on the passivation layer 180, the red filter 230R and the green filter 230G stacked on the channel portion 154 of the semiconductor layer on the passivation layer 180, and And a channel light blocking layer 55 made of a blue filter 230B. The edge light blocking layer 58 in which the red filter 230R, the green filter 230G, and the blue filter 230B are stacked is formed on the periphery of the pixel region where the pixel electrode is formed. The pixel electrode 190 electrically connected to the drain electrode is formed on the color filters 230R, 230G, and 230B, the channel light blocking layer 55, and the edge light blocking layer 58.

The upper panel 200 includes a second substrate 210 positioned above the first substrate 110 at a predetermined interval and a common electrode 270 formed on the second substrate.

Since the light blocking black matrix is not formed on the upper display panel, light leakage defects caused by both ends of the light blocking black matrix may be prevented and the contrast ratio may be improved.

Although the present invention has been described with reference to one embodiment shown in the accompanying drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Could be. Accordingly, the true scope of protection of the invention should be defined only by the appended claims.

The liquid crystal display according to the present invention removes the light blocking matrix of the upper substrate and overlaps the red filter, the green filter, and the blue filter on the thin film transistor channel portion of the thin film transistor array panel to form a channel light blocking layer. There is an advantage that can prevent the light leakage by both ends and improve the contrast ratio.

In addition, since the channel light blocking layer may be formed on the thin film transistor channel portion of the thin film transistor array panel to have a smaller area than that of the black matrix for blocking light of the conventional upper substrate, the aperture ratio may be improved.

Claims (8)

Insulation board, A gate line formed on the insulating substrate, A gate insulating film formed on the gate line, A semiconductor layer formed on the gate insulating film, A data line and a drain electrode formed on the semiconductor layer; A protective film formed on the data line and the drain electrode, A color filter formed on the protective film, A pixel electrode formed on the color filter and electrically connected to the drain electrode Including; A channel light blocking layer in which a red filter, a green filter, and a blue filter are stacked is formed on the channel portion of the semiconductor layer, and a red filter, a green filter, and a blue filter are stacked around the pixel area where the pixel electrode is formed. A thin film transistor array panel with a border light blocking layer formed thereon. In claim 1, The channel light blocking layer is formed to be smaller than or equal to the area of the channel portion of the semiconductor layer. In claim 2, And a red filter, a blue filter, and a blue filter stacked on the channel portion of the semiconductor layer, each of which is thinner than a color filter formed in most of the pixel region. Forming a gate line, a data line and a thin film transistor on the insulating substrate, Forming a protective film, A color filter is formed in the pixel region on the passivation layer, and a channel light blocking layer in which a red filter, a green filter, and a blue filter are stacked is formed on the channel portion of the semiconductor layer of the thin film transistor, and a red filter is formed at the periphery of the pixel region. Forming a light blocking layer on which a green filter and a blue filter are stacked; Forming a pixel electrode electrically connected to the thin film transistor on the color filter and the channel light blocking layer; Method of manufacturing a thin film transistor array panel comprising a. In claim 4, Forming the channel light blocking layer is Forming a red filter in the red pixel area on the passivation layer, and forming a red filter having a channel shape on the channel part of the thin film transistor in the green pixel area and the blue pixel area, respectively; Forming a green filter on the green pixel area on the passivation layer, and forming a channel-shaped green filter on the channel part of the thin film transistor in the red pixel area and the blue pixel area, respectively; Forming a blue filter in the blue pixel area on the passivation layer, and forming a channel filter-shaped blue filter on the channel part of the thin film transistor in the red pixel area and the green pixel area, respectively; Method of manufacturing a thin film transistor array panel comprising a. In claim 5, And each of the red, green, and blue filters of the channel light blocking layer and the edge light blocking layer are thinner than the red filter, the green filter, and the blue filter formed in the pixel region. In claim 6, And a red filter, a green filter, and a blue filter of the channel light blocking layer and the edge light blocking layer are formed using a slit photomask. A first substrate, a gate line formed on the first substrate, a gate insulating film formed on the gate line, a semiconductor layer formed on the gate insulating film, a data line and a drain electrode formed on the semiconductor layer, the data A passivation layer formed on the line and the drain electrode, a color filter formed on the passivation layer, and a pixel electrode formed on the color filter and electrically connected to the drain electrode, wherein the red color is formed on the channel portion of the semiconductor layer. A thin film transistor array panel including a channel light blocking layer in which a filter, a green filter, and a blue filter are stacked, and an edge light blocking layer in which a red filter, a green filter, and a blue filter are stacked is formed at a periphery of the pixel region; An upper display panel including a second substrate positioned above the first substrate and spaced apart from the first substrate, and a common electrode formed on the second substrate; And a liquid crystal layer formed between the thin film transistor array panel and the upper display panel.