KR100623980B1 - Thin film transistor array panel for liquid crystal display and manufacturing method of the same - Google Patents

Abstract

A gate wiring extending in the horizontal direction is formed on the insulating substrate, and the first insulating film, the semiconductor layer, the contact layer, and the metal layer are successively stacked on the gate wiring, and the metal layer and the contact layer are patterned together to form the data wiring and the contact layer below it. A pattern is formed, a second insulating film is stacked on the data line, and the second insulating film, the semiconductor layer, and the gate insulating film are patterned together to form first to third contact holes exposing the gate pad, the data pad, and the drain electrode, respectively. And an opening for exposing the first insulating film between two adjacent data lines. A color filter is formed on the first insulating film exposed through the opening, and a pixel electrode is formed on the color filter to manufacture a thin film transistor substrate for a liquid crystal display device. In this way, the total number of photolithography processes for manufacturing a liquid crystal display device can be reduced, thereby reducing manufacturing costs, and by forming a black matrix and a color filter on the thin film transistor substrate, it is necessary to consider alignment errors when assembling the upper and lower substrates. As a result, the aperture ratio of the liquid crystal display device can be improved.

Liquid Crystal Display, Thin Film Transistor Board, Black Matrix, Color Filter, Photo Etching Process

Description

Thin film transistor substrate for liquid crystal display device and manufacturing method therefor {THIN FILM TRANSISTOR ARRAY PANEL FOR LIQUID CRYSTAL DISPLAY AND MANUFACTURING METHOD OF THE SAME}

1 is a layout view of a thin film transistor substrate for a liquid crystal display according to a first exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along line II-II ′ of FIG. 1;

3A is a layout view of a substrate in a first step of manufacturing a thin film transistor substrate according to the first embodiment of the present invention;

3B is a cross-sectional view taken along line IIIb-IIIb ',

4A is a layout view of the substrate in the next step of FIGS. 3A and 3B;

4B is a cross-sectional view taken along line IVb-IVb 'of FIG. 4A.

FIG. 5 is a cross-sectional view taken along line IIIb-IIIb 'and shows a state in which substrates and photomasks are aligned at intermediate stages of FIGS. 3b and 4b;

6A is a layout view of the substrate in the next step of FIGS. 4A and 4B;

FIG. 6B is a cross-sectional view taken along line VIb-VIb ′ of FIG. 6A;

FIG. 7A is a layout view of a substrate in the next step of FIGS. 6A and 6B;

FIG. 7B is a cross-sectional view taken along the line VIIb-VIIb 'of FIG. 7A;

8 is a layout view of a thin film transistor substrate according to a second exemplary embodiment of the present invention.

9 is a cross-sectional view taken along line VII-VII 'of FIG. 8,

10 is a layout view of a thin film transistor substrate according to a third exemplary embodiment of the present invention.

FIG. 11 is a cross-sectional view taken along line XI-XI ′ of FIG. 10.

12A is a layout view of a substrate in an intermediate step of manufacturing a thin film transistor substrate according to the third embodiment of the present invention;

12B is a sectional view taken along line XIIb-XIIb ′,

FIG. 13 is a cross-sectional view taken along line XIIb-XIIb ', illustrating a state in which a substrate and an optical mask are aligned in a photolithography process for forming the pattern of FIG. 4b;

14A is a layout view of the substrate in the next step of FIGS. 12A and 12B,

FIG. 14B is a cross sectional view taken along line XIVb-XIVb ′ of FIG. 14A;

15 is a layout view of a thin film transistor substrate according to a fourth exemplary embodiment of the present invention.

FIG. 16 is a cross-sectional view taken along line XVI-XVI ′ of FIG. 15;

17 is a layout view of a thin film transistor substrate according to a fifth exemplary embodiment of the present invention.

FIG. 18 is a cross-sectional view taken along line XVIII-XVIII ′ of FIG. 17;

FIG. 19 is a cross-sectional view taken along line XVIII-XVIII ′ of FIG. 17 and illustrates an alignment state of a photomask and a substrate in an intermediate process of manufacturing a thin film transistor substrate,

20 is a layout view of a thin film transistor substrate according to a sixth exemplary embodiment of the present invention.

FIG. 21 is a cross-sectional view taken along line XXI-XXI ′ of FIG. 20;

FIG. 22 is a cross-sectional view taken along line XXI-XXI ′ of FIG. 20 and illustrates an alignment state of an optical mask and a substrate in an intermediate process of manufacturing a thin film transistor substrate.

The present invention relates to a liquid crystal display device, and more particularly, to a thin film transistor substrate for a liquid crystal display device.

In general, a liquid crystal display device injects a liquid crystal material between an upper substrate on which a common electrode, a color filter, and the like are formed, and a lower substrate on which a thin film transistor and a pixel electrode are formed. By applying a different potential to form an electric field to change the arrangement of the liquid crystal molecules, and through this to control the light transmittance is a device that represents the image.

Among the liquid crystal display devices, a common electrode and a pixel electrode are mainly used on two substrates, and a thin film transistor for switching a voltage applied to the pixel electrode is formed on a substrate on which the pixel electrode is formed, and a common electrode is formed. On the substrate, a color filter and a black matrix are formed.

However, in the case where the color filter and the black matrix are formed on a substrate different from the pixel electrode, the black matrix should be formed to have a certain margin in consideration of the alignment margin during assembly of the upper and lower substrates. However, the wider the black matrix, the lower the aperture ratio.

In addition, in the process of manufacturing the upper and lower substrates are subjected to several photolithography process, the number of such photolithography process is a big factor that determines the manufacturing cost. Therefore, it is necessary to reduce the number of photo etching processes as much as possible.

An object of the present invention is to simplify the manufacturing process of the liquid crystal display device.

Another object of the present invention is to increase the aperture ratio of a liquid crystal display.

In order to solve this problem, in the present invention, a plurality of thin films are formed in different patterns through a single photolithography process, and color filters are formed on the thin film transistor substrate.

Specifically, forming a gate wiring including a gate line extending in the horizontal direction on the insulating substrate, a gate electrode which is a part of the gate line and a gate pad connected to one end of the gate line, a first insulating film on the gate wiring, Stacking the semiconductor layer and the metal layer successively; patterning the metal layer so that the data line extends in the longitudinal direction, a source electrode which is a part of the data line, a data pad formed at one end of the data line, and is separated from the source electrode Forming a data line including the drain electrode as viewed, stacking a second insulating film on the data line, and patterning the second insulating film, the semiconductor layer, and the gate insulating film together to form the gate pad, the data pad, and the drain electrode. Each of the first to third contact holes Forming an opening that exposes a first insulating film between two adjacent data lines, forming a color filter on the first insulating film exposed through the opening, and forming a pixel electrode on the color filter. A thin film transistor substrate for a liquid crystal display device is manufactured through the process described above.

In this case, the contact layer may also be patterned together in the step of further stacking the contact layer on the semiconductor layer and patterning the metal layer. The patterning of the second insulating film, the contact layer, the semiconductor layer, and the first insulating film together may include stacking a photoresist film on the second insulating film and dividing the photoresist film into three or more steps according to the position of the light transmittance. The method may include exposing through the substrate, developing the photosensitive film, and etching the second insulating film, the contact layer, the semiconductor layer, and the first insulating film together with the photosensitive film.

Here, after the step of patterning the second insulating film, the semiconductor layer and the first insulating film together, a black matrix may be further formed, or the second insulating film may be used as the black matrix.

Or forming a gate wiring on the insulating substrate, the gate wiring including a gate line extending in a horizontal direction, a gate electrode which is a part of the gate line, and a gate pad connected to one end of the gate line, wherein the first insulating film and the semiconductor layer are formed on the gate wiring. And sequentially stacking a metal layer, and patterning the metal layer and the semiconductor layer together to separate the data line extending in the longitudinal direction, a source electrode which is a part of the data line, and a data pad formed at one end of the data line and the source electrode. Forming a data line including the drain electrode facing each other, and removing the semiconductor layer between the data line except for the channel portion between the source electrode and the drain electrode, wherein the gate pad and the data are respectively disposed on the data line. To expose the pad and drain electrodes. Forming a second insulating film having first to third contact holes, forming a color filter in an area between the data lines, and a pixel electrode connected to the drain electrode through the third contact hole on the color filter; A thin film transistor substrate may be manufactured through a process including forming a film.

In this case, the contact layer may be further stacked on the semiconductor layer, and the contact layer may be patterned together in the patterning of the metal layer and the semiconductor layer to form a contact layer pattern having substantially the same outline as the data line. The patterning of the metal layer, the contact layer, and the semiconductor layer together may include stacking a photoresist film on the metal layer, exposing the photoresist film through a photomask in which light transmittance is divided into three or more steps according to positions, and developing the photoresist film. And etching the metal layer, the contact layer, and the semiconductor layer together with the photosensitive film.

Here, the black matrix may be further formed after the patterning of the metal layer and the semiconductor layer together, and the second insulating layer may be formed of the black matrix.

Forming a gate wiring including a gate line extending in a horizontal direction on the insulating substrate, a gate electrode which is a part of the gate line, and a gate pad connected to one end of the gate line, wherein the first insulating film, the semiconductor layer, and the metal layer are formed on the gate wiring; Stacking the metal layers in succession, and patterning the metal layer to extend in a lengthwise direction, a source electrode which is a part of the data line, a data pad formed at one end of the data line, and a drain electrode which is separated from and facing the source electrode. Forming a data line including a data line; stacking a second insulating layer on the data line; and patterning the second insulating layer, the semiconductor layer, and the gate insulating layer together to expose the gate pad, the data pad, and the drain electrode, respectively. Forming first to third contact holes and adjoining them Forming an opening for exposing the insulating substrate and the gate wiring between the data lines, forming a color filter on the insulating substrate and the gate wiring exposed through the opening, and forming a pixel electrode on the color filter. The thin film transistor substrate may be manufactured through a process including the same.

In this case, in the step of further stacking the contact layer on the semiconductor layer and patterning the metal layer, the contact layer may also be patterned together, and the second insulating layer may be formed of a black matrix.

Next, a structure of a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention will be described with reference to the drawings.

First, the structure of the thin film transistor substrate for a liquid crystal display according to the first embodiment of the present invention will be described.

1 is a layout view of a thin film transistor substrate for a liquid crystal display according to a first exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along line II-II ′ of FIG. 1.

First, a gate made of a metal or a conductor such as aluminum (Al) or aluminum alloy (Al alloy), molybdenum (Mo) or molybdenum-tungsten (MoW) alloy, chromium (Cr), tantalum (Ta) or the like on the insulating substrate 10. Wiring is formed. The gate wiring is connected to a scan signal line or gate line 22 extending in the horizontal direction, a gate pad 24 connected to the end of the gate line 22 to receive a scan signal from the outside, and to transfer the scan signal to the gate line 22. The gate electrode 26 of the thin film transistor that is part of the gate line 22 is included.

The gate wirings 22, 24, and 26 may be formed in a single layer, but may also be formed in a double layer or a triple layer. In the case of forming more than two layers, it is preferable that one layer is formed of a material having a low resistance and the other layer is formed of a material having good contact properties with other materials, and a double layer of Cr / Al (or Al alloy) or Al / Mo Bilayers are an example.

A gate insulating layer pattern 30 made of silicon nitride (SiN _x ) is formed on the gate lines 22, 24, and 26 to cover the gate lines 22, 24, and 26.

A semiconductor pattern 40 made of a semiconductor such as hydrogenated amorphous silicon is formed on the gate insulating layer pattern 30, and is heavily doped with n-type impurities such as phosphorus (P) on the semiconductor pattern 40. An ohmic contact layer pattern 50 made of amorphous silicon is formed.

On the contact layer pattern 50, a data line made of a conductive material such as Mo or MoW alloy, Cr, Al or Al alloy, Ta is formed. The data line is connected to one end of the data line 62, the data line 62 formed in the vertical direction, and the thin film transistor which is a branch of the data pad 64 and the data line 62 to which an image signal from the outside is applied. And a drain electrode 66 of the thin film transistor, which is separated from the source electrode 65 and is disposed opposite the source electrode 65 with respect to the gate electrode 26.

The data lines 62, 64, 65, and 66 may be formed in a single layer like the gate lines 22, 24, and 26, but may also be formed in a double layer or a triple layer. Of course, when forming more than two layers, it is preferable that one layer is made of a material having a low resistance and the other layer is made of a material having good contact properties with other materials.

The contact layer pattern 50 lowers the contact resistance between the semiconductor pattern 40 at the bottom thereof and the data lines 62, 64, 65, 66 thereon, and the data lines 62, 64, 65, 66. ) Is exactly the same form.

The semiconductor pattern 40 has a shape similar to that of the data lines 62, 64, 65, and 66 and the contact layer pattern 50. Specifically, it is formed long in the same direction as the data line 62, but is formed in a slightly wider width than the data line 62. In addition, the source electrode 65 and the drain electrode 66 are also connected to each other without disconnection to generate a channel of the thin film transistor. On the other hand, the semiconductor pattern 40 also extends to the periphery and is formed over the entire periphery.

The data wirings 62, 64, 65, and 66 and the semiconductor pattern 40 are covered with the protective film 80, and the protective film 80 contacts the windows 81 and 84 exposing the drain electrode 66 and the data pad 64. Has) The passivation layer 80 also has a contact window 83 exposing the gate pad 24 together with the gate insulating film 30 and the semiconductor pattern 40, and a portion of the gate line 22 overlapping the data line 62. Except for the rest is not covered. In this case, the passivation layer 80 has substantially the same outline as the semiconductor pattern 40 except for the portions of the contact holes 81 and 84. This is because the protective film 80 and the semiconductor pattern 40 are formed together as described later. Meanwhile, the passivation layer 80 may be made of an organic insulating material such as silicon nitride or acrylic, and may cover and protect at least a channel portion between the source electrode 65 and the drain electrode 66 of the semiconductor pattern 40. do.

A black matrix 90 made of a black organic material is formed on the data lines 62, 65 and 66 except for the pads 24 and 64 and the passivation layer 80 on the gate lines 22 and 26. The black matrix 90 is formed to prevent leakage of light due to an electric field formed at the periphery of the pixel electrode 71. In some cases, the black matrix 90 is not formed on the gate line 22. It may not. The black matrix 90 is provided with a contact hole for exposing the drain electrode 66, which is narrower in the center of the contact hole 81 in the protective film pattern 80.

The color filter 100 is formed on the gate insulating film 30 in the region between the data lines 62. The color filter 100 is alternately formed red, green, and blue. At this time, in the present embodiment, the color filters 100 of the same color are formed long up and down without being separated with the gate line 22 as a boundary, but each pixel area is formed by separating the gate filter 22 with the gate line 22 as a boundary. Each color filter 100 may be formed. In addition, the color filter 100 may extend to the top of the contact hole 81. In this case, a contact hole must also be formed in the color filter 100 to connect the drain electrode 66 and the pixel electrode 71, and the size must be at least 4 μm × 4 μm. This is because the color filter 100 is usually formed using a large aligner exposure machine.

The pixel electrode 71 is formed on the color filter 100. The pixel electrode 71 is physically and electrically connected to the drain electrode 66 through the contact window 871 to receive an image signal from the thin film transistor to generate an electric field together with the electrode of the upper plate, such as indium tin oxide (ITO). Made of transparent conductive material In this case, the pixel electrode 71 is formed to be wide so that a part of the pixel electrode 71 overlaps with the gate line 22 and the data line 62. In addition, an opening (not shown) may be formed in the pixel electrode 71 above the channel portion of the thin film transistor.

On the other hand, an auxiliary gate pad 73 and an auxiliary data pad 74 connected to the gate pad 24 and the data pad 64 through the contact windows 83 and 84, respectively, are formed. , 64) and to protect the pads and the adhesion of the external circuit device, it is not essential, and their application is optional.

Next, a method of manufacturing a liquid crystal display substrate according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 3A to 7B and FIGS. 1 and 2.

First, as illustrated in FIGS. 3A and 3B, a conductive layer such as a metal is deposited to a thickness of 1,000 kPa to 3,000 kPa by a sputtering method and dry or wet etched using a first mask to form a substrate 10. A gate wiring including a gate line 22, a gate pad 24, and a gate electrode 26 is formed thereon. Next, the gate insulating film, the semiconductor layer, and the contact layer are successively deposited in a thickness of 1,500 kV to 5,000 kV, 500 kV to 1,500 kV, 300 kV to 600 kV, respectively, by chemical vapor deposition, and then sputtering the conductive layer such as metal. It is deposited in a thickness of 1,500 kPa to 3,000 kPa by the method described above. Subsequently, the conductor layer and the contact layer thereunder are photo-etched using the second mask to form a data line including the data line 62, the data pad 64, the source electrode 65, and the drain electrode 66. The lower contact layer pattern 50 is formed.

As shown in FIGS. 4A and 4B, silicon nitride is deposited by CVD or spin-coated an organic insulating material to form a protective film having a thickness of 3,000 3,000 or more, and then the protective film, the semiconductor layer, and the gate insulating film are formed using a third mask. Patterning is performed to form these patterns, including contact windows 81, 83, 84. At this time, the protective layer, semiconductor layer, and gate insulating film on the gate pad 24 are removed in the peripheral portion, which is not shown on the screen (the protective film on the data pad 64 is also removed), but only the protective film and the semiconductor layer are removed from the screen display section [ Also remove the passivation layer on the drain electrode 66] The semiconductor layer pattern should be formed so that the channel is formed only in the required portion. To this end, a method of forming a photoresist pattern having a different thickness according to a portion and etching the lower layers using the etching mask as an etching mask will be described with reference to FIG. 5.

As shown in FIG. 5, after the photoresist film PR, preferably a positive photoresist film, is applied on the protective film to a thickness of 5,000 kPa to 30,000 kPa, it is exposed through the third mask 200. The photosensitive film PR after exposure is different from the screen display portion and the peripheral portion, as shown in FIG. 5. That is, the portion C of the photosensitive film PR exposed to light in the screen display unit decomposes the polymer by reacting with light only from a surface to a predetermined depth, and the polymer remains thereunder, but the photosensitive film PR of the peripheral portion is On the contrary, the part B exposed to the light reacts to the light to the lower portion, whereby the polymer is decomposed. Here, portions C and B exposed to light in the screen display unit or the peripheral portion are portions where the protective layer 80 is to be removed.

In order to form such a photoresist film PR, as shown in FIG. 5, a photomask used during exposure may include a transparent substrate 210 and a transmittance adjusting film 220 that transmits only a part of light thereon, chromium, and the like. It is formed of a double layer of the opaque layer 230 made of an opaque material of. In this case, the portion corresponding to the region B is removed to remove all of the transmittance adjusting film 220 and the opaque layer 230 so that the light transmittance is 90% or more, and the portion corresponding to the region C is removed only the opaque layer 230. The light transmittance is between 20% and 40%, and the portion corresponding to the area A leaves both layers 220 and 230 so that the light transmittance is 3% or less.

Another type of photomask is to form only an opaque layer, but to remove the opaque layer in the portion corresponding to the B region and to form a slit or mosaic pattern having a size of 2.5 μm or less in the portion corresponding to the C region to reduce the light transmittance. Can be used.

After exposing the photoresist film PR in this manner, when developing, the photoresist film pattern PR having a different thickness depending on the position is formed. That is, the photoresist is not formed on a portion of the gate pad 24 and the data pad 64, and all peripheral portions except the gate pad 24 and the data pad 64 and the screen display portion except for part of the drain electrode 66. A thick photoresist film is formed on the upper portion of the semiconductor layer 40 between the data wirings 62, 64, and 65, the drain electrode 66, and the source electrode 65, and a portion of the drain electrode 66 and other portions of the screen display. A thin photosensitive film is formed in the film.

Subsequently, etching is performed on the photoresist pattern PR and the lower layers thereof, that is, the protective layer, the semiconductor layer, and the gate insulating layer by a dry etching method.

At this time, as mentioned above, the thick portion of the photoresist pattern PR should remain without being completely removed, and the protective film, the semiconductor layer and the gate insulating film under the portion without the photoresist should be removed, and only the protective film and the semiconductor layer beneath the thin portion. And the gate insulating layer should not be removed, and only the passivation layer should be removed on the drain electrode 66.

To this end, it is preferable to use a dry etching method capable of simultaneously etching the photoresist pattern PR and the films below it.

In addition, when the protective film and the semiconductor layer are etched together with the thin photosensitive film, a portion of the semiconductor layer may remain on the gate insulating film due to the non-uniform thickness of the thin photosensitive film. In order to prevent this, the photoresist pattern PR and the lower layer may be etched in several steps. That is, the pads 24 and 64 are exposed by removing the passivation layer, the semiconductor layer, and the gate insulating layer of the portion where all of the photoresist layer is removed by primary etching, and then ashing the photoresist pattern to remove the thin portion of the photoresist pattern. The protective film pattern 80 is completed by removing the exposed protective film. At this time, the gate insulating film pattern 30, which may remain on the pads 24 and 64, is also removed to complete the gate insulating film pattern 30. Next, the semiconductor pattern 40 is completed by etching the exposed semiconductor layer due to the removal of the protective film, and the photoresist pattern is removed.

In the above, the photoresist film PR is separately coated on the passivation film, and the photoresist film is exposed and developed to form a photoresist film PR pattern having a different thickness depending on the position. Then, together with the photoresist pattern PR, the protective film, semiconductor layer, and gate insulating film underneath it. The protective film itself is formed of a photosensitive organic material, for example, a product code PC 403 supplied by JSR of Japan, and a pattern having a different thickness depending on the position of the protective film is exposed through an exposure and development process. After the formation, the semiconductor layer and the gate insulating film under the protective film pattern can be etched. In this case, the process of separately applying the photoresist film or the process of ashing and removing the remaining photoresist film PR can be omitted.

6A to 6B, an organic black matrix is deposited and patterned by a fourth photolithography process to form a black matrix pattern 90. In this case, the black matrix pattern 90 may be formed without undergoing all photolithography processes. That is, a black photosensitive film is apply | coated, exposed, and developed, and a photosensitive film pattern is formed and it can also be used as the black matrix pattern 90. FIG.

Subsequently, as shown in FIGS. 7A to 7B, the color filter 100 of red, green, and blue is formed in the area between the data lines 62 by screen printing, or includes red, green, and blue pigments. It is formed by applying a photoresist film in sequence and by patterning in a fifth to seventh photolithography process using a mask.

Finally, as shown in FIGS. 1 and 2, an ITO layer having a thickness of 400 kHz to 500 kHz is deposited and etched using a fifth or eighth mask to etch the pixel electrode 71, the auxiliary gate pad 73, and The auxiliary data pad 74 is formed.

When the thin film transistor substrate is formed as described above, only the common electrode needs to be formed on the counter substrate, so that the total number of photolithography processes is reduced once by considering both the upper and lower substrates.

As such, by forming a plurality of thin films in different patterns through a single photolithography process, the number of photolithography processes can be reduced, and the black matrix 90 and the color filter 100 are formed on the thin film transistor substrate to fabricate the upper and lower substrates. It is not necessary to consider the alignment error of, thereby improving the aperture ratio of the liquid crystal display device.

Next, a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment of the present invention will be described.

8 is a layout view of a thin film transistor substrate according to a second exemplary embodiment of the present invention, and FIG. 9 is a cross-sectional view taken along the line 'VIII' of FIG. 8.

The thin film transistor substrate for a liquid crystal display according to the second embodiment is almost the same as that of the first embodiment. The difference is that no black matrix is formed. Therefore, the manufacturing method also needs to omit only the process of forming a black matrix in the manufacturing method of 1st Example.

In this case, the upper and lower plate alignment errors must be taken into consideration compared to the first embodiment, but the aperture ratio is reduced, but the black matrix formed on the upper plate can be formed by contacting the common electrode with a conductive material such as chromium, thereby reducing the resistance of the common electrode. You can.

A thin film transistor substrate according to a third embodiment of the present invention will be described.

10 is a layout view of a thin film transistor substrate according to a third exemplary embodiment of the present invention, and FIG. 11 is a cross-sectional view taken along line XI-XI ′ of FIG. 10.

In the third embodiment, the gate wirings 22, 24, and 26 and the gate insulating film pattern 30 have the same structure as in the first embodiment.

The semiconductor pattern 40 and the ohmic contact layer pattern 50 are successively formed on the gate insulating layer pattern 30, and the data lines 62, 64, 65, and 66 are formed on the contact layer pattern 50. In this case, the contact layer pattern 50 is formed in the same form as the data lines 62, 64, 65, and 66, and the semiconductor pattern 40 also includes a thin film transistor between the source electrode 65 and the drain electrode 66. It has the same form as the data lines 62, 64, 65, and 66 except that the portion which becomes the channel of is connected.

On the data lines 62, 64, 65, and 66, a passivation layer pattern 80 having contact holes 81, 83, and 84 exposing the gate pad 24, the data pad 64, and the drain electrode 66 is formed. Formed.

An organic black matrix pattern 90 is formed on the passivation layer pattern 80 on the data lines 62, 64, 65, 66 and the gate lines 62, 64, 66. The organic black matrix pattern 90 has a contact hole for exposing the drain electrode 66, which is formed narrower in the center of the contact hole 81 of the protective film pattern 80.

The color filter 100 is formed on the passivation layer 80 between two adjacent data lines 62, and is connected to the drain electrode through a contact hole formed in the black matrix 90 on the color filter 100. The pixel electrode 71 is formed.

The material used for each part of the thin film transistor substrate according to the third embodiment described above is the same as in the first embodiment.

A method of manufacturing a thin film transistor substrate according to a third embodiment of the present invention will now be described with reference to FIGS. 12A to 14B and FIGS. 10 and 11.

12A is a layout view of a substrate in an intermediate step of manufacturing a thin film transistor substrate according to a third embodiment of the present invention. FIG. 12B is a cross-sectional view taken along line XIIb-XIIb ', and FIG. 13 is XIIb-XIIb'. As a cross-sectional view of the line, the substrate and the photomask are aligned in the photolithography process for forming the pattern of FIG. 4B, FIG. 14A is a layout view of the substrate in the next steps of FIGS. 12A and 12B, and FIG. It is sectional drawing about the XIVb-XIVb 'line of FIG. 14A.

First, the gate wirings 22, 24, and 26 are formed on the insulating substrate 10 by using a first photolithography process, a gate insulating film, a semiconductor layer, a contact layer, and a metal layer are sequentially stacked on the gate wirings, and a metal layer, The contact layer and the semiconductor layer are simultaneously patterned through a second photolithography process to form a pattern of each thin film as shown in FIGS. 12A and 12B. That is, the semiconductor pattern 40, the contact layer pattern 50, and the data lines 62, 64, 65, and 66 have almost the same shape, but the semiconductor in the region between the source electrode 65 and the drain electrode 66. Only the fact that the pattern 40 is connected forms three thin film layer patterns.

The method used for this purpose uses the method used when patterning the protective film, the semiconductor layer, and the gate insulating film simultaneously in the first embodiment. That is, as shown in FIG. 13, after the photoresist film PR, preferably the positive photoresist film is laminated, the transmittance control film of the photomask 200 is formed at the portion where the data lines 62, 64, 65, and 66 are to be formed. Only the transmittance adjusting film 220 is formed in the portion where the semiconductor pattern 40 between the source electrode 65 and the drain electrode 66 should remain, and the portion where both the 220 and the opaque layer 230 are formed correspond to each other. Corresponding portions are formed, and other portions are exposed by corresponding portions where only the transparent substrate 210 is formed. Next, the photoresist film PR is developed to form a photoresist pattern having a different thickness depending on the position, and the metal layer, the contact layer, and the semiconductor layer below are etched together with the photoresist pattern. The etching process is broken down as follows.

First, the exposed metal layer is etched to expose the lower intermediate layer. In this process, either a dry etching method or a wet etching method may be used. In this case, the metal layer may be etched and the photoresist pattern may be hardly etched. However, in the case of dry etching, since it is difficult to find a condition in which only the metal layer is etched and the photoresist pattern is not etched, the photoresist pattern may also be etched together.

When the metal layer is any one of Mo or MoW alloy, Al or Al alloy, and Ta, either dry etching or wet etching can be used. However, since Cr is not easily removed by the dry etching method, only wet etching is preferable if the metal layer is Cr. CeNHO ₃ may be used as an etchant in the case of wet etching with a metal layer of Cr, and a mixed gas of CF ₄ and HCl or a mixture of CF ₄ and O ₂ as an etching gas for dry etching with a metal layer of Mo or MoW. Gases can be used, and in the latter case the etch ratio to the photoresist is nearly the same.

In this way, patterns of the data wirings 62, 64, 65, and 66 are formed and the underlying contact layer is exposed. However, the source and drain electrodes 65 and 66 are connected without being separated. In addition, when dry etching is used, the photoresist pattern is also etched to a certain thickness.

Subsequently, the exposed contact layer and the semiconductor layer below it are simultaneously removed by dry etching. In this step, the semiconductor pattern 40 is completed.

Subsequently, ashing removes the photoresist residue remaining on the surface of the metal layer between the source electrode and the drain electrode of the channel portion.

Next, the metal layer between the source electrode and the drain electrode and the contact layer below it are etched and removed. In this case, the etching may be performed only by dry etching with respect to both the metal layer and the contact layer, and may be performed by wet etching with respect to the metal layer and dry etching with respect to the contact layer. In the former case, it is preferable to perform etching under the condition that the etching selectivity of the metal layer and the contact layer is large. . For example, those of etching the metal layer using a mixed gas of SF ₆ and O _2. In the latter case of alternating between wet etching and dry etching, the side of the wet-etched metal layer is etched, but the dry-etched contact layer is hardly etched, thus making it stepped. Examples of the etching gas used to etch the contact layer and the semiconductor layer include the aforementioned mixed gas of CF ₄ and HCl or mixed gas of CF ₄ and O _{2. When} CF ₄ and O ₂ are used, The semiconductor pattern 40 may be left in the thickness.

In this way, the source electrode 65 and the drain electrode 66 are separated, thereby completing the data wirings 62, 64, 65, and 66 and the contact layer pattern 50 thereunder.

Finally, the photoresist remaining on the data line is removed.

As mentioned earlier, wet and dry etching can be alternately used or only dry etching can be used. In the latter case, since only one type of etching is used, the process is relatively easy, but it is difficult to find a suitable etching condition. On the other hand, in the former case, the etching conditions are relatively easy to find, but the process is more cumbersome than the latter.

Next, as shown in FIGS. 14A and 14B, the passivation layer 80 is stacked on the data lines 62, 64, 65, and 66, and patterned through a third photolithography process to form contact holes 81, 83, and 84. Next, the organic black matrix is stacked and patterned through a fourth photolithography process to form a black matrix pattern 90.

Next, red, green, and blue color filters 100 are formed by screen printing, or a process of applying a photosensitive film containing a pigment of any one of red, green, and blue colors, exposing and developing through a mask It forms by advancing about green, blue, and blue, respectively.

Finally, as shown in FIGS. 10 and 11, the pixel electrode 71, the auxiliary gate pad 73, and the auxiliary data pad 74 are deposited by depositing an ITO layer and patterning using a fifth or eighth photolithography process. ).

Also by the above method, the number of photolithography processes can be reduced, and the aperture ratio can be increased.

A thin film transistor substrate according to a fourth embodiment of the present invention will be described.

15 is a layout view of a thin film transistor substrate according to a fourth exemplary embodiment of the present invention, and FIG. 16 is a cross-sectional view taken along line XVI-XVI 'of FIG. 15.

The thin film transistor substrate according to the fourth embodiment is the same as the third embodiment except that no protective film is formed. In other words, the black matrix pattern 90 serves as a protective film. However, the black matrix pattern 90 should also be formed in the periphery of the third embodiment, but the black matrix pattern 90 may be formed in the periphery. Therefore, the manufacturing method is also the same as omitting the process of forming the protective film pattern in the manufacturing method of the third embodiment.

In this way, the number of photolithography processes can be reduced once more.

A thin film transistor substrate according to a fifth embodiment of the present invention will be described.

FIG. 17 is a layout view of a thin film transistor substrate according to a fifth exemplary embodiment of the present invention, FIG. 18 is a cross-sectional view taken along line XVIII-XVIII ′ of FIG. 17, and FIG. 19 is a cross-sectional view taken along line XVIII-XVIII ′ of FIG. 17. FIG. 11 is a diagram illustrating an alignment state of a photomask and a substrate in an intermediate process of manufacturing a thin film transistor substrate.

As shown in FIGS. 17 and 18, the thin film transistor substrate according to the fifth embodiment allows the black matrix 90 to function as a protective film without separately forming a protective film in the first embodiment. Therefore, in the first embodiment, the black matrix 90, the semiconductor layer 40 and the gate insulating film 30 below are simultaneously patterned using the black matrix 90 instead of the protective film, and the black matrix 90 is separately formed. The same is omitted if the step of forming a. That is, the gate wirings 22, 24, and 26 are formed on the insulating substrate 10, the gate insulating film, the semiconductor layer, the contact layer, and the metal layer are successively deposited thereon, and then the metal layer and the contact layer are patterned together to form the data wiring. (62, 64, 65, 66) and a contact layer pattern 50 are formed. Subsequently, as shown in FIG. 19, an organic black matrix layer is laminated, a photosensitive film is coated on the black matrix layer, and then exposed through a mask in which light transmittance is separated in three stages depending on the position. Next, the photoresist film is developed to form a photoresist pattern, and the black matrix layer, the semiconductor layer, and the gate insulating film are etched together with the photoresist pattern to complete the patterns 30, 40, and 90, and the color filter 100 and the color filter 100 ) And the auxiliary pads 73 and 74 on the pixel electrode 71.

At this time, the black matrix layer may be formed of a photosensitive material containing a black pigment. In this case, without forming a photoresist pattern on the black matrix layer separately, the black matrix layer is exposed and developed through a mask in which light transmittance is separated into three stages according to positions, thereby forming a black matrix layer having a different thickness depending on the position. The patterns 30, 40, and 90 may be formed by etching the semiconductor layer and the gate insulating layer below the black matrix layer.

This further reduces the number of photolithography steps once compared with the first embodiment.

Finally, a sixth embodiment of the present invention will be described.

20 is a layout view of a thin film transistor substrate according to a sixth exemplary embodiment of the present invention, FIG. 21 is a cross-sectional view taken along line XXI-XXI ′ of FIG. 20, and FIG. 22 is a cross-sectional view taken along line XXI-XXI ′ of FIG. 20. A diagram showing the alignment state of the photomask and the substrate during an intermediate process of manufacturing a thin film transistor substrate.

20 and 21, the thin film transistor substrate according to the sixth embodiment is the same except for the fifth embodiment and the gate insulating film pattern 30. That is, in the sixth embodiment, the gate insulating film between two neighboring data lines 62 is removed to have the same shape as that of the semiconductor pattern 40, and the color directly on the insulating substrate 10 and the gate line 22. The filter 100 is formed. At this time, the minimum width W of the portion where the gate insulating film between the two data lines 62 is removed should be 1 μm or more. That is, the separation width of the semiconductor layer 40 should be 1 μm or more. This is to prevent leakage current that may occur when neighboring data lines are connected through the semiconductor layer.

The manufacturing method of the thin film transistor substrate according to the sixth embodiment is similar to the manufacturing method according to the fifth embodiment, except that an optical mask in which light transmittance is divided into three stages is not used. This will be described with reference to FIG. 22 and FIGS. 20 and 21.

First, gate wirings 22, 24, and 26 are formed on the insulating substrate 10, and a gate insulating film, a semiconductor layer, a contact layer, and a metal layer are successively deposited thereon, and then the metal layer and the contact layer are patterned together to form a data wiring. (62, 64, 65, 66) and a contact layer pattern 50 are formed.

Subsequently, as shown in FIG. 22, an organic black matrix layer is laminated, a photosensitive film is applied on the black matrix layer, and then exposed through a general mask consisting of only a transparent portion and an opaque portion. Next, the photoresist film is developed to form a photoresist pattern, and the black matrix layer, the semiconductor layer, and the gate insulating film are etched using the photoresist pattern as an etch mask to complete each pattern 30, 40, and 90. At this time, the contact hole 83 exposing the gate pad 24, the contact hole 84 exposing the data pad 64, the contact hole 81 exposing the drain electrode 66, and two neighboring data lines. An opening for exposing the substrate 10 and the gate line 22 between the 62 is formed.

At this time, the black matrix layer may be formed of a photosensitive material containing a black pigment. In this case, instead of forming a photoresist pattern on the black matrix layer, the black matrix layer is exposed through a mask and developed to form a black matrix pattern 90, which is then etched to etch the lower semiconductor layer and the gate insulating layer. Each pattern 30 and 40 can be formed.

Subsequently, the color filter 100 filling the opening, the pixel electrode 71 on the color filter 100, and the auxiliary pads 73 and 74 are formed. At this time, the color filter 100 completely covers the exposed gate line 22 by removing the gate insulating film, and insulates the gate line 22 from the pixel electrode 71.

As described above, the number of photolithography processes for manufacturing a liquid crystal display device can be reduced twice, while using a general optical mask including only transparent and opaque portions.

In all the above embodiments, each element of the thin film transistor substrate may be formed of the material described in the first embodiment.

In addition, the thin film transistor substrate may be manufactured by various modified forms and methods.

By fabricating the thin film transistor substrate as described above, the total number of photolithography processes for manufacturing a liquid crystal display device can be reduced, thereby reducing the manufacturing cost. The upper and lower substrates are assembled by forming a black matrix and a color filter on the thin film transistor substrate. Since it is not necessary to consider the alignment error at the time, the aperture ratio of the liquid crystal display device can be improved.

Claims (27)

Insulation board, A gate line formed on the insulating substrate and including a gate line extending in a horizontal direction, a gate electrode which is a part of the gate line, and a gate pad connected to one end of the gate line; A first insulating film formed on the gate wiring and having a first contact hole for exposing the gate pad, A semiconductor pattern formed in the longitudinal direction on the first insulating film, A data line formed on the semiconductor pattern and extending in a vertical direction, a source electrode which is a part of the data line, a data pad formed at one end of the data line, and a drain electrode which is separated from and facing the source electrode; Data wiring, A second contact hole formed on the data line and having substantially the same outline as the semiconductor pattern, exposing the gate pad through the first contact hole, a third contact hole exposing the data pad and the drain; A second insulating film having a fourth contact hole exposing the electrode, A color filter formed in a pixel region where the gate lines and the data lines of two adjacent lines cross each other; A pixel electrode formed on the color filter and connected to the drain electrode through the fourth contact hole; Thin film transistor substrate comprising a. In claim 1, And a contact layer formed between the semiconductor layer and the data line and having substantially the same outline as the data line. In claim 1, The thin film transistor substrate further comprising an auxiliary gate pad and an auxiliary data pad covering the gate pad and the data pad, respectively. The method according to any one of claims 1, 2 and 3, And a light blocking layer formed on the passivation layer on the data line and the gate line. In claim 4, And a fifth contact hole for exposing the drain electrode through the fourth contact hole in the organic layer pattern having the light blocking property, wherein the fifth contact hole is narrower than the fourth contact hole. The method according to any one of claims 1, 2 and 3, And the second insulating film is an organic film having light blocking property. In claim 6, The thin film transistor substrate of claim 1, wherein an outline of the first insulating layer is substantially the same as the semiconductor pattern. In claim 7, The thin film transistor substrate of claim 1, wherein a minimum distance between two adjacent semiconductor patterns under the data line is 1 μm or more. Insulation board, A gate line formed on the insulating substrate and including a gate line extending in a horizontal direction, a gate electrode which is a part of the gate line, and a gate pad connected to one end of the gate line; A first insulating film formed on the gate wiring and having a first contact hole for exposing the gate pad, A semiconductor pattern formed in the longitudinal direction on the first insulating film, A data line extending in a longitudinal direction, a source electrode which is a part of the data line, a data pad formed at one end of the data line, and a drain electrode separately separated from the source electrode and formed on the semiconductor pattern; A data line formed to have substantially the same outline as the semiconductor pattern except between the source electrode and the drain electrode; A second insulating film formed on the data line and having a second contact hole exposing the first contact hole, a third contact hole exposing the data pad, and a fourth contact hole exposing the drain electrode; A color filter formed on the passivation layer of the pixel region where the two adjacent gate lines and the data line cross each other; A pixel electrode formed on the color filter and connected to the drain electrode through the fourth contact hole; Thin film transistor substrate comprising a. In claim 9, And a contact hole formed between the semiconductor layer and the data line and having an outline substantially the same as that of the data line. In claim 9, The thin film transistor substrate further comprising an auxiliary gate pad and an auxiliary data pad covering the gate pad and the data pad, respectively. The method according to any one of claims 9, 10 and 11, And a light blocking layer formed on the passivation layer on the data line and the gate line. In claim 12, And a fifth contact hole for exposing the drain electrode through the fourth contact hole in the organic layer pattern having the light blocking property, wherein the fifth contact hole is narrower than the fourth contact hole. The method according to any one of claims 9, 10 and 11, And the second insulating film is an organic film having light blocking property. Forming a gate line including a gate line extending in a horizontal direction on the insulating substrate, a gate electrode which is a part of the gate line, and a gate pad connected to one end of the gate line; Sequentially depositing a first insulating film, a semiconductor layer, and a metal layer on the gate wiring; Patterning the metal layer to form a data line including a data line extending in a vertical direction, a source electrode which is a part of the data line, a data pad formed at one end of the data line, and a drain electrode which is separated from and facing the source electrode; Steps, Stacking a second insulating film on the data line; Patterning the second insulating film, the semiconductor layer, and the gate insulating film together to form first to third contact holes exposing the gate pad, the data pad, and the drain electrode, respectively, and openings for exposing the first insulating film between adjacent data lines. Forming step, Forming a color filter on the first insulating film exposed through the opening; Forming a pixel electrode on the color filter; Method of manufacturing a thin film transistor substrate comprising a. The method of claim 15, And further stacking a contact layer on the semiconductor layer, and patterning the contact layer together in the patterning of the metal layer. The method of claim 16, Patterning the second insulating film, the contact layer, the semiconductor layer and the first insulating film together Stacking a photosensitive film on the second insulating film, Exposing the photosensitive film through an optical mask having three regions having different light transmittances depending on at least a position; Developing the photosensitive film; Etching the second insulating film, the contact layer, the semiconductor layer, and the first insulating film together with the photosensitive film. The method according to any one of claims 15, 16 and 17, And patterning the second insulating film, the semiconductor layer, and the first insulating film together, thereby forming an organic film pattern having light blocking properties. The method according to any one of claims 15, 16 and 17, And the second insulating film is a light-blocking organic film. Forming a gate line including a gate line extending in a horizontal direction on the insulating substrate, a gate electrode which is a part of the gate line, and a gate pad connected to one end of the gate line; Sequentially stacking a first insulating film, a semiconductor layer, and a metal layer on the gate wiring; And patterning the metal layer and the semiconductor layer together to extend in the longitudinal direction, a source electrode which is a part of the data line, a data pad formed at one end of the data line, and a drain electrode which is separated from the source electrode. Forming a data line and removing a semiconductor layer between the data lines except for a channel portion between the source electrode and the drain electrode; Forming a second insulating layer having first to third contact holes exposing the gate pad, the data pad, and the drain electrode, respectively, on the data line; Forming a color filter in an area between the data lines; Forming a pixel electrode connected to the drain electrode through the third contact hole on the color filter; Method of manufacturing a thin film transistor substrate comprising a. The method of claim 20, Further depositing a contact layer on the semiconductor layer, and patterning the contact layer together in the patterning of the metal layer and the semiconductor layer to form a contact layer pattern having substantially the same outline as the data line. Method for the manufacture of the jig board. The method of claim 21, Patterning the metal layer, the contact layer and the semiconductor layer together Stacking a photoresist on the metal layer; Exposing the photosensitive film through an optical mask having three regions having different light transmittances depending on at least a position; Developing the photosensitive film; Etching the metal layer, the contact layer, and the semiconductor layer together with the photosensitive film. 23. The method of any of claims 20, 21 and 22, And patterning the metal layer and the semiconductor layer together, thereby forming an organic film pattern having light blocking properties. 23. The method of any of claims 20, 21 and 22, And the second insulating film is an organic film having light blocking property. Forming a gate line including a gate line extending in a horizontal direction on the insulating substrate, a gate electrode which is a part of the gate line, and a gate pad connected to one end of the gate line; Sequentially stacking a first insulating film, a semiconductor layer, and a metal layer on the gate wiring; Patterning the metal layer to form a data line including a data line extending in a vertical direction, a source electrode which is a part of the data line, a data pad formed at one end of the data line, and a drain electrode which is separated from and facing the source electrode; Steps, Stacking a second insulating film on the data line; Patterning the second insulating film, the semiconductor layer, and the gate insulating film together to form first to third contact holes exposing the gate pad, the data pad, and the drain electrode, respectively, and exposing the insulating substrate and the gate wiring between adjacent data lines. Forming an opening, Forming a color filter on the insulating substrate and the gate wiring exposed through the opening; Forming a pixel electrode on the color filter; Method of manufacturing a thin film transistor substrate comprising a. The method of claim 25, And further depositing a contact layer on the semiconductor layer, and patterning the contact layer together in the patterning of the metal layer. The method of claim 25 or 26, And the second insulating film is an organic film having light blocking property.

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