KR100560975B1 - Thin film transistor substrate for liquid crystal display and manufacturing method thereof - Google Patents

Abstract

First, a gate wiring including a gate line, a gate electrode, and a gate pad and an electrode for a storage capacitor are formed on an insulating substrate. Subsequently, a gate insulating film, a semiconductor layer, and an etching blocking insulating film made of silicon nitride are stacked, and a photoresist pattern having at least three different thicknesses is formed by a photolithography process using a second mask, and then patterned with an etching mask to cover the gate wiring. In addition, a semiconductor pattern having a contact hole exposing a portion of the gate pad and a gate insulating layer pattern are formed, and an etch stop layer is formed on the gate electrode. In this case, a process using the photosensitive film for forming the etch stop layer as the photosensitive insulating insulating film may be omitted. Subsequently, a resistive contact layer made of silicide is formed on the semiconductor layer pattern, which is not covered by the etch stop layer, and a conductive film made of ITO or IZO, a conductor layer for data wiring, and a protective film are successively stacked, and then a third mask is used for a photo process. A photoresist pattern having at least three portions having different thicknesses is formed and used as an etching mask to form a resistive contact layer pattern, a data line, a conductive layer pattern including a pixel electrode, and a protective layer pattern. Here again, the process of forming a protective film by the photosensitive insulating film and using a photosensitive film can be skipped. Next, when the semiconductor layer remains on the gate line and the storage capacitor electrode, it is preferable to remove the semiconductor layer not covered by the conductive film pattern and the ohmic contact layer thereon in order to prevent leakage current.

Mask, photoresist, transmittance, exposure machine, resolution

Description

Thin film transistor substrate for liquid crystal display device and manufacturing method therefor {THIN FILM TRANSISTOR SUBSTRATE FOR LIQUID CRYSTAL DISPLAY AND MANUFACTURING METHOD THEREOF}

1 is a layout view illustrating a structure of a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view of the thin film transistor substrate illustrated in FIG. 1 taken along the line II-II.

FIG. 3 is a cross-sectional view of the thin film transistor substrate illustrated in FIG. 1 taken along line III-III.

4A and 5A are layout views of a thin film transistor substrate in an intermediate process of manufacturing according to an embodiment of the present invention, and are shown in sequence according to a manufacturing sequence;

4B and 4C are cross-sectional views taken along lines IVb-IVb 'and IVc-IVc' in FIG. 4A, and

5B, 6A, 5C, and 6B are cross-sectional views taken along the lines Vb-Vb 'and Vc-Vc' in FIG. 5A, showing the next steps of FIGS. 4B and 4C;

7A and 7B are cross-sectional views taken along the lines Vb-Vb 'and Vc-Vc' in FIG. 5A, showing another embodiment of the following steps of FIGS. 4B and 4C;

8A and 8B are cross-sectional views taken along the lines II-II 'and III-III' of FIG. 1 and illustrating the following steps of FIGS. 6A and 6B.

The present invention relates to a thin film transistor substrate for a liquid crystal display device and a manufacturing method thereof.

The liquid crystal display is one of the most widely used flat panel display devices. The liquid crystal display includes two substrates on which electrodes are formed and a liquid crystal layer interposed therebetween, and rearranges the liquid crystal molecules of the liquid crystal layer by applying a voltage to the electrode. By controlling the amount of light transmitted.

Among the liquid crystal display devices, a liquid crystal display device having a thin film transistor for forming an electrode on each of two substrates and switching a voltage applied to the electrode is generally used. The thin film transistor is generally formed on one of two substrates. .

At this time, the substrate on which the thin film transistor is formed is manufactured through a photolithography process using a mask. In order to reduce the production cost, it is required to reduce the number of photolithography processes using a mask.

An object of the present invention is to simplify the method of manufacturing a thin film transistor substrate for a liquid crystal display device.

In order to achieve the above object, the present invention forms a photoresist pattern having at least three different thicknesses in one photolithography process using a mask and uses the same as an etching mask to expose the gate pad while forming an etch stop layer on the gate electrode. The data line and the pixel electrode are formed together.

More specifically, first, a conductive layer is stacked and patterned on an insulating substrate, and includes a gate line in a horizontal direction, a gate electrode that is part or branch of the gate line, and a gate pad connected to the gate line and receiving a scan signal from the outside. Form the wiring. Subsequently, the gate insulating film, the semiconductor layer, and the etch stop insulating film covering the gate wirings are sequentially stacked, and the etch stop insulating film, the semiconductor layer, and the gate insulating film are patterned by a photolithography process using a first mask to form an etch stop layer and at least an etch stop layer. The semiconductor layer pattern and the gate insulating layer pattern having a first contact hole exposing the gate pads are formed. Next, the conductive film, the data wiring conductor layer, and the protective film are sequentially stacked, and the conductive film, the data wiring conductor layer, and the protective film are patterned by a photolithography process using a second mask to extend in the longitudinal direction with the conductive film pattern including the pixel electrode. A data line defining a pixel crossing the line, a source electrode that is a part or a branch of the data line, a drain electrode located opposite the source electrode with respect to the gate electrode, and a data pad connected to the data line to receive an image signal from the outside A protective film pattern covering the data wiring and the data wiring is formed.

Here, the first and second masks have a transmittance of at least three regions, and in order to partially adjust the transmittance, a fine pattern having a transmittance of a thin film having a different transmittance or a thin film having a different thickness or an exposure device may be used.

In addition, the semiconductor layer pattern not covered by the conductive film pattern may be etched to separate the semiconductor layer patterns under the neighboring data lines.

The manufacturing method according to the present invention further includes forming an ohmic contact layer between the semiconductor layer pattern and the conductive layer pattern, wherein the ohmic contact layer may be formed of silicide or doped amorphous silicon.

In the photolithography process using the first mask, a photoresist layer may be used. In this case, a photoresist layer may be coated on the etch stop insulating layer and exposed to light to develop at least a first portion and a second portion having a first thickness thicker than the first portion. A photosensitive film pattern including a third portion having a second thickness thicker than the first thickness is formed. Next, using the photoresist pattern as an etch mask, the etch stop insulating film, the gate insulating film, and the semiconductor layer of the first portion are etched together with the second portion to complete the gate insulating film pattern and the semiconductor layer pattern, and the third portion is used as the etching mask. The etch stop layer is etched to complete the etch stop layer.

In addition, in the photolithography process using the first mask, the etch stop insulating film may be formed as a photosensitive organic insulating film. In this case, the etch stop insulating film may be exposed and developed to have at least a first portion and a first thickness thicker than the first portion. An etching barrier insulating layer pattern including a second portion and a third portion having a second thickness thicker than the first thickness is formed, and the gate insulating layer and the semiconductor layer of the first portion are etched together with the second portion by using the same as an etching mask. As a result, the gate insulating layer pattern and the semiconductor layer pattern are completed, and a third portion is left to complete the etch stop layer.

In addition, in the photolithography process using the second mask, a photoresist film is used, and the photoresist film is applied to the upper portion of the protective film, and the photoresist film is exposed and developed to have at least a first part, a second part having a first thickness thicker than the first part, and a first thickness. A photosensitive film pattern including a third portion having a thicker second thickness is formed. Using the photoresist pattern as an etch mask, the protective layer, the data wiring conductor layer and the conductive film of the first portion are etched together with the second portion to complete the conductive film pattern, and the protective layer and the conductor layer for the data wiring, using the third portion as an etching mask. Is etched to complete the data line and the passivation pattern.

In this case, the protective film may be formed of a photosensitive organic insulating film. In this case, the protective film may be exposed and developed to have at least a first part, a second part having a first thickness thicker than the first part, and a second thickness thicker than the first thickness. A sub passivation layer pattern including a third part is formed, and the conductor layer and the conductive layer for data wiring of the first part are etched together with the second part using the sub passivation pattern as an etching mask to complete the conductive layer pattern and the passivation layer pattern. The data wiring is etched by etching the conductor layer for data wiring which is not covered by three parts.

The conductive layer pattern may be formed of ITO or IZO, and the protective layer pattern and the data line may have a second contact hole that exposes the conductive layer pattern under the data pad, and the conductive layer pattern may be formed on the gate pad. It further comprises an auxiliary gate pad connected to the gate pad through the one contact hole.

Then, the liquid crystal display according to an exemplary embodiment of the present invention and a manufacturing method thereof will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention.

In the embodiment of the present invention, in order to simplify the manufacturing process, a photo process using a mask that can adjust the intensity of the light partially transmitted to form a photoresist pattern having at least three parts having different thicknesses and using it as an etching mask, The contact holes exposing the etch stop layer and the gate pad are formed together, and the data line and the pixel electrode are formed together.

In the thin film transistor substrate for a liquid crystal display device completed through such a manufacturing process, a gate wiring including a gate line and a gate electrode that is part of the gate line is formed on the insulating substrate, and a gate insulating film pattern and a semiconductor covering the gate wiring are formed on the gate wiring. A layer pattern is formed. An etch stop layer is formed on the semiconductor layer pattern of the gate electrode, and the semiconductor layer pattern on the gate electrode, the etch stop layer, and the transparent conductive layer pattern including the pixel electrode are separated into two parts around the gate electrode. Is formed. On one transparent conductive film pattern, a data line crossing the gate line and a source electrode which is a branch or part of the data line and a data pad connected to the data line are formed. A pixel electrode and a drain electrode are formed on the other transparent conductive film pattern. The protective film is formed on the above.

First, the structure of a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 to 3 are layout views illustrating a structure of a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view of the thin film transistor substrate illustrated in FIG. 1 taken along a line II-II. 3 is a cross-sectional view of the thin film transistor substrate illustrated in FIG. 1 taken along the line III-III. The structure of the thin film transistor substrate for a liquid crystal display according to this embodiment is manufactured according to the manufacturing method using the three-layer mask described later.

1 to 3, a gate wiring made of a single film or a double film of aluminum or an aluminum alloy and chromium, molybdenum or molybdenum alloy on the insulating substrate 10, and a storage capacitor electrode 28 separated from the gate wiring. ) Is formed. The gate line is connected to the gate line 22 and the end of the gate line 22 extending in the horizontal direction, and is a part of the gate pad 26 and the gate line 22 which receive a scan signal from the outside and transfer the gate signal to the gate line. And a gate electrode 24 of the thin film transistor. Here, the storage capacitor electrode 28 is used as one electrode of the storage capacitor overlapping the pixel electrode 64 formed later to form the storage capacitor.

A gate insulating layer pattern 30 made of silicon nitride (SiN _x ) is formed on the substrate 10 to cover the gate wirings 22, 24, 26, and the storage capacitor electrode 28.

The semiconductor layer patterns 42, 44, 46, and 48 are formed on the gate insulating layer pattern 30. The semiconductor layer pattern is formed on the gate pad 26 and positioned on the portion 46 and the gate electrode 24 having a contact hole 36 to expose the gate pad 26 together with the gate insulating layer pattern 30. The portion 42 in which the channel of the thin film transistor is formed, the portion 48 positioned between the pixel electrode 64 and the storage capacitor electrode 28, and the data line 82 and the storage capacitor electrode 28 formed thereafter. And four parts separated from each other by the remaining parts 44 positioned between the gate lines 22. In this case, the pixel electrode 64 may be formed to overlap the gate line 22 of the front end positioned at an upper portion thereof. In this case, the storage capacitor formed between the pixel electrode 64 and the gate line 22 of the front end overlapped with each other may be formed. The storage capacitor electrode 28 may be omitted if sufficient.

On the semiconductor layer pattern 42 of the gate electrode 24, an etch stop layer 50 made of silicon nitride or an organic insulating layer is formed in an island shape in the semiconductor layer pattern 42.

The semiconductor patterns 42, 44, 46, and 48 that are not covered by the etch stop layer 50 and the etch stop layer 50 and the substrate 10 are separated from the gate electrode 24 and are formed of ITO (transparent conductive material). Conductive film patterns 62, 64, and 66 made of indium tin oxide (IZO) or indium zinc oxide (IZO) are formed. Here, one conductive film pattern 64 is a pixel electrode formed in the pixel region, and the other transparent conductive pattern 62 extends in the vertical direction while crossing the gate line 22 and the storage capacitor electrode 28. An auxiliary data line, and the remaining conductive layer pattern 66 is an auxiliary gate pad formed on the gate pad 26 and connected to the gate pad 26 through the contact hole 36.

Meanwhile, between the conductive film patterns 62, 64, 66 and the semiconductor layer patterns 42, 44, 46, and 48, the contact resistance is reduced between them, and the ohmic contact layer 72 made of a doped amorphous silicon layer or silicide is formed. 74, 76, and 78) are formed.

A portion 62 of the conductive film pattern is formed in a vertical direction and extends to the upper portion of the data line 82 and the gate electrode 24 defining the pixel by crossing the gate line 22. A data pad 88 connected to one end of the source electrode 84 and the data line 82, which is a branch, is formed. In addition, a drain electrode 86 is formed adjacent to the gate electrode 24 on a portion of the other portion 64 of the conductive film pattern.

The upper portion of the data lines 82, 84, 86, and 88 has the same shape as that of the data lines, and a protective film 90 made of silicon nitride or an organic insulating film is formed, and the protective film 90 is formed together with the data pad 88. The contact hole 98 which exposes a part of the conductive film pattern 62 is provided.

In the structure according to the exemplary embodiment of the present invention, the semiconductor layer patterns 42, 44, 46, and 48 are formed only on the gate insulating layer pattern 30 not covered by the conductive layer patterns 62 and 64.

Next, a method of manufacturing a thin film transistor substrate for a liquid crystal display device having a structure according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 to 3 and 4A to 8B.

4A and 5A are layout views of a thin film transistor substrate in an intermediate process of manufacturing according to an embodiment of the present invention, and are shown in sequence according to the manufacturing sequence. 4B and 4C are cross-sectional views taken along lines IVb-IVb 'and IVc-IVc' in FIG. 4A, and FIGS. 5B and 6A and 5C and 6B are Vb-Vb 'and Vc-Vc' in FIG. 5A. 4B and 4C are cross-sectional views taken along the line, and FIGS. 7A and 7B are views taken along the lines Vb-Vb 'and Vc-Vc' in FIG. 5A, and FIGS. 4B and 4C. FIG. 8A and FIG. 8B are cross-sectional views taken along the lines II-II 'and III-III' of FIG. 1, showing the next steps of FIGS. 6A and 6B. . 4B, 5B, 6A, 7A, and 8A are cross-sectional views of the screen display unit, and Figs. 4C, 5C, 6B, 7B, and 8B are cross-sectional views of the pad unit.

First, as shown in FIGS. 4A to 4C, a single film or a double metal film of aluminum or aluminum alloy, molybdenum or molybdenum alloy, or chromium is laminated on the insulating substrate 10 and patterned by a photo process using a first mask. A gate wiring including the gate line 22, the gate electrode 24, and the gate pad 26 in the direction and a pixel electrode formed later are formed to form a storage capacitor electrode 28 that forms a storage capacitor.

Next, as shown in FIGS. 5A, 6A, and 6B, an insulating material such as a gate insulating film 30 made of silicon nitride, a semiconductor layer 40 made of a semiconductor such as amorphous silicon, and silicon nitride is used as an etch stop layer. The semiconductor pattern having the contact hole 36 exposing a part of the gate pad 26, covering the gate wirings 22 by laminating the insulating film 50 to be used and patterning it by a photo process using a second mask. 40 and gate insulating film pattern 30 are formed, and an etch stop layer 50 is formed on gate electrode 24.

At this time, in some cases, the screen display part needs to pattern the insulating layer 50 for etching the semiconductor layer 40 in a different shape. In the pad part, the insulating layer 50 and the semiconductor layer for preventing the etching are formed in order to form the contact hole 36. 40 and the gate insulating film 30 should be patterned. To this end, a photoresist pattern having a part that is partially different in thickness and at least three parts having different thicknesses is formed, and the lower layers are etched using this as an etching mask. This will be described in detail with reference to FIGS. 5B and 5C.

First, as shown in FIGS. 5B and 5C, the positive photosensitive film 100 is coated on the etch stop insulating film 50, and then the photosensitive film 100 is exposed using the second mask 200. In this case, the second mask 200 uses different portions of light transmittance (A, B, C) in order to form the photoresist film remaining after the development to have at least three portions having different thicknesses. The second mask 200 is about 0 to 3% in the first portion A corresponding to the portion where the etch stop layer 50 is formed, and the semiconductor layer pattern 40 does not have the etch stop layer 50. 20-60%, Preferably it is about 25-40% in the 2nd part B corresponding to the other parts except the 1st and 2nd parts A and B, and the agent corresponding to the contact hole 36. Each of the three parts (C) has a transmittance of 90% or more. 5B and 5C show the thickness of the photosensitive film 100 remaining after development. At this time, the photosensitive film 100 of the portion corresponding to C may be completely removed as shown in the drawing and may be left with a fine thickness, the thickness t1 of the photosensitive film 100 of the portion corresponding to B is 2,000 ~ 5,000 kPa, preferably Preferably it is about 3,000-4,000 micrometers, and it is preferable that the thickness of the part corresponding to A is 1 micrometer or more. However, these conditions may vary depending on the etching method and the conditions for patterning the lower layers 30, 40, and 50, and may vary depending on the thicknesses of the lower layers 30, 40, and 50.

Subsequently, when dry etching is performed using photoresist patterns 100 having partially different thicknesses t1 and t2 as an etching mask, etching may be selectively performed in order according to the difference in thicknesses of the photoresist patterns 100. First, using the photoresist pattern 100 of the A and B portions as an etch mask, the etch stop insulating film 50, the semiconductor layer 40, and the gate insulating film 30 of the portion corresponding to C in the screen display part and the pad part are etched. 6A and 6B, the semiconductor layer pattern 40 and the gate insulating layer pattern 30 having the contact holes 36 exposing a portion of the substrate 10 and exposing the gate pads 26 are formed. Here, it is preferable that the photoresist film is sufficiently left in the exposure and development processes so that the photoresist film of the portion B is not completely removed even if the contact hole 36 is completely formed. Next, the photoresist film remaining in the portion B is removed by an ashing process, and the etch stop insulating film 50 is etched using the photoresist pattern 100 remaining in the portion A as an etching mask, thereby etching as shown in FIG. 6A. The blocking film 50 is formed and the photoresist film remaining on the etch stop film 50 is removed. Here, the intermediate ashing process may be omitted depending on the etching conditions and the thickness of the photoresist pattern 100.

Here, in the portion B of FIG. 5B, the thickness of the photoresist film 100 may be left as the portion A so that a portion of the insulating film 50 for blocking the etching may be left around the gate pad 26, and the pad except the contact hole 36 may be left. An etch stop insulating film 50 may be left over the entire portion.

 In the foregoing, the etch stop layer 50, the semiconductor layer pattern 40, the gate insulating layer pattern 30, and the contact hole 36 were formed using the photoresist pattern as an etch mask. 50) may be formed of a photosensitive organic insulating material capable of a photographic process. When the etch stop insulating film 50 is exposed and developed using a second mask, an etch stop insulating film pattern 50 is formed as shown in FIGS. 7A and 7B, and the etch stop insulating film pattern 50 is used as an etch mask. When the semiconductor layer 40 and the gate insulating film 30 are etched, the semiconductor layer pattern 40, the gate insulating film pattern 30, and the contact hole 36 as shown in FIGS. 6A and 6B are completed, and the etch stop is completed. The film 50 can be formed. In this way, the manufacturing process can be simplified simply by removing the formation of a photosensitive film and eliminating the step.

When the photoresist pattern having at least three portions having different thicknesses or an insulating pattern made of a photosensitive organic insulating material is formed and used as an etching mask, the etch stop layer 50 on the gate electrode 24 may be patterned even in one photolithography process. ), The gate insulating layer pattern 30 having the semiconductor layer pattern 40 and the contact hole 36 may be formed.

Subsequently, as shown in FIGS. 8A and 8B, the ohmic contact layer 70 made of silicide is formed on the upper portion of the semiconductor layer pattern 40 that is not covered by the etch stop layer 50 by stacking a metal film capable of forming silicide in combination with silicon. ) And the metal film is removed. Subsequently, a conductive film 60 made of ITO or IZO, a single layer made of molybdenum or molybdenum alloy chromium, or a conductor layer 60 for data wiring made of a multilayer made of aluminum or aluminum alloy or ITO, and a protective film made of silicon nitride ) Are successively stacked and then patterned in one photo process using a third mask. The resistive contact layer patterns 72, 74, 76, 78 and data lines 82, 84, 86, 88, conductive film patterns 62, 64, 66 including the pixel electrode 64, and the protective film pattern 90 are formed.

Here, in order to form the data wirings 82, 84, 86 and 88, the conductive film patterns 62, 64 and 66 and the protective film pattern 90 having different shapes through the photolithography process using one mask, As described above, a photoresist pattern having a different thickness is formed by using a mask having a partially different transmittance, and the lower layers may be etched using this as an etching mask. This will be described in detail with reference to FIGS. 8A and 8B.

First, as shown in FIGS. 8A and 8B, after applying the positive photoresist layer 300 on the passivation layer 90, the third mask 400 may partially adjust light transmittance similarly to the second mask. Exposing to form a photoresist pattern 300 having a partly different thickness. 8A and 8B illustrate the photoresist pattern 300 remaining after exposure and development. When the dry etching process is performed using the photoresist pattern 300 having the thicknesses D, E, and F which are partially different as the etching mask, the pattern of the thin film may be differently formed according to the order of thickness. First, the protective film 90, the data wiring conductor layer 80, and the conductive film 60 are sequentially etched in the D portion using the photoresist pattern 300 of the E and F portions as an etching mask to include a pixel electrode. The conductive film pattern including the first portion 62, the second portion 64 including the auxiliary data lines, and the auxiliary gate 66 is completed. At this time, it is preferable that the photoresist film is sufficiently left in the previous exposure development step so that the photoresist film is not completely removed at the portion corresponding to E.

At this time, when the semiconductor layer remains on the gate line 22 and the storage capacitor electrode 28 between the adjacent data lines 82, the distortion of the image signal applied to the data line 82 due to leakage current. This may occur and it is desirable to separate the semiconductor layer. To this end, the semiconductor layer 40, which is not covered by the conductive layer patterns 62, 64, and 66, and the ohmic contact layer 70 thereon are etched to form the semiconductor layer patterns 42, 44, 46 and 48 and the resistive contact layer patterns 72, 74, 76 and 78 thereon.

Next, an ashing process is performed to remove the photoresist film remaining in the portion corresponding to E, and to expose the protective film 90 and the data wiring conductor layer 80 thereunder using the photoresist pattern 300 of the F portion as an etching mask. By etching, the protective film pattern 90 having the same shape as that of the data wires 82, 84, 86, and 88 having the contact holes 98 as shown in FIGS. 1 to 3 is completed. Here, a process of completing the semiconductor layer patterns 42, 44, 46, and 48 and the ohmic contact layer patterns 72, 74, 76, and 78 thereon may be performed.

The data lines 62, 64, 66, and 68 may be formed by wet etching using an etchant.

In addition, as described above, when the data lines 62, 64, 66, and 68 are formed of a dry-etchable material such as molybdenum, aluminum, or an alloy thereof, the ashing process is not used as described above. It may be formed together with the protective film pattern 90 even in one dry etching process.

In addition, the protective film pattern 90 may not be formed in the method of manufacturing the thin film transistor substrate for a liquid crystal display according to the exemplary embodiment of the present invention. Then, a photosensitive film pattern is formed on the data layer conductor layer, and the conductive film patterns 62, 64, and 66 are completed similarly to the manufacturing method described above by using the photosensitive film pattern as an etching mask, and the data wirings 82, 84, 86, 88) can be completed.

In this case, when the protective film 90 is formed of a photosensitive organic insulating film that can be patterned by a photolithography process, the process of using the photosensitive film as in the case of forming the etch stop film 50 using the photosensitive organic insulating film is omitted. Can be simplified. In this case, a sub passivation layer pattern such as the photoresist layer pattern 300 of FIGS. 8A and 8B is formed, and the lower layers are etched using a mask to complete the conductive layer patterns 62, 64, 66 and the passivation layer pattern 90, and to form a passivation layer. The data wiring conductor layer not covered by the pattern 90 is etched to complete the data wirings 62, 64, 66, and 68.

In this case, the photoresist patterns 100 and 300 having different thicknesses are formed by using masks having different transmittances. In order to partially control the light transmittance of the masks, the fine patterns smaller than the resolution of the exposure machine used during exposure are used. Or a thin film having a different transmittance, or a thin film having the same transmittance and having a different thickness can be used.

As described above, in the present invention, the semiconductor pad pattern and the etch stop layer are formed by exposing the gate pad in one photo process using a mask that can partially control the transmittance, and the pixel electrode and the passivation layer pattern are formed while the data wiring is formed. The manufacturing cost can be reduced by manufacturing a thin film transistor substrate for a liquid crystal display device by simplifying the above. In addition, when the protective film or the etch stop layer is formed of the photosensitive organic insulating film, the step of using the photosensitive film may be omitted.

Claims (21)

Stacking and patterning a conductor layer on an insulating substrate to form a gate wiring including a horizontal gate line, a gate electrode which is a part or branch of the gate line, and a gate pad connected to the gate line to receive a scan signal from the outside; , Stacking a gate insulating film, a semiconductor layer, and an etch stop insulating film sequentially covering the gate wiring; Patterning the etch stop insulating film, the semiconductor layer, and the gate insulating film by a photolithography process using a first mask to form a first contact hole having a different size from the etch stop film and at least the etch stop film and exposing the gate pad; Forming a semiconductor layer pattern and a gate insulating layer pattern; Laminating the conductive film and the conductor layer for data wiring in sequence, Data lines defining a pixel by patterning the conductive layer and the data wiring conductor layer using a second mask to extend the conductive layer pattern including the pixel electrode in a vertical direction and intersect the gate line, and a portion of the data line. Or forming a data line including a source electrode which is a branch, a drain electrode which is opposite to the source electrode with respect to the gate electrode, and a data pad connected to a data line to receive an image signal from an external source; Method of manufacturing a thin film transistor substrate for a liquid crystal display device comprising a. In claim 1, And the first and second masks have different transmittances of at least three regions. In claim 2, A method of manufacturing a thin film transistor substrate for a liquid crystal display device, wherein the first and second masks use a fine pattern smaller than the resolution of a thin film having a different transmittance or a thin film having a different thickness or an exposure device to partially adjust the transmittance. In claim 1, And etching the semiconductor layer pattern not covered by the conductive layer pattern to separate the semiconductor layer pattern under the data line adjacent to each other. In claim 1, The method may further include forming an ohmic contact layer between the semiconductor layer pattern and the conductive layer pattern. Forming the ohmic contact layer, Stacking a metal film capable of forming silicide on the semiconductor layer; Forming a silicide on the semiconductor layer; Removing the metal film; and manufacturing a thin film transistor substrate for a liquid crystal display device. In claim 1, The method of manufacturing a thin film transistor substrate for a liquid crystal display device, wherein the semiconductor pattern and the gate insulating layer pattern are formed in the same shape in the photolithography process using the first mask. In claim 1, A method of manufacturing a thin film transistor substrate for a liquid crystal display device, the method comprising: laminating a protective film on the data wiring conductor layer. In claim 7, The method of manufacturing a thin film transistor substrate for a liquid crystal display device, wherein the data line and the passivation pattern are formed in the same shape in the photolithography process using the second mask. In claim 1, The photolithography process using the first mask uses a photosensitive film, The etching stop layer, the semiconductor layer pattern, and the gate insulating layer pattern forming step may include Applying the photoresist on the etch stop insulating layer; Exposing and developing the photosensitive film to form a photoresist pattern including at least a first part, a second part having a first thickness thicker than the first part, and a third part having a second thickness thicker than the first thickness; Etching the etch stop insulating film, the gate insulating film, and the semiconductor layer together with the second portion by using the photoresist pattern as an etch mask to complete the gate insulating film pattern and the semiconductor layer pattern; And etching the etch stop insulating layer using the third portion as an etch mask to complete the etch stop layer. In claim 1, In the photolithography process using the first mask, the etch stop insulating film is formed of a photosensitive organic insulating film, Forming the etch stop layer, the semiconductor layer pattern and the gate insulating layer pattern, An etch stop insulating film including an at least first portion, a second portion having a first thickness thicker than the first portion, and a third portion having a second thickness thicker than the first thickness Forming a pattern, The gate insulating layer and the semiconductor layer of the first portion are etched together with the second portion by using the etch stop insulating layer pattern as an etch mask to complete the gate insulating layer pattern and the semiconductor layer pattern and to form the third portion. A method of manufacturing a thin film transistor substrate for a liquid crystal display device comprising the step of completing the etch stop layer. In claim 1, The photolithography process using the second mask uses a photosensitive film, The conductive film pattern and the data wiring forming step, Coating the photosensitive film on the data wiring conductor layer; Exposing and developing the photosensitive film to form a photoresist pattern including at least a first part, a second part having a first thickness thicker than the first part, and a third part having a second thickness thicker than the first thickness; Etching the data layer conductor layer and the conductive layer of the first portion together with the second portion by using the photoresist pattern as an etching mask to complete the conductive layer pattern; And etching the data wiring conductor layer using the third portion as an etching mask to complete the data wiring. In claim 11, Forming a protective film between the data wiring conductor layer and the photosensitive film; In the step of completing the conductive film pattern, the protective film of the first portion is etched, And manufacturing the thin film transistor substrate for a liquid crystal display device using the third portion as an etching mask in the data wiring completion step. In claim 1, In the photolithography process using the second mask, a protective film pattern made of the photosensitive organic insulating layer is used as an etching mask. The protective film pattern, the data line and the conductive film pattern forming step, Exposing and developing the passivation layer to form a sub passivation pattern including at least a first portion, a second portion having a first thickness thicker than the first portion, and a third portion having a second thickness thicker than the first thickness. , The data wiring conductor layer and the conductive layer of the first portion are etched together with the second portion by using the sub protective layer pattern as an etch mask to complete the conductive layer pattern and the protective layer pattern and not cover the third portion. And etching the data wiring conductor layer to complete the data wiring. In claim 1, And the conductive film pattern is formed of ITO or IZO. In claim 1, And the data line has a second contact hole exposing the conductive layer pattern under the data pad. In claim 1, The conductive layer pattern may further include an auxiliary gate pad connected to the gate pad through the first contact hole on the gate pad. Insulation board, A gate wiring formed on the substrate and including a gate line in a horizontal direction and a gate electrode which is a branch or part of the gate line, A gate insulating film pattern covering the gate wiring; A semiconductor layer pattern formed on the gate insulating layer pattern; An ohmic contact layer pattern formed on the semiconductor layer pattern and having at least a first portion and a second portion separated from the gate electrode; A conductive layer pattern covering the resistance contact layer, the conductive layer pattern including a first portion separated from the gate electrode and a second portion including pixel electrodes of a pixel region; It is formed in the same shape as the conductive film pattern except for the pixel electrode, and is formed on the first portion of the conductive film in a vertical direction of the conductive film pattern to define the gate line and the pixel region. A data line including a source electrode formed on an upper portion of the portion and connected to the data line and a drain electrode formed on an upper portion of the second portion of the conductive layer; A protective film pattern covering the data line and formed in the same shape as the data line. Thin film transistor substrate for a liquid crystal display device comprising a. The method of claim 17, And a etch stop layer formed between the first and second portions of the ohmic contact layer pattern on the semiconductor layer pattern. The method of claim 18, And the semiconductor layer pattern is formed only at a portion where the data line and the etch stop layer and the conductive layer pattern overlap. The method of claim 17, The gate line further includes a gate pad connected to the gate line, The conductive layer pattern may further include a third portion connected to the gate pad through a first contact hole formed in the gate insulating layer pattern and the semiconductor layer pattern. The data line further includes a data pad connected to the data line. The passivation pattern and the data pad have a second contact hole exposing a first portion of the conductive layer pattern under the data pad. The method of claim 17, The conductive film pattern is a thin film transistor substrate for a liquid crystal display device made of ITO or IZO.

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