KR20000033836A - Photolithographic process for thin films and method for manufacturing tft substrate for lcd using the same - Google Patents

Abstract

PURPOSE: A method for manufacturing a TFT substrate is provided to fabricate the TFT substrate with low cost and obtain excellent step coverage over a broad range even if the deposited layers are etched in different depth. CONSTITUTION: A method for manufacturing a TFT substrate comprises forming a gate wiring(22, 24, 26) consisting of a gate line(22), a gate electrode(24) and a gate pad(26) on a substrate(10) which contains display parts and peripheral parts, forming gate insulator pattern(30) on the gate wiring(22, 24, 26), forming semiconductor pattern on the gate insulator pattern(30), forming contact layer patterns(55, 56) on the semiconductor pattern, forming a data wiring(62, 64, 65, 66) consisting of a data line(62), a source electrode(65), a drain electrode(66) and a data pad(64) on the contact layer patterns(55, 56), forming a channel protecting pattern(70) and forming pixel electrodes connected to the drain electrode(66). The gate insulator pattern(30) is transferred from photo masks(300, 410, 420). The first photo mask(300) patterning the display parts has different transmittance from the second photo mask(410, 420) patterning the peripheral parts. In addition, the fate insulator pattern(30) is formed by etching.

Description

Photolithography method of thin film and manufacturing method of thin film transistor substrate for liquid crystal display device using same

The present invention relates to a method of etching a thin film and a method of manufacturing a thin film transistor substrate for a liquid crystal display device using the same.

In general, a liquid crystal display device is composed of two substrates, and two or more kinds of electrodes for generating an electric field are formed on one or both of the substrates to display an image by adjusting a voltage applied to the electrodes.

Among the two substrates, the thin film transistor substrate for a liquid crystal display device has a basic structure of a thin film transistor formed on the substrate and a pixel electrode controlled thereby, as in the present inventors patent application No. 95-189.

As in this patent application, a thin film transistor substrate is manufactured through film formation and photolithography processes of a thin film over several layers, and photolithography recovery represents a number of manufacturing processes. Therefore, how stable a device is formed through a small number of photolithography processes is an important factor in determining the manufacturing cost, as also shown in the aforementioned No. 95-189.

However, in order to actually complete the substrate of the liquid crystal display device, wirings for transmitting an electrical signal to each thin film transistor are required, and a pad for electrically connecting each wiring to an external driving circuit is necessary. The manufacturing process should be presented. However, Patent Application No. 95-189 describes a process for manufacturing only thin film transistors.

As another prior art, A TFT Manufactured by 4 Masks Process with New Photolithography (Chang Wook Han et al., Proceedings of The 18th International Display Research Conference Asia Display 98, p. 1109-1112, 1998. 9.28-10.1) Display ”) to fabricate thin film transistors using four masks. However, there is no mention of the pad here either. On the other hand, it is common to form a storage capacitor in order to preserve the voltage applied to the pixel for a long time, and the storage capacitor is made by superposing a pixel electrode formed on the passivation layer and a storage capacitor electrode made of the same layer as the gate electrode and the gate line. However, since the storage capacitor electrode is covered with the gate insulating film, the semiconductor layer, and the protective film, and the pixel electrode is formed directly on the substrate without the lower gate insulating film, in order to overlap the pixel electrode with the storage capacitor electrode, the pixel electrode is directly placed on the substrate. Since it must be placed directly on the three-layer film made of the gate insulating film, the semiconductor layer, and the protective film from above, there is a fear that the step becomes severe and a disconnection may occur.

On the other hand, as shown in No. 95-189, in the conventional general photolithography process, the photoresist film is divided into two parts, that is, the part irradiated to light and the part that is not exposed, and then developed. As a result, the etching depth is also constant. However, in an "Asian display", a photosensitive film is exposed by using a mask having a grid in only a specific part, thereby reducing the amount of light emitted to the grid part to form a photosensitive film pattern having a part having a thickness smaller than that of other parts. Techniques are described. When etching in this state, the etching depth of the lower photoresist layer is changed.

As described above, the conventional etching process used in the case of No. 95-189 has a problem in that the etching depth cannot be adjusted in one photolithography process, and in the case of an Asian display, the area that can be treated as a grid mask is limited. Even if the region cannot be processed or can be diarrhea, it is difficult to process to have a uniform etching depth as a whole.

In addition, U.S. Patent Nos. 4,231,811, 5,618,643, 4,415,262, and Japanese Patent Laid-Open No. 61-181130 are also exposed by using a grid optical mask or by varying the transmittance by adjusting the thickness of the photomask. Ion implantation and thin film etching methods using the thickness difference of the formed photosensitive film are known, but these also have the same problem.

An object of the present invention is to propose a new photolithography method for thin films.

Another technical problem to be achieved by the present invention is to simplify the manufacturing process of the thin film transistor substrate for a liquid crystal display device, thereby lowering the manufacturing cost and increasing the yield.

Another technical problem to be achieved by the present invention is to etch a wide area to different depths while having a uniform etch depth for one etch depth.

1 is a diagram illustrating regions of a substrate for manufacturing a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 2 is a layout view schematically illustrating elements and wirings formed in one thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a layout view of a thin film transistor substrate for a liquid crystal display according to a first exemplary embodiment of the present invention, and is an enlarged view of one pixel and pads in FIG. 2.

4 and 5 are cross-sectional views of the thin film transistor substrate shown in FIG. 3 taken along lines IV-IV 'and V-V'.

6A is a layout view of a thin film transistor substrate at a first stage of manufacture in accordance with an embodiment of the invention,

6B and 6C are cross-sectional views taken along the lines IVb-IVb 'and IVc-IVc' in FIG. 4A, respectively.

FIG. 7A is a layout view of a thin film transistor substrate in the following steps of FIGS. 6A to 6C;

7B and 7C are cross-sectional views taken along the lines 'b-'b' and 'c-'c' in FIG. 7A, respectively.

FIG. 8A is a layout view of a thin film transistor substrate in the following steps of FIGS. 7A to 7C;

8B and 8C are cross-sectional views taken along the lines 'b-'b' and 'c-'c' in FIG. 8A, respectively.

9A and 9B, 10A and 10B and 11 are cross-sectional views showing the structure of the photomask used in the steps of FIGS. 8A to 8C, respectively.

12A and 12B are cross-sectional views taken along the lines 'b-'b' and 'c-'c' in FIG. 8A, respectively, and are cross-sectional views at the next steps of FIGS. 8B and 8C;

13A and 13B are cross-sectional views taken along the lines 'b-'b' and 'c-'c' in FIG. 8A, respectively, and are cross-sectional views taken in the next steps of FIGS. 12A and 12A.

In order to solve the above problem, the present invention patterns the contact window exposing the gate pad together with at least one other thin film.

According to the present invention, a gate line including a gate line and a gate electrode of the screen display portion and a gate pad of the peripheral portion is formed on a substrate including the screen display portion and the peripheral portion, and a gate insulating film pattern is formed thereon. After forming a semiconductor layer pattern on the gate insulating film pattern, and forming a contact layer pattern thereon, a data line including a data line, a source and a drain electrode, and a data pad of the peripheral portion of the screen display is formed thereon. A channel passivation layer pattern is formed and a pixel electrode connected to the drain electrode is formed. Here, in the step of forming the gate insulating film pattern, the first photomask and the first photomask for patterning the screen display part are different from each other, and the second photomask is exposed using the second photomask for patterning the peripheral part. Together with at least one, it is formed in one etching process.

The photosensitive film used in this process is preferably a positive photosensitive film, and the transmittance of the first photomask is preferably 20% to 60% of the transmittance of the second photomask.

Each of the first and second photomasks includes a substrate and an opaque pattern layer formed on the substrate and a pellicle formed on the substrate not covered with at least the pattern layer, wherein the difference in transmittance between the first and second photomasks is It can be adjusted by adjusting the transmittance of the pellicle of the first and second photomask.

The first and second photomasks form one mask, and the mask may form two pattern layers having different heights to give a difference in transmittance. In addition, the transmittance difference can be adjusted by forming a slit or a lattice-like fine pattern having a size equal to or less than the resolution of the light source used for exposure.

In the photolithography method of the thin film according to the present invention, at least one thin film is formed on a substrate including at least two zones, and a photosensitive film is coated on the thin film. After each of the two zones is exposed using at least two or more photomasks including pellicles having different transmittances, the photoresist is developed to form photoresist patterns having different heights according to portions. Finally, a single etching is performed on the photosensitive film and the thin film to form a thin film pattern.

At this time, the etching may use a dry etching, the photosensitive film is preferably a positive photosensitive film.

The photolithography method may be used to form the thin film transistor and the pad of the liquid crystal display.

Specifically, a gate wiring including a gate line and a gate electrode of the screen display portion and a gate pad of the peripheral portion is formed on a substrate including the screen display portion and the peripheral portion, and a gate insulating film, a semiconductor layer, a contact layer, and a conductor layer are formed on the gate wiring. Is deposited continuously. The conductor layer and the contact layer are photo-etched to form a data line including a data line of the screen display unit, a source and drain electrode, and a data pad of the peripheral portion, and a contact layer pattern thereunder, and a protective insulating layer is deposited thereon.

The photoresist is coated on the protective insulating layer, and the photoresist is exposed using a first photomask for patterning the screen display part and a second photomask for forming a peripheral portion with a transmittance different from the first mask. A photosensitive film pattern is formed. A first process of patterning the protective insulating layer and the semiconductor layer under the patterned portion of the screen display unit through a single etching process to form a protective layer pattern and a semiconductor layer pattern, and at the same time patterning the protective insulating layer, semiconductor layer and the gate insulating layer in the peripheral portion to expose the gate pad Form a contact window. Finally, a pixel electrode electrically connected to the drain electrode is formed.

In this case, a second contact window exposing the data pad by removing the protective insulating layer on the data pad may be simultaneously formed at the time of forming the first contact window.

In addition, when forming the pixel electrode, an auxiliary gate pad and an auxiliary data pad connected to the gate pad and the data pad may be formed through the first and second contact windows, respectively.

Then, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention.

In order to achieve the above object, the present invention is to simultaneously pattern the contact window exposing the gate pad with one or more thin films, but patterning only another thin film on the screen display part, leaving the gate insulating film and completely removing the gate insulating film on the gate pad part. do.

First, the structure of a thin film transistor substrate according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 to 5.

As shown in FIG. 1, several panel regions for a liquid crystal display are simultaneously formed on one insulating substrate. For example, as shown in FIG. 1, four liquid crystal display panel regions 110, 120, 130, and 140 are formed in one glass substrate 1, and the panel region is a thin film transistor panel. Reference numerals 110, 120, 130, and 140 include screen displays 111, 121, 131, and 141 made up of a plurality of pixels, and peripheral parts 112, 122, 132, and 142. Thin film transistors, wirings, and pixel electrodes are repeatedly arranged in the form of a matrix in the screen display units 111, 121, 131, and 141, and elements connected to driving elements in the peripheral portions 112, 122, 132, and 142. That is, pads and other static electricity protection circuits are disposed.

However, when forming such a liquid crystal display device, a stepper exposure device is usually used, and when the exposure device is used, the screen display parts 111, 121, 131, and 141 and the peripheral parts 112, 122, 132, and 142 are divided into various zones. The photosensitive film coated on the thin film is exposed using the same mask or another photomask for each zone, and after exposure, the entire substrate is developed to form a photosensitive film pattern, and then a specific thin film pattern is formed by etching the lower thin film. By repeatedly forming such a thin film pattern, a thin film transistor substrate for a liquid crystal display device is completed.

FIG. 2 is a layout view schematically illustrating an arrangement of a thin film transistor substrate for a liquid crystal display device formed in one panel region in FIG. 1.

As shown in FIG. 2, the screen display unit surrounded by the line 1 includes a plurality of thin film transistors 3, a pixel electrode 82, a gate line 22, and a data line (electrically connected to each of the thin film transistors 3). A wiring including 62) is formed. A gate pad 24 connected to the gate line 22 and a data pad 64 connected to the data line 62 are disposed at the periphery of the outside of the screen display, and the gate line 22 is disposed to prevent device destruction due to electrostatic discharge. Gate line shorting bar 4 and data line shorting band 5 for electrically connecting the data line 62 and the data line 62 to an equipotential, respectively. The line short circuit board 5 is electrically connected via the short circuit board connection part 6. These short-circuit bands 4 and 5 are later removed, and the line cutting the substrate when removing them is denoted by reference numeral 2. Reference numeral 7, which is not explained, is drilled through the insulating film to connect the shorting line connecting portion 6 between the gate line shorting band 4 and the data line shorting band 5 and the insulating film (not shown) as a contact window. have.

3 to 5 are enlarged views of thin film transistors, pixel electrodes, wirings, and peripheral pads of the screen display unit of FIG. 3, FIG. 3 is a layout view, and FIGS. 4 and 5 are lines IV-IV ′ of FIG. 3. A cross-sectional view taken along the line VV '.

First, a gate made of a metal or a conductor such as aluminum (Al) or aluminum alloy (Al alloy), molybdenum (Mo) or molybdenum-tungsten (MoW) alloy, chromium (Cr), tantalum (Ta) or the like on the insulating substrate 10. Wiring is formed. The gate wiring is connected to the scan signal line or the gate line 22 extending in the horizontal direction and the gate line 22 and the gate pad 24 and the gate which receive the scan signal from the outside and transmit the scan signal to the gate line 22. A gate electrode 26 of the thin film transistor that is part of the line 22.

The gate wirings 22, 24, and 26 may be formed in a single layer, but may also be formed in a double layer or a triple layer. In the case of forming more than two layers, it is preferable that one layer is formed of a material having a low resistance and the other layer is formed of a material having good contact properties with other materials, and a double layer of Cr / Al (or Al alloy) or Al / Mo Bilayers are an example.

A gate insulating film 30 made of silicon nitride (SiN _x ) is formed on the gate wirings 22, 24, and 26 to cover the gate wirings 22, 24, and 26.

Semiconductor patterns 42 and 48 made of semiconductors such as hydrogenated amorphous silicon are formed on the gate insulating layer 30, and high concentrations of n-type impurities such as phosphorus (P) are formed on the semiconductor patterns 42 and 48. An ohmic contact layer pattern or an intermediate layer pattern 55, 56, 58 made of amorphous silicon doped with is formed.

On the contact layer patterns 55, 56, and 58, a data line made of a conductive material such as Mo or MoW alloy, Cr, Al or Al alloy, and Ta is formed. The data line is a thin film transistor which is a branch of the data line 62 formed in the vertical direction, the data pad 64 connected to one end of the data line 62 to receive an image signal from the outside, and the data line 62. A drain electrode of the thin film transistor including a data line portion formed of the source electrode 65 of the thin film transistor, and separated from the data line portions 62, 64, and 65 and positioned opposite to the source electrode 65 with respect to the gate electrode 26. Also included is a conductor pattern 68 for a storage capacitor which is positioned over the 66 and the gate line 22. The conductive pattern 68 for the storage capacitor is connected to the pixel electrode 82 to be described later to form a storage capacitor. However, the conductive capacitor pattern 68 for the storage capacitor may not be formed if the storage capacitor of sufficient size can be obtained only by the superposition of the pixel electrode 82 and the gate line 22.

The data lines 62, 64, 65, 66, and 68 may be formed in a single layer like the gate lines 22, 24, and 26, but may be formed in a double layer or a triple layer. Of course, when forming more than two layers, it is preferable that one layer is made of a material having a low resistance and the other layer is made of a material having good contact properties with other materials.

The contact layer patterns 55, 56, and 58 serve to lower the contact resistance between the semiconductor patterns 42 and 48 below and the data lines 62, 64, 65, 66, and 68 above them. It has exactly the same form as (62, 64, 65, 66, 68). That is, the data line part intermediate layer pattern 55 is the same as the data line parts 62, 64 and 65, the drain electrode intermediate layer pattern 56 is the same as the drain electrode 66, and the storage capacitor intermediate layer pattern 58 is It is the same as the conductor pattern 68 for holding capacitors.

On the other hand, the semiconductor patterns 42 and 48 have a shape similar to that of the data lines 62, 64, 65, 66, and 68 and the contact layer patterns 55, 56, and 57. Specifically, the semiconductor capacitor 48 for the storage capacitor has the same shape as the conductor pattern 68 for the storage capacitor and the contact layer pattern 58 for the storage capacitor, but the semiconductor pattern 42 for the thin film transistor has data wiring and contact. It is different from the rest of the layer pattern. That is, the data line parts 62, 64, 65, in particular, the source electrode 65 and the drain electrode 66 are separated from the channel portion C of the thin film transistor, and the contact layer pattern for the data line intermediate layer 55 and the drain electrode is separated. Although 56 is also separated, the semiconductor pattern 42 for thin film transistors is not disconnected here and is connected to generate a channel of the thin film transistor. On the other hand, the semiconductor pattern 42 also extends to the periphery and is formed over the entire periphery.

The data line portions 62, 64, and 65, the drain electrode 66, and the semiconductor pattern 42 are covered by the passivation layer 70, and the passivation layer 70 exposes a contact window exposing the drain electrode 66 and the data pad 64. Has (71, 73). The passivation film 70 also has a contact window 72 exposing the gate pad 24 together with the gate insulating film 30 and the semiconductor pattern 42, and a portion of the gate line 22 overlapping the data line 62. Except for the rest is not covered. The passivation layer 70 may be formed of an organic insulating material such as silicon nitride or acrylic, and may cover and protect at least a channel portion of the semiconductor pattern 42 positioned between the source electrode 65 and the drain electrode 66.

The pixel electrode 82 is formed on the gate insulating film 30 in the region surrounded by the gate line 22 and the data line 62. The pixel electrode 82 is physically and electrically connected to the drain electrode 66 through the contact window 71 to receive an image signal from the thin film transistor to generate an electric field together with the electrode of the upper plate, and to form an indium tin oxide (ITO). Made of transparent conductive material The pixel electrode 82 also extends over the conductor pattern 68 for the storage capacitor and is physically and electrically connected so that the conductor pattern 68 for the storage capacitor and the gate line 22 and the storage capacitor thereunder are provided. To achieve. On the other hand, an auxiliary gate pad 84 and an auxiliary data pad 86 connected to the gate pad 24 and the data pad 64 through the contact windows 72 and 73, respectively, are formed. , 64) and to protect the pads and the adhesion of the external circuit device, it is not essential, and their application is optional.

Although transparent ITO has been used as an example of the material of the pixel electrode 82, an opaque conductive material may be used for the reflective liquid crystal display device.

Next, a method of manufacturing a liquid crystal display substrate according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 6A to 13B and FIGS. 3 to 5.

First, as illustrated in FIGS. 6A to 6C, a conductive layer such as a metal is deposited to a thickness of 1,000 kPa to 3,000 kPa by a sputtering method, and first, dry or wet etch using a mask to form a gate on the substrate 10. A gate wiring including the line 22, the gate pad 24, and the gate electrode 26 is formed.

Next, as shown in FIGS. 7A and 7B, the gate insulating film 30, the semiconductor layer 40, and the intermediate layer 50 are respectively 1,500 kV to 5,000 kV, 500 kV to 1,500 kV, and 300 kV using chemical vapor deposition. To 600 kPa in thickness, and then the conductive layer 60 such as metal is deposited to a thickness of 1,500 kPa to 3,000 kPa by a method such as sputtering. Subsequently, the conductor layer 60 and the intermediate layer 50 below are patterned using a second mask to form data line portions such as data lines 62, data pads 64, and source electrodes 65 and lower data line portions. The intermediate layer pattern 55, the drain electrode 66, the conductor pattern 56 for drain electrodes in the lower part, the conductor pattern 68 for sustain capacitors, and the intermediate layer pattern 58 for sustain capacitors in the lower part are formed.

As shown in FIGS. 8A, 13A, and 13C, silicon nitride is deposited by CVD or spin-coated an organic insulating material to form a protective film 70 having a thickness of 3,000 Å or more, and thereafter, using a third mask, the protective film 70. ) And the semiconductor layer 40 and the gate insulating film 30 are patterned to form a pattern thereof including the contact windows 71, 72, and 73. At this time, the peripheral portion P removes the passivation layer 70, the semiconductor layer 40, and the gate insulating layer 30 on the gate pad 24 (also removes the passivation layer 70 on the data pad 64). In (D), only the protective film 70 and the semiconductor layer 40 are removed (the protective film 70 on the drain electrode 66 is also removed). The semiconductor layer pattern must be formed so that a channel is formed only in a necessary portion. To this end, photoresist patterns having different thicknesses are formed according to portions, and dry etching of lower layers is performed using the photoresist layer as an etching mask, which will be described in detail with reference to FIGS. 8B to 13C.

First, a photoresist film PR, preferably a positive photoresist film, is applied on the protective film 70 to a thickness of 5,000 kPa to 30,000 kPa, and then exposed through the third masks 300, 410, and 420. The photosensitive film PR after exposure is different from the screen display portion D and the peripheral portion P, as shown in FIGS. 8A and 8B. That is, the portion C of the photosensitive film PR of the screen display unit D that is exposed to light reacts with light only to a certain depth from the surface to decompose the polymer, and the polymer remains under the periphery P. Unlike the photoresist film PR, the portion B exposed to light is in a state in which the polymer is decomposed in response to light. Here, portions C and B exposed to light in the screen display unit D or the peripheral portion P are portions where the protective film 70 is to be removed.

To this end, a method of changing the structure of the mask 300 used for the screen display unit D and the masks 410 and 420 used for the peripheral portion P may be used. Here, three methods are presented.

As shown in FIGS. 9A and 9B, the masks 300 and 400 are typically opaque pattern layers 320 and 420 consisting of the substrates 310 and 410 and chromium thereon, and the pattern layers 320 and 420. ) And the pellicles 330 and 430 covering the exposed substrates 310 and 410, and the light transmittance of the pellicle 330 of the mask 300 used for the screen display unit D is the peripheral portion P. FIG. ) Is lower than the light transmittance of the pellicle 430 of the mask 400. The transmittance of the pellicle 330 is preferably in the range of 10% to 80%, preferably 20% to 60% of the transmittance of the pellicle 430.

Next, as shown in FIGS. 10A and 10B, the mask 300 of the screen display unit D has a chromium layer 350 having a thickness of about 100 kPa to 300 kPa over the entire surface to lower the transmittance, The mask 400 of P) does not leave such a chromium layer. In this case, the pellicle 340 of the mask 300 used in the screen display unit D may have the same transmittance as the pellicle 430 of the peripheral portion P. FIG.

Of course, the above two methods can be used in combination.

In the above two examples, it is applicable to the split exposure using a stepper, and is possible because the screen display unit D and the peripheral portion P are exposed using different masks. In the case of the divided exposure in this manner, the thickness can be adjusted by changing the exposure time of the screen display unit D and the peripheral portion P.

However, the screen display unit D and the periphery unit P may be exposed using a single mask without dividing the exposure. In this case, a structure of a mask that can be applied will be described in detail with reference to FIG. 11.

As shown in FIG. 11, the transmittance adjusting film 550 is formed on the substrate 510 of the mask 500, and the pattern layer 520 is formed on the transmittance adjusting film 550. The transmittance adjusting film 550 is formed not only under the pattern layer 520 but also over the entire surface in the screen display unit D, but is formed only under the pattern layer 550 in the peripheral portion P. As a result, two or more patterns having different heights are formed on the substrate 510.

Of course, the periphery portion P may also have a transmittance adjusting film. In this case, the transmittance of the transmittance adjusting film of the peripheral portion P should have a transmittance higher than that of the transmittance adjusting film 550 of the screen display portion P.

When manufacturing the photomask 500 having the transmittance control film 550, first, a transmittance control film 550 and a pattern layer 520 having an etching ratio different from that of the transmittance control film 550 are formed on the substrate 500. Laminate in succession. After the photoresist (not shown) is applied, exposed and developed over the entire surface, the pattern layer 520 is etched using the photoresist as an etch mask. After removing the remaining photoresist film, a new photoresist pattern (not shown) for exposing the transmittance control film at a position corresponding to the contact window of the peripheral portion P is formed again, and then the transmittance control film 550 is etched using this as an etching mask. The optical mask 500 is completed.

In addition to the above method, the transmittance may be adjusted by using a mask having a slit or a lattice-like fine pattern having a size smaller than the resolution of the light source.

However, a portion of the photoresist film PR having a high reflectance metal layer, that is, the gate wirings 22, 24, 26 or the data wirings 62, 64, 65, 66, 68, is different during exposure due to the reflected light. The amount of light may be higher than that of the part. In order to prevent this, a layer may be used to block reflected light from the bottom or a colored photoresist film PR may be used.

After exposing the photoresist film PR in this manner and developing it, the photoresist pattern PR as shown in FIGS. 12A and 12B is formed. That is, a photosensitive film is not formed on a portion of the gate pad 24, the data pad 64, and the drain electrode 66, and all peripheral parts P except the gate pad 24 and the data pad 64 and the screen display unit ( In D), a thick photoresist film A is formed on the data lines 62, 64, 65 and the drain electrode 66 and the semiconductor layer 40 between the two, and a thin photoresist film is formed on the other part of the screen display part D. (B) is formed.

At this time, the thickness of the thin portion of the photoresist film PR may be about 1/4 to 1/7 level of the initial thickness, that is, 350 to 10,000 GPa, more preferably 1,000 to 6,000 GPa. For example, the initial thickness of the photosensitive film PR may be 25,000 kPa to 30,000 kPa, and the transmittance of the screen display unit D may be 30% so that the thickness of the thin photosensitive film may be 3,000 kPa to 5,000 kPa. However, since the thickness to be left must be determined according to the dry etching process conditions, the thickness of the pellicle of the mask, the residual chromium layer, or the transmittance or exposure time of the transmittance control film must be adjusted according to the process conditions.

Such a thin photosensitive film may be formed through reflow after exposing and developing the photosensitive film in a conventional manner.

Subsequently, etching is performed on the photoresist pattern PR and the lower layers thereof, that is, the passivation layer 70, the semiconductor layer 40, and the gate insulating layer 30 by a dry etching method.

At this time, as mentioned above, part A of the photoresist pattern PR should remain without being completely removed, and the protective film 70, the semiconductor layer 40, and the gate insulating film 30 under the B part should be removed, and C Under the portion, only the passivation layer 70 and the semiconductor layer 40 may be removed, and the gate insulating layer 30 should not be removed.

To this end, it is preferable to use a dry etching method capable of simultaneously etching the photoresist pattern PR and the films below it. That is, using the dry etching method, as shown in FIGS. 13A and 13B, the thin film is formed in three layers and the C portion of the protective film 70, the semiconductor layer 40, and the gate insulating film 30 under the portion B having no photosensitive film. The three layers of the photosensitive film, the protective film 70 and the semiconductor layer 40 can be simultaneously etched. However, the conductive layer 60 is not removed from the drain electrode 66 portion of the screen display unit D, the data pad 64 portion of the peripheral portion P, and the portion where the conductive capacitor conductive pattern 68 is to be formed. Conditions for etching selectivity with respect to the conductor layer 60 should be taken. In this case, the portion A of the photoresist pattern PR may be etched to a certain thickness.

Accordingly, only one passivation layer 70 and the semiconductor layer 40 are removed from the screen display unit D by using a single mask process and a dry etching method to form the contact window 71 and the semiconductor patterns 42 and 48. In P), all of the passivation layer 70, the semiconductor layer 40, and the gate insulating layer 30 may be removed to form the contact windows 72 and 73.

Finally, the remaining photoresist pattern of the A portion is removed, and as illustrated in FIGS. 3 to 5, an ITO layer having a thickness of 400 μs to 500 μs is deposited and etched using a fourth mask to etch the pixel electrode 82. The auxiliary gate pad 84 and the auxiliary data pad 86 are formed.

As described above, in the present exemplary embodiment, the contact window 72 exposing the gate pad 24 is formed by using a mask together with the passivation pattern 70 and the semiconductor patterns 42 and 48. 72 may also be formed together when patterning other films, which are within the scope naturally conceivable to one skilled in the art. In particular, the present invention is a particularly effective method for patterning a thin film etched by a dry etching method.

In addition, in the present embodiment, a case where the pixel electrode of a wide surface shape is present is illustrated, but the pixel electrode may be formed in a line shape, and the common electrode for driving the liquid crystal molecules together with the pixel electrode is formed on the same substrate as the pixel electrode. It may be formed.

As described above, the present invention reduces the manufacturing process number of the thin film transistor substrate for a liquid crystal display device through a new photolithography method of the thin film, and simplifies the process to lower the manufacturing cost and increase the yield. In addition, it is possible to etch a large area to different depths while having a uniform etching depth for one etching depth.

Claims (13)

Forming a gate line including a gate line and a gate electrode of the screen display unit and a gate pad of the peripheral unit on a substrate including a screen display unit and a peripheral unit; Forming a gate insulating layer pattern on the gate wiring; Forming a semiconductor layer pattern on the gate insulating layer pattern; Forming a contact layer pattern on the semiconductor layer pattern, Forming a data line on the contact layer pattern, the data line including a data line, a source and a drain electrode, and a data pad of the peripheral part; Forming a channel passivation pattern, and Forming a pixel electrode connected to the drain electrode Including; In the gate insulating film pattern forming step, a first photomask for patterning the screen display unit and a first photomask are different from each other in transmittance, and are exposed using a second photomask for patterning the peripheral portion. The gate insulating layer pattern may be formed in at least one of the semiconductor layer pattern, the contact layer pattern, the data line, the channel passivation pattern, and the pixel electrode in one etching process. . In claim 1, And the gate insulating film pattern is formed using a positive photosensitive film. In claim 2, The transmittance of the first photomask is 20% to 60% of the transmittance of the second photomask. In claim 1, The first and second photomasks each include a substrate, an opaque pattern layer formed on the substrate, and a pellicle formed on the substrate not covered with at least the pattern layer, wherein the first and second photomasks The transmittance difference of is controlled by controlling the transmittance of the pellicle of the first and second photomasks. In claim 1, The first and second photomasks form a mask, and the mask includes a substrate, a first pattern layer formed on the substrate, and a second pattern layer formed on the substrate and having a different height from the first pattern layer. And a difference in transmittance between the first and second photomasks due to a height difference between the first and second pattern layers. In claim 1, The method of manufacturing a thin film transistor substrate for a liquid crystal display device, wherein the difference in transmittance between the first and second photomasks is controlled by forming a slit or a lattice-like fine pattern having a size equal to or less than the resolution of the light source used for the exposure. Forming at least one thin film on a substrate comprising at least two zones, Applying a photoresist film on the thin film, Exposing each of the zones using at least two photomasks containing pellicles having different transmittances, Developing the photoresist to form a photoresist pattern having different heights according to portions; Performing a single etching on the photoresist and the thin film Photo etching method of a thin film comprising a. In claim 7, The etching step is a photographic etching method of a thin film using dry etching. The method of claim 8, wherein the photoresist is a positive photoresist. A method of manufacturing a liquid crystal display device using the photolithography method of claim 7 to form a thin film transistor and a pad. Forming a gate line including a gate line and a gate electrode of the screen display unit and a gate pad of the peripheral unit on a substrate including a screen display unit and a peripheral unit; Continuously depositing a gate insulating film, a semiconductor layer, a contact layer, and a conductor layer on the gate wiring; Photo-etching the conductor layer and the contact layer to form a data line including a data line, a source and a drain electrode of the screen display unit, and a data pad of the periphery, and a contact layer pattern thereunder; Depositing a protective insulating film, Applying a photosensitive film on the protective insulating film, Exposing the photosensitive film using a first photomask for patterning the screen display unit and a second photomask having a transmittance different from that of the first mask and forming the peripheral portion; Developing the photoresist to form a photoresist pattern having a different thickness; Patterning the protective insulating film and the lower semiconductor layer of the screen display part through a single etching process to form a protective film pattern and a semiconductor layer pattern, and simultaneously patterning the protective insulating film, the semiconductor layer and the gate insulating film of the peripheral part. A patterning step of forming a first contact window exposing the gate pad, Forming a pixel electrode electrically connected to the drain electrode Method of manufacturing a thin film transistor substrate for a liquid crystal display device comprising a. In claim 11, And removing the protective insulating layer on the data pad to form a second contact window exposing the data pad in the patterning step. In claim 12, And forming an auxiliary gate pad and an auxiliary data pad connected to the gate pad and the data pad, respectively, through the first and second contact windows in the pixel electrode forming step.