CN112185814A - Etching method of semiconductor structure - Google Patents

Etching method of semiconductor structure Download PDF

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CN112185814A
CN112185814A CN202011187636.3A CN202011187636A CN112185814A CN 112185814 A CN112185814 A CN 112185814A CN 202011187636 A CN202011187636 A CN 202011187636A CN 112185814 A CN112185814 A CN 112185814A
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etching
semiconductor structure
over
layer
utm
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CN112185814B (en
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梁梦诗
蒋燚
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Shanghai Huali Microelectronics Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H01L22/26—Acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection, in-situ thickness measurement

Abstract

The invention provides an etching method of a semiconductor structure, which comprises the steps of providing the semiconductor structure, wherein the semiconductor structure comprises a substrate and a UTM lamination on the substrate, and the UTM lamination comprises a first low-dielectric oxide layer, a second low-dielectric oxide layer and an etching stop layer which are sequentially formed on the substrate; forming a patterned photoresist layer on the UTM stack, and collecting the light transmittance of the photoresist layer; performing main etching on the UTM laminated layer, and etching the second low-dielectric oxide layer and stopping at the first low-dielectric oxide layer; and substituting the light transmittance into an over-etching equation to obtain over-etching process parameters, and feeding the over-etching process parameters back to the process cavity to perform over-etching on the UTM laminated layer so as to stop etching on the etching stop layer. According to the etching method of the semiconductor structure, the over-etching equation is obtained by fitting the relation between the light transmittance and the over-etching process parameters of different semiconductor structures, so that the process parameters when the semiconductor structure is over-etched are calculated and adjusted, and the etching precision of the semiconductor structure is improved.

Description

Etching method of semiconductor structure
Technical Field
The invention relates to the technical field of semiconductors, in particular to an etching method of a semiconductor structure.
Background
In the integrated circuit production process, the back-end copper interconnection is applied to the etching process of an Ultra Thick Metal (UTM), and the UTM etching process has higher requirements on etching selection ratio and uniformity and has high process difficulty. In the UTM etching process, a load effect between different semiconductor structures needs to be considered, otherwise, Punch-through (Punch through) of the semiconductor structure due to too fast etching or open circuit of a metal line of the semiconductor structure due to insufficient etching may occur. In the prior art, an end point monitoring (EPD) is usually used to detect the etching condition of the UTM, and the etching degree of the corresponding dielectric layer is determined by collecting an emission spectrum (OES) curve generated by chemical changes of different dielectric layers of the semiconductor structure during the etching process, so as to control corresponding parameters of the etching process.
However, when the light transmittance of the semiconductor structure is too large or too small, the EPD cannot accurately acquire the etching condition of the semiconductor structure, so that the condition of excessive etching or insufficient etching occurs. Meanwhile, the light transmittance of the semiconductor structure has a very important influence on the critical dimension of the semiconductor structure. The smaller the light transmittance of the semiconductor structure is, the larger the coverage area of the photoresist on the surface of the semiconductor structure is, and the more polymers generated by the reaction of the photoresist in the etching process are. The polymer adheres to the sidewalls of the semiconductor structure, which can have a severe impact on the critical dimensions of the semiconductor device.
In order to avoid the above situation, a new etching method is required to improve the etching accuracy.
Disclosure of Invention
The invention aims to provide an etching method of a semiconductor structure, which obtains an over-etching equation by fitting the relation between the light transmittance of different semiconductor structures and the process parameters in the over-etching process, thereby calculating and adjusting the process parameters in the over-etching process of the semiconductor structure and further improving the etching precision of the semiconductor structure.
In order to achieve the above object, the present invention provides an etching method for a semiconductor structure, comprising:
providing a semiconductor structure, wherein the semiconductor structure comprises a substrate and a UTM lamination formed on the substrate, and the UTM lamination comprises a first low dielectric oxide layer, a second low dielectric oxide layer and an etching stop layer which are sequentially formed on the substrate;
forming a patterned photoresist layer on the UTM stack, and collecting light transmittance of the photoresist layer;
performing main etching on the UTM laminated layer, and etching the second low-dielectric oxide layer and stopping at the first low-dielectric oxide layer;
and substituting the light transmittance into an over-etching equation to obtain over-etching process parameters, and feeding the over-etching process parameters back to a process cavity to perform over-etching on the UTM laminated layer so as to stop etching on the etching stop layer.
Optionally, the parameters of the over-etching process include etching time and a ratio of a reactive gas to a cleaning gas in the over-etching process.
Optionally, the reaction gas is a heavy polymer gas comprising C4F6Said cleaning gas comprising O2。
Optionally, the over-etching equation includes:
y＝2.2583x-9.1535；
z＝0.0164x+0.0897；
wherein x is the light transmittance; y is the etching time; z is C in the process gas4F6And O2The ratio of (a) to (b).
Optionally, after the over-etching is performed on the UTM stack, the method further includes:
and collecting the characteristic dimension of the photoresist layer, and correcting the over-etching equation according to the characteristic dimension so as to calculate the etching process of the next batch of UTM laminated layers.
Optionally, an end point monitoring mode is adopted to monitor the etching condition of the main etching and control the etching time of the main etching.
Optionally, the light transmittance is collected in real time by an APC feedback system, and the feedback of the over-etching process parameters is adjusted according to the over-etching equation.
Optionally, the UTM stack further includes a dielectric barrier layer formed between the first low dielectric oxide layer and the second low dielectric oxide layer.
Optionally, the UTM stack further includes a plurality of metal vias penetrating through the etch stop layer and the first low dielectric oxide layer.
Optionally, an anti-reflection layer is further formed between the second low dielectric oxide layer and the photoresist layer.
In summary, the present invention provides an etching method for a semiconductor structure, including providing a semiconductor structure, where the semiconductor structure includes a substrate and a UTM stack formed on the substrate, and the UTM stack includes a first low dielectric oxide layer, a second low dielectric oxide layer, and an etching stop layer sequentially formed on the substrate; forming a patterned photoresist layer on the UTM stack, and collecting light transmittance of the photoresist layer; performing main etching on the UTM laminated layer, and etching the second low-dielectric oxide layer and stopping at the first low-dielectric oxide layer; and substituting the light transmittance into an over-etching equation to obtain over-etching process parameters, and feeding the over-etching process parameters back to a process cavity to perform over-etching on the UTM laminated layer so as to stop etching on the etching stop layer. According to the etching method of the semiconductor structure, the over-etching equation is obtained by fitting the relation between the light transmittance of different semiconductor structures and the process parameters in the over-etching process, so that the process parameters in the over-etching process of the semiconductor structure are calculated and adjusted, and the etching precision of the semiconductor structure is improved. In addition, the etching method of the semiconductor structure also introduces an APC feedback system in the etching process, and solves the problem that the etching condition cannot be monitored when the light transmittance of the semiconductor structure is too large or too small only by using an end point monitoring mode.
Drawings
Fig. 1 is a flowchart of a method for etching a semiconductor structure according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a semiconductor structure in the method for etching a semiconductor structure provided in this embodiment;
fig. 3 is a graph illustrating a relationship between light transmittance and etching time in the etching method for a semiconductor structure according to the present embodiment;
FIG. 4 shows the transmittance and C in the process gas in the etching method for the semiconductor structure provided in this embodiment4F6And O2A relationship diagram of the proportion of (1);
fig. 5 and fig. 6 are schematic structural diagrams of the etched semiconductor structure in the etching method for the semiconductor structure according to the embodiment;
wherein the reference numbers are as follows:
100-a substrate; 200-etching stop layer; 300-a first low dielectric oxide layer; 310-a dielectric barrier layer; 320-metal vias; 400-a second low dielectric oxide layer; 410-an anti-reflection layer; 420-photoresist layer.
Detailed Description
The following describes in more detail embodiments of the present invention with reference to the schematic drawings. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Fig. 1 is a flowchart of a method for etching a semiconductor structure according to an embodiment of the present invention. Referring to fig. 1, the method for etching a semiconductor structure according to the present embodiment includes:
step S01: providing a semiconductor structure, wherein the semiconductor structure comprises a substrate and a UTM lamination formed on the substrate, and the UTM lamination comprises a first low dielectric oxide layer, a second low dielectric oxide layer and an etching stop layer which are sequentially formed on the substrate;
step S02: forming a patterned photoresist layer on the UTM stack, and collecting light transmittance of the photoresist layer;
step S03: performing main etching on the UTM laminated layer, and etching the second low-dielectric oxide layer and stopping at the first low-dielectric oxide layer;
step S04: and substituting the light transmittance into an over-etching equation to obtain over-etching process parameters, and feeding the over-etching process parameters back to a process cavity to perform over-etching on the UTM laminated layer so as to stop etching on the etching stop layer.
The method for etching the semiconductor structure provided by the present embodiment is described in detail below with reference to fig. 2 to 6.
First, referring to fig. 2, step S01 is performed to provide a semiconductor structure including a substrate 100 and a UTM stack formed on the substrate 100, the UTM stack including sequential shapesA first low dielectric oxide layer 300, a second low dielectric oxide layer 400, and an etch stop layer 200 formed on the substrate 100. Specifically, in this embodiment, a dielectric barrier layer 310 is further disposed between the first low dielectric oxide layer 300 and the second low dielectric oxide layer 400. In other embodiments of the present invention, other semiconductor structures may be further included between the substrate 100 and the etch stop layer 200, that is, the semiconductor structures may be adjusted according to actual needs, which is not limited in the present invention. Optionally, the thickness of the etch stop layer 200 is
Figure BDA0002751801460000041
And the material of the etch stop layer 200 includes Silicon Nitride Doped with carbon (NDC); the first low dielectric oxide layer 300 has a thickness of
Figure BDA0002751801460000042
The second low dielectric oxide layer 400 has a thickness of
Figure BDA0002751801460000043
And the materials of the first low dielectric oxide layer 300 and the second low dielectric oxide layer 400 both include polyethylene oxide (PEOX); the dielectric barrier layer 310 has a thickness of
Figure BDA0002751801460000044
And the material of the dielectric barrier layer 310 comprises silicon nitride. It should be noted that the thickness of each film layer in the semiconductor structure is only an example, and the composition, thickness and material of each film layer of the semiconductor structure may be adjusted according to actual needs, which is not limited in the present invention. In addition, referring to fig. 2, the semiconductor structure further includes a plurality of metal vias 320, wherein the metal vias 320 penetrate through the first low dielectric oxide layer 300 and the etch stop layer 200.
Next, with continuing reference to fig. 2, step S02 is performed to form a patterned photoresist layer 420 on the UTM stack, and the optical transmittance of the photoresist layer 420 is collected. Optionally, the second low dielectric oxide layer 400 and theAn anti-reflective layer 410 is also disposed between the photoresist layers 420. In this embodiment, the thickness of the anti-reflection layer 410 is
Figure BDA0002751801460000051
The thickness of the photoresist layer is
Figure BDA0002751801460000052
It should be noted that the thickness of each film layer in the semiconductor structure is only an example, and the composition, thickness and material of each film layer of the semiconductor structure may be adjusted according to actual needs, which is not limited in the present invention. Optionally, the transmittance is collected using an Advanced Process Control (APC) system.
Subsequently, referring to fig. 5, step S03 is performed to perform a main etching on the UTM stack, and the second low dielectric oxide layer 400 is etched and stopped at the first low dielectric oxide layer 300. In this embodiment, the semiconductor structure is subjected to main etching under the conditions of a low selection ratio and a high etching rate, an End Point Detection (EPD) is used to monitor the etching condition, and the etching condition is judged by collecting an emission spectrum curve generated by chemical changes of each film layer in the etching process, so as to control the termination time of the main etching. In other embodiments of the present invention, the method for monitoring the etching condition of the main etching may be adjusted according to actual needs, which is not limited in the present invention.
Next, referring to fig. 3, 4 and 6, step S04 is executed to substitute the transmittance into an over-etching equation to obtain over-etching process parameters, and the over-etching process parameters are fed back to the process chamber to over-etch the UTM stack layer, so that the etching is stopped at the etching stop layer 200. In this embodiment, the parameters of the over-etching process include etching time and a ratio of a reactive gas to a cleaning gas in the over-etching process. The reaction gas is heavy polymer gas, i.e. gas containing carbon with large specific gravity, including C4F6Said cleaning gas comprising O2In other embodiments of the present invention, the over-etching process parameter may be other process parameters affecting the etching effect, such as the etching temperatureThe invention is not limited in this regard.
Specifically, the transmittance acquired in step S02 is substituted into the over-etching equation to obtain the over-etching process parameters, i.e., the over-etching time and C in the process gas4F6And O2And feeding back the first process parameter to the process chamber through the APC system, thereby controlling the over-etching process of the semiconductor structure, etching the first low-k oxide layer 300 of the semiconductor structure under the condition of high selectivity, and avoiding the etching stop layer 200 from being etched through due to over-etching. The APC system is introduced to solve the problem that the etching condition cannot be monitored when the light transmittance of the semiconductor structure is too large or too small only by using an endpoint monitoring mode.
In this embodiment, the light transmittance of different semiconductor structures and the over-etching process parameters corresponding to the semiconductor structures are collected, and the light transmittance and the over-etching process parameters are fitted to obtain a relational expression between the light transmittance of the semiconductor structures and the over-etching process parameters, that is, the over-etching equation. Optionally, a database is established, and data basis for subsequently optimizing the over-etching equation can be provided by collecting the light transmittance and the over-etching process parameters of different semiconductor structures in the etching process.
FIG. 3 is a graph of light transmittance versus etching time; FIG. 4 shows transmittance and C in process gas4F6And O2Is shown in the relationship diagram of the proportion of (1). Referring to fig. 3 and 4, the relationship (1) between the etching time and the transmittance in the over-etching process and C in the process gas are obtained by fitting4F6And O2The over-etching equation, which is a relation (2) between the ratio of (a) to (b) and the transmittance, is as follows:
y＝2.2583x-9.1535； (1)
z＝0.0164x+0.0897； (2)
wherein x is the light transmittance; y is the etching time and the unit is s; z is C in the process gas4F6And O2The ratio of (a) to (b). Meanwhile, the fitting degree value R1 of the relation (1) of the etching time and the light transmittance in the over-etching process20.9754; c in the process gas4F6And O2Degree of fit R2 of the relation (2) between the ratio of (A) and the light transmittance20.9033. The degree of fit value R12And R22Closer to 1 indicates a better fit for the relationship.
In addition, the etching method of the semiconductor structure further comprises the following steps: respectively collecting the characteristic sizes of the photoresist layer in the semiconductor structure before and after etching, correcting the over-etching equation according to the change condition of the characteristic sizes, wherein the corrected over-etching equation is used for calculating over-etching process parameters in the next over-etching step so as to improve the etching precision. Specifically, the change condition of the characteristic dimension of the photoresist layer before and after etching can be compared, and the over-etching equation is corrected by taking the variation of the characteristic dimension as an influence factor so as to continuously improve the fitting degree of the over-etching equation and further improve the etching precision.
In summary, the present invention provides an etching method for a semiconductor structure, including providing a semiconductor structure, where the semiconductor structure includes a substrate and a UTM stack formed on the substrate, and the UTM stack includes a first low dielectric oxide layer, a second low dielectric oxide layer, and an etching stop layer sequentially formed on the substrate; forming a patterned photoresist layer on the UTM stack, and collecting light transmittance of the photoresist layer; performing main etching on the UTM laminated layer, and etching the second low-dielectric oxide layer and stopping at the first low-dielectric oxide layer; and substituting the light transmittance into an over-etching equation to obtain over-etching process parameters, and feeding the over-etching process parameters back to a process cavity to perform over-etching on the UTM laminated layer so as to stop etching on the etching stop layer. According to the etching method of the semiconductor structure, the over-etching equation is obtained by fitting the relation between the light transmittance of different semiconductor structures and the process parameters in the over-etching process, so that the process parameters in the over-etching process of the semiconductor structure are calculated and adjusted, and the etching precision of the semiconductor structure is improved. In addition, the etching method of the semiconductor structure also introduces an APC feedback system in the etching process, and solves the problem that the etching condition cannot be monitored when the light transmittance of the semiconductor structure is too large or too small only by using an end point monitoring mode.
The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any way. It will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (10)

1. A method for etching a semiconductor structure, comprising:
providing a semiconductor structure, wherein the semiconductor structure comprises a substrate and a UTM lamination formed on the substrate, and the UTM lamination comprises a first low dielectric oxide layer, a second low dielectric oxide layer and an etching stop layer which are sequentially formed on the substrate;
forming a patterned photoresist layer on the UTM stack, and collecting light transmittance of the photoresist layer;
performing main etching on the UTM laminated layer, and etching the second low-dielectric oxide layer and stopping at the first low-dielectric oxide layer;
and substituting the light transmittance into an over-etching equation to obtain over-etching process parameters, and feeding the over-etching process parameters back to a process cavity to perform over-etching on the UTM laminated layer so as to stop etching on the etching stop layer.
2. The method of etching a semiconductor structure according to claim 1, wherein the parameters of the over-etching process include etching time and a ratio of a reactive gas to a cleaning gas in the over-etching process.
3. The method of etching a semiconductor structure of claim 2, wherein the reactive gas is a heavy polymer gas comprising C4F6Said cleaning gas comprising O2。
4. The method of etching a semiconductor structure of claim 3, wherein the over-etch equation comprises:
y＝2.2583x-9.1535；
z＝0.0164x+0.0897；
wherein x is the light transmittance; y is the etching time; z is C in the process gas4F6And O2The ratio of (a) to (b).
5. The method of etching a semiconductor structure of claim 1, wherein over-etching the UTM stack further comprises:
and collecting the characteristic dimension of the photoresist layer, and correcting the over-etching equation according to the characteristic dimension so as to calculate the etching process of the next batch of UTM laminated layers.
6. The method of etching a semiconductor structure according to claim 1, wherein an end point monitoring mode is used to monitor the etching condition of the main etch and control the etching time of the main etch.
7. The method of etching a semiconductor structure of claim 1, wherein the transmittance is collected in real time by an APC feedback system and the feedback of the over-etch process parameters is adjusted according to the over-etch equation.
8. The method of etching a semiconductor structure of claim 1, wherein the UTM stack further comprises a dielectric barrier layer formed between the first low dielectric oxide layer and the second low dielectric oxide layer.
9. The method of etching a semiconductor structure of claim 8, wherein the UTM stack further comprises a plurality of metal vias through the etch stop layer and the first low dielectric oxide layer.
10. The method for etching a semiconductor structure according to claim 1, wherein an anti-reflection layer is further formed between the second low dielectric oxide layer and the photoresist layer.
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Publication number Priority date Publication date Assignee Title
CN117092881A (en) * 2023-08-29 2023-11-21 上海铭锟半导体有限公司 Preparation method of nano-imprinting master plate

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