KR100876834B1

KR100876834B1 - Method for manufacturing semiconductor device

Info

Publication number: KR100876834B1
Application number: KR1020070066741A
Authority: KR
Inventors: 김나현
Original assignee: 주식회사 하이닉스반도체
Priority date: 2007-07-03
Filing date: 2007-07-03
Publication date: 2009-01-07

Abstract

The present invention relates to a method of fabricating a semiconductor device, the method comprising: forming a gate insulating film, a gate polysilicon layer, a gate electrode layer, and a gate hard mask layer on an upper surface of a semiconductor substrate to prevent the gate from leaning; Forming a gate hard mask layer pattern by etching the gate hard mask layer by a photolithography process using a gate mask, forming a first spacer on sidewalls of the gate hard mask layer pattern, a gate hard mask layer pattern, and a first mask Forming a gate by etching the gate electrode layer and the gate polysilicon layer using the spacer as a mask, and forming a second spacer on the sidewall of the gate, so that stress generated during subsequent thermal processing is applied directly to the gate. It is a technology that can prevent the gate from leaking because it is not supported.

Description

Manufacturing method of semiconductor device {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}

1 is a cross-sectional view showing a method for manufacturing a semiconductor device according to the prior art.

2A to 2F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

100 semiconductor substrate 102 gate insulating film

104: gate polysilicon layer

104a: gate polysilicon layer pattern

106: diffusion barrier 106a: diffusion barrier pattern

108: gate electrode layer 108a: gate electrode layer pattern

110: gate hard mask layer

110a: gate hard mask layer pattern

112: oxide film for first spacer 112a: first spacer

114: capping insulating film 114a: second spacer

116 gate 118 oxide film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a gate of a semiconductor device.

As is well known, the gates of semiconductor devices have usually been formed of polysilicon. This is because the polysilicon sufficiently satisfies the physical properties required as a gate such as high melting point, ease of thin film formation, ease of line pattern, stability to an oxidizing atmosphere, and flat surface formation.

In addition, in actual semiconductor devices, the polysilicon gate contains a dopant such as phosphorus (P), arsenic (As), and boron (B) to realize low resistance.

However, as the degree of integration of semiconductor devices increases, variable values such as the line width of the gate, the thickness of the gate insulating layer, the junction depth, and the like decrease, thereby limiting the polysilicon to realize the low resistance required on the fine line width.

Accordingly, various studies on materials for gate electrodes applicable to highly integrated devices have been conducted. As one of them, a gate electrode having a laminated structure of polysilicon and tungsten has been proposed.

1 is a cross-sectional view showing a method of manufacturing a semiconductor device according to the prior art.

Referring to FIG. 1, a gate insulating layer 12, a gate polysilicon layer 14, a diffusion barrier layer 16, a gate electrode layer 18, and a gate hard mask layer 20 are formed on a semiconductor substrate 10.

In this case, the gate insulating film 12 is formed of an oxide film, and the diffusion barrier 16 is formed of a tungsten silicide (Wsix) film.

The gate electrode layer 18 is formed of a tungsten (W) film, and the gate hard mask layer 20 is formed of a nitride film.

Next, the gate hard mask layer 20, the gate electrode layer 18, the diffusion barrier 16, and the gate polysilicon layer 14 having a predetermined depth may be formed by a photolithography process using a mask defining a gate pattern. Etch it.

Next, a capping insulating film 22 is formed over the entire surface.

In this case, since the capping insulating film 22 is formed at a high temperature of 710 ° C. or higher, the capping insulating film 22 is constricted by the densification of the film quality of the gate hard mask layer 20 by the thermal process. ) To stress.

In particular, when the exposed gate polysilicon layer 14 is not etched with the same thickness on the left and right sides, a thickness difference d1 occurs between the left and the right sides.

That is, when the right side is formed thicker than the left side, since the contact area of the capping insulating layer 22 is as large as the portion (A) on the left side, as shown in FIG. ), The force F1 applied to the left side of the gate is greater than the force F2 applied to the right side.

Therefore, the gate is leaned due to the difference between the forces (F1-F2) applied to the left and the right.

As a result, when forming the subsequent storage electrode contact plug, there is a problem of lowering yield by causing a self alignment contact (SAC) defect between the gate and the storage electrode contact plug.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device capable of preventing the gate from leaking.

Method for manufacturing a semiconductor device according to the invention,

Forming a gate insulating film, a gate polysilicon layer, a gate electrode layer, and a gate hard mask layer on the semiconductor substrate;

Forming a gate hard mask layer pattern by etching the gate hard mask layer by a photolithography process using a gate mask;

Forming a first spacer on sidewalls of the gate hard mask layer pattern;

Etching the gate electrode layer and the gate polysilicon layer using the gate hard mask layer pattern and the first spacer as a mask to form a gate; And

Forming a second spacer on the gate sidewall

Characterized in that it comprises a.

In the present invention, further comprising forming a diffusion barrier layer between the gate polysilicon layer and the gate electrode layer,

The gate hard mask layer pattern forming step may be performed by remaining 5 to 20% of the thickness of the gate electrode layer in a region other than the gate region;

The first spacer forming step

Forming an oxide film over the entire surface,

Performing an entire surface etching process on the oxide film;

The oxide film is formed to a thickness of 10 ~ 1000Å,

The second spacer forming step

Forming a capping insulation layer over the entire surface;

Performing an entire surface etching process on the capping insulation layer;

Performing a selective gate reoxidation process to form an oxide film on sidewalls of the gate polysilicon layer

It characterized in that it further comprises.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

2A through 2F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

Referring to FIG. 2A, a gate insulating layer 102, a gate polysilicon layer 104, a diffusion barrier layer 106, a gate electrode layer 108, and a gate hard mask layer 110 are formed on the semiconductor substrate 100.

In this case, the gate insulating layer 102 is formed of an oxide film, and the diffusion barrier layer 106 is formed of a tungsten silicide (WSix) film.

The gate electrode layer 108 is formed of a tungsten (W) layer, and the gate hard mask layer 110 is formed of a nitride film.

Referring to FIG. 2B, a photosensitive film is formed on the gate hard mask layer 110.

Then, the photoresist film is exposed and developed with an exposure mask defining a gate pattern to form a photoresist pattern.

Next, the gate hard mask layer 110 is etched using the photoresist pattern as a mask to form a gate hard mask layer pattern 110a.

In this case, during the etching process of the gate hard mask layer 110, the etching target is preferably etched so as to remain on the surface of the gate electrode layer 108.

This is to prevent the gate electrode layer 108 from oxidizing in a subsequent oxide film forming process, and is preferably formed to remain by 5 to 20% of the thickness of the gate electrode layer 108.

Then, the photoresist pattern is removed.

Referring to FIG. 2C, the oxide film 112 for the first spacer is formed on the entire surface.

At this time, the first spacer oxide film 112 is preferably formed to a thickness of 10 ~ 1000Å.

Referring to FIG. 2D, a first spacer 112a is formed on sidewalls of the gate hard mask layer pattern 110a by performing an entire surface etching process.

Next, the gate electrode layer 108, the diffusion barrier layer 106, and the gate polysilicon layer 104 having a predetermined depth are etched using the gate hard mask layer pattern 110a and the first spacer 112a as a mask. Thus, the gate electrode layer pattern 108a, the diffusion barrier layer pattern 106a, and the gate polysilicon layer pattern 104a are formed.

Referring to FIG. 2E, a capping insulating layer 114 is formed on the entire surface.

In this case, in the thermal process for forming the capping insulating layer 114, the gate hard mask layer pattern 110a is densified and the volume is reduced to generate stress.

However, since the stress is not directly applied to the capping insulating layer 114 by the first spacer 112a, the gate may be tilted.

Meanwhile, the capping insulating film 114 may be formed of a nitride film.

Referring to FIG. 2F, the capping insulating layer 114 is etched to form a second spacer 114a.

Next, the gate polysilicon layer pattern 104a is etched to form the gate 116.

Next, a selective gate re-oxidation process is performed to form an oxide film 118 on sidewalls of the gate polysilicon layer pattern 104a.

As described above, the method of manufacturing a semiconductor device according to the present invention forms a spacer on a sidewall of a gate hard mask layer pattern so that a stress generated during a subsequent thermal process is not directly applied to the gate, so that the gate is inclined. The phenomenon can be prevented.

In the method of fabricating a semiconductor device according to the present invention, a spacer may be formed on a sidewall of a gate hard mask layer pattern, thereby preventing the gate from being leaned because stress generated in a subsequent thermal process is not directly applied to the gate. This prevents SAC defects between the gate and the landing plug, thereby improving device yield.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims

Forming a gate insulating layer, a gate polysilicon layer, a gate electrode layer, and a gate hard mask layer on the semiconductor substrate;

Forming a first spacer on sidewalls of the gate hardmask layer pattern;

Forming a second spacer on the gate sidewall

Method of manufacturing a semiconductor device comprising a.

2. The method of claim 1, further comprising forming a diffusion barrier layer between the gate polysilicon layer and the gate electrode layer.

The method of claim 1, wherein the forming of the gate hard mask layer pattern comprises forming the gate hard mask layer pattern by remaining 5 to 20% of the thickness of the gate electrode layer in a region other than the gate region.

The method of claim 1, wherein the first spacer forming step

Forming an oxide film over the entire surface; And

Performing an entire surface etching process on the oxide layer

Method of manufacturing a semiconductor device comprising a.

The method of manufacturing a semiconductor device according to claim 4, wherein the oxide film is formed to a thickness of 10 to 1000 GPa.

The method of claim 1, wherein the second spacer forming step

Forming a capping insulation layer over the entire surface; And

Performing an entire surface etching process on the capping insulating layer

Method of manufacturing a semiconductor device comprising a.

The method of claim 1, further comprising: forming an oxide film on sidewalls of the gate polysilicon layer by performing a selective gate reoxidation process.

Method for manufacturing a semiconductor device characterized in that it further comprises