KR100620234B1 - Fabricating method for forming a salicide blocklayer - Google Patents

Fabricating method for forming a salicide blocklayer Download PDF

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KR100620234B1
KR100620234B1 KR1020040115667A KR20040115667A KR100620234B1 KR 100620234 B1 KR100620234 B1 KR 100620234B1 KR 1020040115667 A KR1020040115667 A KR 1020040115667A KR 20040115667 A KR20040115667 A KR 20040115667A KR 100620234 B1 KR100620234 B1 KR 100620234B1
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salicide
mask
photoresist
block
voltage region
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KR1020040115667A
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KR20060077029A (en
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김재영
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동부일렉트로닉스 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type

Abstract

본 발명은 반도체 소자의 살리사이드 형성 방법에 관한 것으로, 살리사이드 블록을 증착하는 단계; 상기 살리사이드 블록에 포토레지스터를 도포하고, 높은 전압 영역의 마스크와 낮은 전압 영역의 마스크에 투과율이 다른 물질을 선택적으로 코팅하여 노광 현상 및 패턴을 형성하는 단계; 상기 포토레지스터 패턴을 마스크로 살리사이드 블록을 식각하고 포토레지스터를 제거하는 단계 및 상기 살리사이드 블록을 식각한 후, 세정하는 단계로 이루어짐에 기술적 특징이 있고, 살리사이드 블록 영역을 패터닝시 마스크에 투과율이 다른 물질을 선택적으로 코팅함으로써 낮은 전압 영역에서 발생하는 실리콘 손실이 감소되어 구동전류와 콘택저항의 특성이 개선되는 효과가 있다.The present invention relates to a method of forming a salicide of a semiconductor device, the method comprising: depositing a salicide block; Applying a photoresist to the salicide block and selectively coating a material having a different transmittance to a mask of a high voltage region and a mask of a low voltage region to form an exposure phenomenon and a pattern; The salient block is etched using the photoresist pattern as a mask, the photoresist is removed, and the salicide block is etched and then cleaned, and the pattern of the salicide block region is transmitted to the mask during patterning. By selectively coating this other material, silicon loss in the low voltage region is reduced, thereby improving the characteristics of the driving current and the contact resistance.

살리사이드 블록, 마스크, 포토레지스터Salicide Blocks, Masks, Photoresistors

Description

살리사이드 블록막 형성 방법{Fabricating method for forming a salicide blocklayer}Fabrication method for forming a salicide blocklayer}

도 1a 내지 도 1e는 종래의 살리사이드 형성 방법을 나타내는 공정 단면도이다.1A to 1E are cross-sectional views illustrating a conventional salicide forming method.

도 2a 내지 도 2e는 본 발명에 따른 살리사이드 형성 방법을 나타내는 공정 단면도이다.2A to 2E are cross-sectional views illustrating a method of forming a salicide according to the present invention.

본 발명은 반도체 소자의 살리사이드 형성 방법에 관한 것으로, 보다 자세하게는 살리사이드 블록 영역을 패터닝시 마스크에 투과율이 다른 물질을 선택적으로 코팅하여 낮은 전압 영역의 실리콘 손실을 최소화하는 살리사이드 형성 방법에 관한 것이다.The present invention relates to a method for forming a salicide of a semiconductor device, and more particularly, to a method for forming a salicide in which a silicon substrate in a low voltage region is minimized by selectively coating a material having a different transmittance to a mask when patterning a salicide block region. will be.

트랜지스터의 성능은 트랜지스터의 속도, 구동전류(Drive Current) 및 누설전류(Leakage Current)와 밀접한 관계가 있으며, 트랜지스터의 성능을 좋게하기 위 해서 트랜지스터의 속도 및 구동전류는 커야 하고, 누설전류는 작아야 한다.Transistor performance is closely related to transistor speed, drive current, and leakage current. To improve transistor performance, transistor speed and drive current must be large and leakage current must be small. .

트랜지스터의 속도와 구동전류를 증가시키고, 누설전류를 작게 하기 위해서는 트랜지스터의 소스 및 드레인의 저항, 트랜지스터의 게이트의 저항 및 콘택저항들의 저항값을 작게 만들어야 한다.In order to increase the speed and driving current of the transistor and to reduce the leakage current, the resistance of the source and drain of the transistor, the resistance of the gate of the transistor, and the contact resistances must be made small.

트랜지스터의 소스 및 드레인의 저항, 트랜지스터의 게이트의 저항 및 콘택저항들의 저항값을 작게 만들기 위해 드레인/소스의 계면 및 게이트의 계면에 실리사이드(Silicide)를 제조하기 위한 살리사이드(Self-aligned silicide:Salicide) 공정을 사용한다.Self-aligned silicide (Salicide) for the production of silicide at the interface of the drain and source and the interface of the gate to make the resistance of the source and drain of the transistor, the resistance of the gate of the transistor and the contact resistances small. ) Process is used.

도 1a 내지 도 1e는 종래의 살리사이드 형성 방법을 나타내는 공정 단면도이다. 도 1a에 도시된 바와 같이, 살리사이드 블록(Salicide Block)을 증착하기 전에 높은 전압(High Voltage) 영역과 낮은 전압(Low Voltage) 영역 간의 두께의 차이가 발생한다. 1A to 1E are cross-sectional views illustrating a conventional salicide forming method. As shown in FIG. 1A, a difference in thickness between a high voltage region and a low voltage region occurs before depositing a salicide block.

도 1b 및 도 1e에 도시된 바와 같이, TEOS(Tetra-Ethoxysilane)로 살리사이드 블록(10)을 약 1000Å의 두께로 증착한 후, 상기 살리사이드 블록(10)에 포토레지스터를 도포하고, 마스크(20)를 이용하여 상기 포토레지스터를 노광 현상함으로써, 패턴을 형성한다. 상기 포토레지스터 패턴을 마스크로 살리사이드 블록(10)을 식각한 후, 상기 포토레지스터를 제거한다. 이후, 식각 공정을 통해 선택적으로 살리사이드 블록 영역을 형성한다.1B and 1E, after depositing a salicide block 10 with a thickness of about 1000 GPa using TEOS (Tetra-Ethoxysilane), a photoresist is applied to the salicide block 10, and a mask ( The pattern is formed by exposing and developing the photoresist using 20). After the salicide block 10 is etched using the photoresist pattern as a mask, the photoresist is removed. Thereafter, the salicide block region is selectively formed through an etching process.

그러나 상기와 같은 종래의 기술은 살리사이드 블록 영역을 형성하기 위하여 비교적 두꺼운 TEOS를 약 1000Å의 두께로 증착하는데, 이때 높은 전압 영역과 낮 은 전압 영역의 산화막 두께 차이가 큰 소자일수록 살리사이드 블록을 식각할 때 낮은 전압 활성 영역의 실리콘 손실이 크게 발생되어 구동전류와 콘택 저항 등의 특성을 악화시키는 문제점이 있었다.However, the conventional technique as described above, to form a salicide block region, a relatively thick TEOS is deposited to a thickness of about 1000 mA, wherein the salicide block is more etched in a device having a large difference in oxide thickness between the high voltage region and the low voltage region. When the silicon loss in the low voltage active region is large, there is a problem that deteriorates characteristics such as driving current and contact resistance.

따라서, 본 발명은 상기와 같은 종래 기술의 제반 단점과 문제점을 해결하기 위한 것으로, 살리사이드 블록 영역을 패터닝시 마스크에 투과율이 다른 물질을 선택적으로 코팅하여 낮은 전압 영역의 일정량의 포토레지스터를 의도적으로 남겨 살리사이드 영역의 식각시 낮은 전압 영역의 실리콘 손실을 최소화하는 반도체 소자의 살리사이드 형성 방법을 제공함에 본 발명의 목적이 있다.
Accordingly, the present invention is to solve the above-mentioned disadvantages and problems of the prior art, by intentionally coating a certain amount of photoresist in a low voltage region by selectively coating a material having a different transmittance to the mask when patterning the salicide block region. It is an object of the present invention to provide a method for forming a salicide of a semiconductor device which minimizes silicon loss in the low voltage region during etching of the salicide region.

본 발명의 상기 목적은 살리사이드 블록을 증착하는 단계; 상기 살리사이드 블록에 포토레지스터를 도포하고, 높은 전압 영역의 마스크와 낮은 전압 영역의 마스크에 투과율이 다른 물질을 선택적으로 코팅하여 노광 현상 및 패턴을 형성하는 단계; 상기 포토레지스터 패턴을 마스크로 살리사이드 블록을 식각하고 포토레지스터를 제거하는 단계 및 상기 살리사이드 블록을 식각한 후, 세정하는 단계를 포함하여 이루어진 반도체 소자의 살리사이드 형성 방법에 의해 달성된다.The object of the present invention is to deposit a salicide block; Applying a photoresist to the salicide block and selectively coating a material having a different transmittance to a mask of a high voltage region and a mask of a low voltage region to form an exposure phenomenon and a pattern; Etching the salicide block using the photoresist pattern as a mask and removing the photoresist; and etching the salicide block and then cleaning the salicide block.

본 발명의 상기 목적과 기술적 구성 및 그에 따른 작용효과에 관한 자세한 사항은 본 발명의 바람직한 실시예를 도시하고 있는 도면을 참조한 이하 상세한 설 명에 의해 보다 명확하게 이해될 것이다.Details of the above object and technical configuration and the effects thereof according to the present invention will be more clearly understood by the following detailed description with reference to the drawings showing preferred embodiments of the present invention.

도 2a 내지 도 2e는 본 발명에 따른 살리사이드 형성 방법을 나타내는 공정 단면도이다. 도 2a에 도시된 바와 같이, 살리사이드 블록을 증착하기 전에 높은 전압 영역(100)과 낮은 전압 영역(110) 간의 두께의 차이가 발생한다. 2A to 2E are cross-sectional views illustrating a method of forming a salicide according to the present invention. As shown in FIG. 2A, the difference in thickness between the high voltage region 100 and the low voltage region 110 occurs prior to depositing the salicide block.

도 2b 및 도 2d에 도시된 바와 같이, 살리사이드 블록(120)을 증착한 후, 상기 살리사이드 블록(120)에 포토레지스터를 도포하고, 마스크를 이용하여 상기 포토레지스터를 노광 현상함으로써, 패턴을 형성한다. 이때, 높은 전압 영역(100)의 마스크(130)와 낮은 전압 영역(110)의 마스크(140)에 투과율이 다른 물질을 선택적으로 코팅함으로써, 상기 낮은 전압 영역(110)의 포토레지스터(150)를 의도적으로 남기게 한다.2B and 2D, after depositing the salicide block 120, a photoresist is applied to the salicide block 120, and the photoresist is exposed and developed using a mask to form a pattern. Form. In this case, the photoresist 150 of the low voltage region 110 is selectively coated by selectively coating a material having a different transmittance to the mask 130 of the high voltage region 100 and the mask 140 of the low voltage region 110. Intentionally left.

이후, 상기 포토레지스터 패턴을 마스크로 살리사이드 블록(120)을 식각한 후, 상기 포토레지스터를 제거한다.Thereafter, the salicide block 120 is etched using the photoresist pattern as a mask, and then the photoresist is removed.

도 2e에 도시된 바와 같이, 식각 공정을 통해 선택적으로 살리사이드 블록 영역을 형성한 후, 세정한다.As shown in FIG. 2E, the salicide block region is selectively formed through an etching process and then cleaned.

따라서, 본 발명에 의한 살리사이드 형성 공정은 살리사이드 영역을 패터닝할 때, 높은 전압 영역의 마스크와 낮은 전압 영역의 마스크에 투과율이 다른 물질을 선택적으로 코팅하고, 살리사이드 영역의 패터닝시 낮은 전압 영역에 일정량의 포토레지스터를 의도적으로 남김으로써 이후 진행되는 살리사이드 식각 공정시 낮은 전압 영역의 실리콘 손실을 방지하는 것이다.Therefore, the salicide forming process according to the present invention selectively coats a material having a different transmittance to the mask of the high voltage region and the mask of the low voltage region when patterning the salicide region, and the low voltage region at the time of patterning the salicide region. By intentionally leaving a certain amount of photoresist on the silicon wafer, the silicon oxide in the low voltage region is prevented during the subsequent salicide etching process.

본 발명은 이상에서 살펴본 바와 같이 바람직한 실시예를 들어 도시하고 설 명하였으나, 상기한 실시예에 한정되지 아니하며 본 발명의 정신을 벗어나지 않는 범위 내에서 당해 발명이 속하는 기술분야에서 통상의 지식을 가진 자에 의해 다양한 변경과 수정이 가능할 것이다.Although the present invention has been shown and described with reference to the preferred embodiments as described above, it is not limited to the above embodiments and those skilled in the art without departing from the spirit of the present invention. Various changes and modifications will be possible.

따라서, 본 발명의 반도체 소자의 살리사이드 형성 방법은 살리사이드 블록 영역을 패터닝시 마스크에 투과율이 다른 물질을 선택적으로 코팅함으로써 낮은 전압 영역에서 발생하는 실리콘 손실이 감소되어 구동전류와 콘택저항의 특성이 개선되는 효과가 있다.Therefore, in the method of forming a salicide of the semiconductor device of the present invention, when the salicide block region is patterned, by selectively coating a material having a different transmittance to the mask, silicon loss generated in the low voltage region is reduced, thereby improving the characteristics of driving current and contact resistance. There is an improvement effect.

Claims (2)

기판상에 살리사이드 블록을 증착하는 단계;Depositing a salicide block on the substrate; 상기 살리사이드 블록에 포토레지스터를 도포하고, 투과율이 다른 물질이 선택적으로 코팅된 마스크를 이용하여 상기 포토레지스터의 패턴을 형성하는 단계; 및Applying a photoresist to the salicide block and forming a pattern of the photoresist using a mask selectively coated with a material having a different transmittance; And 상기의 포토레지스터 패턴을 마스크로 이용하여, 상기 살리사이드 블록을 식각하는 단계;가 포함되는 살리사이드 블록막 형성 방법. And etching the salicide block by using the photoresist pattern as a mask. 제 1 항에 있어서,The method of claim 1, 상기 살리사이드 블록을 식각하는 단계가 수행된 다음에는 상기 살리사이드 블록 위에 형성된 포토레지스터 중에서 소정 영역의 포토레지스터를 제거하기 위한 공정이 더 수행되는 것을 특징으로 하는 살리사이드 블록막 형성 방법. And after the etching of the salicide block is performed, a process for removing the photoresist of a predetermined region from the photoresist formed on the salicide block is further performed.
KR1020040115667A 2004-12-29 2004-12-29 Fabricating method for forming a salicide blocklayer KR100620234B1 (en)

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JPH09162299A (en) * 1995-12-04 1997-06-20 Fujitsu Ltd Manufacture of semiconductor device
KR20010002661A (en) * 1999-06-16 2001-01-15 윤종용 Thin film transistor substrate for liquid crystal display and manufacturing method thereof

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JPH09162299A (en) * 1995-12-04 1997-06-20 Fujitsu Ltd Manufacture of semiconductor device
KR20010002661A (en) * 1999-06-16 2001-01-15 윤종용 Thin film transistor substrate for liquid crystal display and manufacturing method thereof

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