KR100209732B1 - Method of fabricating a semiconductor device - Google Patents
Method of fabricating a semiconductor device Download PDFInfo
- Publication number
- KR100209732B1 KR100209732B1 KR1019960052561A KR19960052561A KR100209732B1 KR 100209732 B1 KR100209732 B1 KR 100209732B1 KR 1019960052561 A KR1019960052561 A KR 1019960052561A KR 19960052561 A KR19960052561 A KR 19960052561A KR 100209732 B1 KR100209732 B1 KR 100209732B1
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- KR
- South Korea
- Prior art keywords
- oxide film
- semiconductor device
- forming
- active region
- manufacturing
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 10
- 239000010703 silicon Substances 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 9
- -1 silicon ions Chemical class 0.000 claims abstract description 7
- 238000002955 isolation Methods 0.000 claims abstract description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 claims 1
- 229920002120 photoresistant polymer Polymers 0.000 description 10
- 238000000034 method Methods 0.000 description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 238000004140 cleaning Methods 0.000 description 3
- 238000000059 patterning Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
Abstract
본 발명은 반도체 소자에 관한 것으로, 특히 서로 다른 게이트 산화막을 갖는 MOSFET의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly, to a method of manufacturing a MOSFET having different gate oxide films.
이를위한 본 발명의 반도체 소자 제조방법은 반도체 기판에 적어도 두개 이상의 활성영역을 정의하여 소자 격리를 위한 필드 산화막을 형성하는 공정과; 상기 하나의 활성영역에 실리콘 이온을 주입하는 공정과; 상기 각 활성영역상에서 서로 다른 두께를 갖도록 제1산화막을 형성하는 공정과; 상기 제1산화막상에 게이트 전극을 형성하는 공정을 포함하여 이루어짐을 특징으로 한다.The semiconductor device manufacturing method of the present invention for this purpose is to form a field oxide film for device isolation by defining at least two active regions on the semiconductor substrate; Implanting silicon ions into the active region; Forming a first oxide film to have a different thickness on each of the active regions; And forming a gate electrode on the first oxide film.
Description
본 발명은 반도체 소자에 관한 것으로, 특히 서로 다른 게이트 산화막을 갖는 MOSFET의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly, to a method of manufacturing a MOSFET having different gate oxide films.
이하, 첨부된 도면을 참조하여 종래의 반도체 소자 제조방법에 대하여 설명하면 다음과 같다.Hereinafter, a conventional semiconductor device manufacturing method will be described with reference to the accompanying drawings.
제1a도 내지 제1e도는 종래의 반도체 소자 제조방법을 나타낸 공정 단면도이다.1A to 1E are cross-sectional views illustrating a conventional semiconductor device manufacturing method.
먼저, 제1a도에 도시한 바와같이 반도체 기판(1)의 적어도 두 개의 활성영역을 정의하여 상기 활성영역 이외의 특정영역에 소자 격리층으로 이용되는 필드 산화막(2)을 형성한다.First, as shown in FIG. 1A, at least two active regions of the semiconductor substrate 1 are defined to form the field oxide film 2 used as the device isolation layer in a specific region other than the active region.
이어, 제1b도에 도시한 바와같이 필드 산화막(2)을 제외한 활성영역상에 제1산화막(3a,3b)을 형성하고, 상기 제1산화막(3a,3b)상에 포토레지스트를 증착한 후, 현상 및 노광 공정을 이용하여 하나의 활성영역에 포토레지스트 패턴(4)을 형성한다.Subsequently, as shown in FIG. 1B, the first oxide films 3a and 3b are formed on the active region except for the field oxide film 2, and the photoresist is deposited on the first oxide films 3a and 3b. The photoresist pattern 4 is formed in one active region by using the development and exposure processes.
이어서, 제1c도에 도시한 바와같이 상기 포토레지스트 패턴(4)을 마스크로 하여 다른 하나의 활성영역의 제1산화막(3a)을 제거한다.Subsequently, as shown in FIG. 1C, the first oxide film 3a in the other active region is removed using the photoresist pattern 4 as a mask.
이어, 제1d도에 도시한 바와같이 포토레지스트 패턴(4)을 제거한 후, 상기 제1산화막(3b)을 포함한 전면에 제2산화막(5)을 형성한다.Next, after removing the photoresist pattern 4 as shown in FIG. 1d, the second oxide film 5 is formed on the entire surface including the first oxide film 3b.
이어서, 제1e도에 도시한 바와같이 제2산화막(5)상에 폴리 실리콘층을 형성하고, 상기 제2산화막(5)과 폴리 실리콘층을 선택적으로 패터닝하여 게이트 전극(6)을 형성하므로 듀얼 게이트 산화막을 갖는 MOSFET을 형성한다.Subsequently, as shown in FIG. 1E, a polysilicon layer is formed on the second oxide film 5, and the gate electrode 6 is formed by selectively patterning the second oxide film 5 and the polysilicon layer. A MOSFET having a gate oxide film is formed.
그러나 상기와 같은 종래의 반도체 소자 제조방법에 있어서는 다음과 같은 문제점이 있었다.However, the conventional semiconductor device manufacturing method as described above has the following problems.
첫째, 포토레지스 패턴을 제거할 때, 제1산화막도 일부 식각될 가능성이 크다.First, when the photoresist pattern is removed, a portion of the first oxide film is also likely to be etched.
둘째, 제2산화막을 형성하기 전 세정공정시 제1산화막의 손상과 산화막을 콘트롤 하기 힘들다.Second, it is difficult to control the oxide film and damage of the first oxide film during the cleaning process before forming the second oxide film.
따라서 양질의 게이트 산화막을 형성하기가 어렵다.Therefore, it is difficult to form a high quality gate oxide film.
본 발명은 이와같은 문제점을 해결하기 위하여 안출한 것으로, 실리콘 이온이 주입된 부분의 산화막의 성장 속도를 증가시켜 반도체 디바이스의 특수한 용도에 맞게 게이트 산화막의 두께를 달리할 수 있는 반도체 소자 제조방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above problems, and provides a semiconductor device manufacturing method that can increase the growth rate of the oxide film of the portion implanted with silicon ions to vary the thickness of the gate oxide film to suit the special use of the semiconductor device. Its purpose is to.
제1a도 내지 제1e도는 종래의 반도체 소자 제조방법을 나타낸 공정 단면도.1A to 1E are cross-sectional views showing a conventional method for manufacturing a semiconductor device.
제2a도 내지 제2d도는 본 발명의 반도체 소자 제조방법을 나타낸 공정 단면도.2A to 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
20 : 기판 21 : 필드 산화막20: substrate 21: field oxide film
22 : 포토레지스 패턴 23 : 제1산화막22 photoresist pattern 23 first oxide film
24 : 게이트 전극24: gate electrode
상기와 같은 목적을 달성하기 위한 본 발명의 반도체 소자 제조방법은 반도체 기판에 적어도 두 개의 활성영역을 정의하여 소자 격리를 위한 필드 산화막을 형성하는 공정과; 상기 하나의 활성영역에 실리콘 이온을 주입하는 공정과; 상기 각 활성영역상에서 서로 다른 두께를 갖는 제1산화막을 형성하는 공정과; 상기 제1산화막상에 게이트 전극을 형성하는 공정을 포함하여 이루어짐을 특징으로 한다.The semiconductor device manufacturing method of the present invention for achieving the above object comprises the steps of forming a field oxide film for device isolation by defining at least two active regions on the semiconductor substrate; Implanting silicon ions into the active region; Forming a first oxide film having a different thickness on each active region; And forming a gate electrode on the first oxide film.
이하, 첨부된 도면을 참조하여 본 발명의 반도체 소자 제조방법을 보다 상세히 설명하면 다음과 같다.Hereinafter, a semiconductor device manufacturing method of the present invention will be described in detail with reference to the accompanying drawings.
제2a도 내지 제2d도는 본 발명의 반도체 소자 제조방법을 나타낸 공정 단면도이다.2A to 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device of the present invention.
먼저, 제2a도에 도시한 바와같이 반도체 기판(20)의 적어도 두 개의 활성영역을 정의하여 성가 활성영역 이외의 특정영역에 소자 격리층으로 이용되는 필드 산화막(21)을 형성한다.First, as shown in FIG. 2A, at least two active regions of the semiconductor substrate 20 are defined to form the field oxide film 21 used as the device isolation layer in a specific region other than the annoying active region.
이어, 제2b도에 도시한 바와같이 반도체 기판(20) 전면에 포토레지스트를 증착하고, 현상 및 노광 공정을 이용하여 하나의 활성영역에 포토레지스트 패턴(22)을 형성한다. 그리고 상기 포토레지스트 패턴(22)을 마스크로 하여 기판(20)내에 실리콘 이온을 주입한다.Subsequently, as shown in FIG. 2B, photoresist is deposited on the entire surface of the semiconductor substrate 20, and the photoresist pattern 22 is formed in one active region by using a development and exposure process. Silicon ions are implanted into the substrate 20 using the photoresist pattern 22 as a mask.
이어서, 제2c도에 도시한 바와같이 상기 포토레지스트 패턴(22)을 제거한 후, 전면에 제1산화막(23)을 형성한다. 이때, 두개의 활성영역에는 서로 다른 두께를 갖는 제1산화막(23)을 형성한다.Subsequently, as shown in FIG. 2C, after the photoresist pattern 22 is removed, the first oxide film 23 is formed on the entire surface. In this case, the first oxide layer 23 having different thicknesses is formed in the two active regions.
여기서, 실리콘 이온이 주입된 기판(20)은 실리콘 농도가 높기 때문에 산화막의 성장 속도가 빨라 산화막이 두껍게 형성한다.Here, since the silicon 20 has a high silicon concentration, the substrate 20 into which the silicon ions are implanted has a high growth rate, thereby forming a thick oxide film.
이어, 제2d도에 도시한 바와같이 제1산화막(23)상에 폴리 실리콘층을 형성한 후, 상기 제1산화막(23)과 폴리 실리콘층을 선택적으로 패터닝하여 게이트 전극(24)을 형성하므로 듀얼 게이트 산화막을 갖는 MOSFET을 형성한다.Subsequently, as shown in FIG. 2D, after the polysilicon layer is formed on the first oxide layer 23, the gate electrode 24 is formed by selectively patterning the first oxide layer 23 and the polysilicon layer. A MOSFET having a dual gate oxide film is formed.
한편, 실리콘 이온의 양과 에너지를 조절하여 게이트 산화막의 두께 비율을 컨트롤 하므로 여러 종류의 게이트 산화막을 형성한다.On the other hand, since the thickness ratio of the gate oxide film is controlled by controlling the amount and energy of silicon ions, various types of gate oxide films are formed.
이상에서 설명한 바와같이 본 발명의 반도체 소자 제조방법에 있어서는 다음과 같은 효과가 있다.As described above, the semiconductor device manufacturing method of the present invention has the following effects.
한번의 산화막 공정으로 여러 종류의 게이트 산화막을 형성하므로 공정의 단순화와 게이트 산화막 형성전 세정공정이 가능하므로 세정공정으로 인한 산화막의 손상을 막을 수 있다.Since various kinds of gate oxide films are formed in one oxide process, the process can be simplified and the cleaning process can be prevented before the gate oxide film is formed, thereby preventing damage to the oxide film due to the cleaning process.
따라서 양질의 게이트 산화막을 형성할 수 있다.Therefore, a high quality gate oxide film can be formed.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960052561A KR100209732B1 (en) | 1996-11-07 | 1996-11-07 | Method of fabricating a semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960052561A KR100209732B1 (en) | 1996-11-07 | 1996-11-07 | Method of fabricating a semiconductor device |
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| Publication Number | Publication Date |
|---|---|
| KR19980034502A KR19980034502A (en) | 1998-08-05 |
| KR100209732B1 true KR100209732B1 (en) | 1999-07-15 |
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| KR1019960052561A KR100209732B1 (en) | 1996-11-07 | 1996-11-07 | Method of fabricating a semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR102295957B1 (en) | 2020-04-09 | 2021-09-01 | 김대업 | Beer cup with dry ice cooling structure |
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1996
- 1996-11-07 KR KR1019960052561A patent/KR100209732B1/en not_active IP Right Cessation
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR102295957B1 (en) | 2020-04-09 | 2021-09-01 | 김대업 | Beer cup with dry ice cooling structure |
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| KR19980034502A (en) | 1998-08-05 |
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