KR100236046B1 - Process for fabricating semiconductor device - Google Patents

Process for fabricating semiconductor device Download PDF

Info

Publication number
KR100236046B1
KR100236046B1 KR1019970025837A KR19970025837A KR100236046B1 KR 100236046 B1 KR100236046 B1 KR 100236046B1 KR 1019970025837 A KR1019970025837 A KR 1019970025837A KR 19970025837 A KR19970025837 A KR 19970025837A KR 100236046 B1 KR100236046 B1 KR 100236046B1
Authority
KR
South Korea
Prior art keywords
region
silicon substrate
gate electrode
forming
sides
Prior art date
Application number
KR1019970025837A
Other languages
Korean (ko)
Other versions
KR19990002276A (en
Inventor
황현상
Original Assignee
김영환
현대반도체주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김영환, 현대반도체주식회사 filed Critical 김영환
Priority to KR1019970025837A priority Critical patent/KR100236046B1/en
Publication of KR19990002276A publication Critical patent/KR19990002276A/en
Application granted granted Critical
Publication of KR100236046B1 publication Critical patent/KR100236046B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28097—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a metallic silicide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

본 발명은 제조공정의 간소화 및 살리사이드막의 특성저하를 방지하도록 한 반도체 소자의 제조방법에 관한 것으로서, 셀 영역과 주변회로 영역으로 정의된 실리콘 기판상의 일정영역에 각각 게이트 절연막 및 게이트 전극을 형성하는 단계와, 상기 셀 영역의 게이트 전극 양측의 실리콘 기판 표면내에 저농도 불순물 영역을 형성하고 상기 주변회로 영역의 게이트 전극 양측의 실리콘 기판 표면내에 고농도 불순물 영역을 형성하는 단계와, 상기 셀 영역의 게이트 전극 양측면에 제 1 절연막 측벽 및 주변회로 영역의 전면에 절연막을 형성하는 단계와, 상기 셀 영역의 게이트 전극 및 실리콘 기판 표면에 불순물 도핑영역을 형성하는 단계와, 상기 주변회로 영역의 절연막을 에치백하여 게이트 전극 양측면에 제 2 절연막 측벽을 형성하는 단계와, 상기 각 게이트 전극 양측의 실리콘 기판 표면에 소오스/드레인 불순물 확산영역을 형성하는 단계와, 상기 실리콘 기판의 전면에 산소 분위기에서 RTA 처리를 실시하는 단계와, 그리고 상기 셀 영역의 불순물 도핑 영역에 살리사이드막을 형성하는 단계를 포함하여 형성함을 특징으로 한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for fabricating a semiconductor device that simplifies the manufacturing process and prevents degradation of the salicide film. Forming a low concentration impurity region in the silicon substrate surface on both sides of the gate electrode of the cell region and forming a high concentration impurity region in the silicon substrate surface on both sides of the gate electrode of the peripheral circuit region; Forming an insulating film over the first insulating film sidewall and the peripheral circuit region, and forming an impurity doped region on the gate electrode and the silicon substrate surface of the cell region, and etching back the insulating film of the peripheral circuit region to form a gate. Forming sidewalls of the second insulating layer on both sides of the electrode; Forming a source / drain impurity diffusion region on the surface of the silicon substrate on both sides of the gate electrode, performing RTA treatment in an oxygen atmosphere on the entire surface of the silicon substrate, and forming a salicide film in the impurity doped region of the cell region It characterized by including the step of forming.

Description

반도체 소자의 제조방법Manufacturing method of semiconductor device

본 발명은 반도체 소자의 제조방법에 관한 것으로 특히, 살리사이드(Salicide)의 특성 약화를 방지하는데 적당한 반도체 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device suitable for preventing the degradation of salicide properties.

이하, 첨부된 도면을 참고하여 종래의 반도체 소자의 제조방법을 설명하면 다음과 같다.Hereinafter, a manufacturing method of a conventional semiconductor device will be described with reference to the accompanying drawings.

도 1a 내지 도 1e는 종래의 반도체 소자의 제조방법을 나타낸 공정단면도이다.1A to 1E are cross-sectional views illustrating a method of manufacturing a conventional semiconductor device.

도 1a에 도시한 바와같이 셀 영역과 주변회로 영역으로 정의된 실리콘 기판(11)상에 게이트 절연막(12) 및 게이트 전극용 폴리 실리콘을 차례로 형성하고, 사진석판술 및 식각공정으로 상기 폴리 실리콘 및 게이트 절연막(12)을 선택적으로 제거하여 셀 영역과 주변회로 영역에 각각 게이트 전극(13)을 형성한다.As shown in FIG. 1A, the gate insulating layer 12 and the polysilicon for the gate electrode are sequentially formed on the silicon substrate 11 defined as the cell region and the peripheral circuit region, and the polysilicon and the photolithography and etching processes are sequentially formed. The gate insulating layer 12 is selectively removed to form the gate electrode 13 in the cell region and the peripheral circuit region, respectively.

도 1b에 도시한 바와같이 상기 게이트 전극(13)을 포함한 실리콘 기판(11)의 전면에 제 1 포토레지스트(14)를 도포한 후, 상기 주변회로 영역에만 상기 제 1 포토레지스트(14)가 남도록 노광 및 현상공정으로 패터닝한다.As shown in FIG. 1B, after applying the first photoresist 14 to the entire surface of the silicon substrate 11 including the gate electrode 13, the first photoresist 14 remains only in the peripheral circuit region. Patterning is performed by exposure and development.

이어, 상기 패터닝된 제 1 포토레지스트(14)를 마스크로 이용하여 전면에 저농도 불순물 이온을 주입하여 상기 셀 영역의 게이트 전극(13) 양측의 실리콘 기판(11) 표면내에 LDD(Lightly Doped Drain) 영역(15)을 형성한다.Subsequently, lightly doped drain (LDD) regions are formed in the surface of the silicon substrate 11 on both sides of the gate electrode 13 of the cell region by implanting low concentration impurity ions onto the entire surface using the patterned first photoresist 14 as a mask. (15) is formed.

도 1c에 도시한 바와같이 상기 제 1 포토레지스트(14)를 제거하고 상기 실리콘 기판(11)의 전면에 제 2 포토레지스트(16)를 도포한 후, 상기 제 2 포토레지스트(16)가 셀 영역에만 남도록 노광 및 현상공정으로 패터닝한다.After removing the first photoresist 14 and applying the second photoresist 16 to the entire surface of the silicon substrate 11 as shown in FIG. 1C, the second photoresist 16 is formed in the cell region. Patterning is performed in the exposure and development process so as to remain.

이어, 상기 패터닝된 제 2 포토레지스트(16)를 마스크로 이용하여 고농도 불순물 이온주입을 실시하여 상기 주변 회로 영역의 게이트 전극(13) 양측의 실리콘 기판(11) 표면내에 고농도 불순물 확산영역(17)을 형성한다.Subsequently, a high concentration of impurity ions are implanted using the patterned second photoresist 16 as a mask, so that a high concentration of impurity diffusion region 17 is formed in the surface of the silicon substrate 11 on both sides of the gate electrode 13 of the peripheral circuit region. To form.

도 1d에 도시한 바와같이 상기 제 2 포토레지스트(16)를 제거하고, 상기 게이트 전극(13)을 포함한 실리콘 기판(11)의 전면에 절연막을 형성한 후, 에치백 공정을 실시하여 상기 각 게이트 전극(13)의 양측면에 절연막 측벽(18)을 형성한다.As shown in FIG. 1D, the second photoresist 16 is removed, an insulating film is formed on the entire surface of the silicon substrate 11 including the gate electrode 13, and then an etch back process is performed to perform the respective gates. An insulating film sidewall 18 is formed on both sides of the electrode 13.

이어, 상기 게이트 전극(13) 및 절연막 측벽(18)을 마스크로 이용하여 상기 실리콘 기판(11)의 전면에 고농도 불순물 이온주입 공정을 실시하여 상기 게이트 전극(13)의 양측 실리콘 기판(11) 표면내에 소오스/드레인 불순물 확산영역(19)을 형성한다.Subsequently, a high concentration impurity ion implantation process is performed on the entire surface of the silicon substrate 11 using the gate electrode 13 and the insulating film sidewall 18 as a mask, so that both surfaces of the silicon substrate 11 of the gate electrode 13 are formed. The source / drain impurity diffusion region 19 is formed in the inside.

도 1e에 도시한 바와같이 상기 소오스/드레인 불순물 확산영역(19)이 형성된 실리콘 기판(11)의 전면에 CVD 산화막(Chemical Vapor Deposition Oxide)(20)을 형성하고, 상기 CVD 산화막(20)을 사진석판술 및 식각공정으로 상기 주변회로 영역에만 남도록 선택적으로 제거한다.As shown in FIG. 1E, a CVD oxide film 20 is formed on the entire surface of the silicon substrate 11 on which the source / drain impurity diffusion region 19 is formed, and the CVD oxide film 20 is photographed. Lithography and etching processes are selectively removed to remain only in the peripheral circuit area.

이어, 상기 실리콘 기판(11)의 전면에 고융점금속을 증착하고, 열처리 공정을 실시하여 상기 셀 영역의 게이트 전극(13)과 실리콘 기판(11)의 계면에 살리사이드막(21)을 형성한다.Subsequently, a high melting point metal is deposited on the entire surface of the silicon substrate 11 and a heat treatment process is performed to form a salicide film 21 at an interface between the gate electrode 13 and the silicon substrate 11 in the cell region. .

여기서 상기 고융점 금속을 상기 실리콘 기판(11)의 전면에 증착하여 열처리 공정을 실시하여 상기 실리콘 기판(11) 및 게이트 전극(13) 계면에 살리사이드막(21)을 형성하고, 나머지 부분의 고융점 금속을 제거한다.Here, the high melting point metal is deposited on the entire surface of the silicon substrate 11 to perform a heat treatment process to form a salicide layer 21 at the interface between the silicon substrate 11 and the gate electrode 13, and the high portion of the remaining portion is formed. Remove the melting point metal.

그러나 이와 같은 종래의 반도체 소자의 제조방법에 있어서 기판의 전면에 산화막을 형성하고 내부회로 영역을 블록킹(Blocking)하도록 산화막을 식각하는 추가 공정에 의해 살리사이드막의 특성을 약화시키는 문제점이 있었다.However, in the conventional method of manufacturing a semiconductor device, there is a problem in that the salicide film is weakened by an additional process of forming an oxide film on the entire surface of the substrate and etching the oxide film to block the internal circuit region.

본 발명은 상기와 같은 문제점을 해결하기 위해 안출한 것으로 살리사이드막의 특성 저하를 방지하는데 적당한 반도체 소자의 제조방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above problems, and an object thereof is to provide a method of manufacturing a semiconductor device suitable for preventing the degradation of the salicide film.

도 1a 내지 도 1e는 종래의 반도체 소자의 제조방법을 나타낸 공정단면도1A through 1E are cross-sectional views illustrating a method of manufacturing a conventional semiconductor device.

도 2a 내지 도 2g는 본 발명에 의한 반도체 소자의 제조방법을 나타낸 공정단면도2A to 2G are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

31 : 실리콘 기판 32 : 게이트 절연막31 silicon substrate 32 gate insulating film

33 : 게이트 전극 34 : 제 1 포토레지스트33 gate electrode 34 first photoresist

35 : LDD 영역 36 : 제 2 포토레지스트35 LDD region 36 second photoresist

37 : 고농도 불순물 영역 38 : 절연막37 high concentration impurity region 38 insulating film

38a : 제 1 측벽 절연막 38b : 제 2 측벽 절연막38a: first sidewall insulating film 38b: second sidewall insulating film

39 : 제 3 포토레지스트 40 : 불순물 도핑 영역39: third photoresist 40: impurity doped region

41 : 소오스/드레인 불순물 영역 42 : 산화막41 source / drain impurity region 42 oxide film

43 : 살리사이드막43: salicide film

상기와 같은 목적을 달성하기 위한 본 발명에 의한 반도체 소자의 제조방법은 셀 영역과 주변회로 영역으로 정의된 실리콘 기판상의 일정영역에 각각 게이트 절연막 및 게이트 전극을 형성하는 단계와, 상기 셀 영역의 게이트 전극 양측의 실리콘 기판 표면내에 저농도 불순물 영역을 형성하고 상기 주변회로 영역의 게이트 전극 양측의 실리콘 기판 표면내에 고농도 불순물 영역을 형성하는 단계와, 상기 셀 영역의 게이트 전극 양측면에 제 1 절연막 측벽 및 주변회로 영역의 전면에 절연막을 형성하는 단계와, 상기 셀 영역의 게이트 전극 및 실리콘 기판 표면에 불순물 도핑영역을 형성하는 단계와, 상기 주변회로 영역의 절연막을 에치백하여 게이트 전극 양측면에 제 2 절연막 측벽을 형성하는 단계와, 상기 각 게이트 전극 양측의 실리콘 기판 표면에 소오스/드레인 불순물 확산영역을 형성하는 단계와, 상기 실리콘 기판의 전면에 산소 분위기에서 RTA 처리를 실시하는 단계와, 그리고 상기 셀 영역의 불순물 도핑 영역에 살리사이드막을 형성하는 단계를 포함하여 형성함을 특징으로 한다.A method of manufacturing a semiconductor device according to the present invention for achieving the above object comprises the steps of forming a gate insulating film and a gate electrode in a predetermined region on the silicon substrate defined by the cell region and the peripheral circuit region, respectively, the gate of the cell region Forming a low concentration impurity region in the silicon substrate surfaces on both sides of the electrode and forming a high concentration impurity region in the silicon substrate surfaces on both sides of the gate electrode of the peripheral circuit region, and forming a first insulating film sidewall and a peripheral circuit on both sides of the gate electrode of the cell region. Forming an insulating film on the entire surface of the region, forming an impurity doped region on the gate electrode and the silicon substrate surface of the cell region, and etching back the insulating film of the peripheral circuit region to form second sidewall sidewalls on both sides of the gate electrode. Forming a surface of the silicon substrate on both sides of the gate electrode; Forming a source / drain impurity diffusion region, subjecting the silicon substrate to an RTA treatment in an oxygen atmosphere, and forming a salicide film in the impurity doped region of the cell region. It features.

이하, 첨부된 도면을 참고하여 본 발명에 의한 반도체 소자의 제조방법을 상세히 설명하면 다음과 같다.Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2g는 본 발명에 의한 반도체 소자의 제조방법을 나타낸 공정단면도이다.2A to 2G are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.

도 2a에 도시한 바와같이 셀 영역과 주변회로 영역으로 정의된 실리콘 기판(31)상에 게이트 절연막(32) 및 게이트 전극용 폴리 실리콘을 차례로 형성하고, 사진석판술 및 식각공정으로 상기 폴리 실리콘 및 게이트 절연막(32)을 선택적으로 제거하여 셀 영역과 주변회로 영역에 각각 게이트 전극(33)을 형성한다.As shown in FIG. 2A, the gate insulating layer 32 and the polysilicon for the gate electrode are sequentially formed on the silicon substrate 31 defined by the cell region and the peripheral circuit region, and the polysilicon and the photolithography and etching processes are sequentially formed. The gate insulating layer 32 is selectively removed to form the gate electrode 33 in the cell region and the peripheral circuit region, respectively.

도 2b에 도시한 바와같이 상기 게이트 전극(33)을 포함한 실리콘 기판(31)의 전면에 제 1 포토레지스트(34)를 도포한 후, 상기 주변회로 영역에만 상기 제 1 포토레지스트(34)가 남도록 노광 및 현상공정으로 패터닝한다.As shown in FIG. 2B, after the first photoresist 34 is coated on the entire surface of the silicon substrate 31 including the gate electrode 33, the first photoresist 34 remains only in the peripheral circuit region. Patterning is performed by exposure and development.

이어, 상기 패터닝된 제 1 포토레지스트(34)를 마스크로 이용하여 전면에 저농도 불순물 이온을 주입하여 상기 셀 영역의 게이트 전극(33) 양측의 실리콘 기판(31) 표면내에 LDD(Lightly Doped Drain) 영역(35)을 형성한다.Subsequently, lightly doped drain (LDD) regions are formed in the surface of the silicon substrate 31 on both sides of the gate electrode 33 of the cell region by implanting low concentration impurity ions into the entire surface using the patterned first photoresist 34 as a mask. (35) is formed.

도 2c에 도시한 바와같이 상기 제 1 포토레지스트(34)를 제거하고, 상기 실리콘 기판(31)의 전면에 제 2 포토레지스트(36)를 도포한 후, 상기 제 2 포토레지스트(36)가 셀 영역에만 남도록 노광 및 현상공정으로 패터닝한다.As shown in FIG. 2C, after the first photoresist 34 is removed and the second photoresist 36 is applied to the entire surface of the silicon substrate 31, the second photoresist 36 is formed into a cell. Patterning is performed by exposure and development so that only the region remains.

이어, 상기 패터닝된 제 2 포토레지스트(36)를 마스크로 이용하여 고농도 불순물 이온주입을 실시하여 상기 주변 회로 영역의 게이트 전극(33) 양측의 실리콘 기판(31) 표면내에 고농도 불순물 확산영역(37)을 형성한다.Subsequently, high concentration impurity ion implantation is performed using the patterned second photoresist 36 as a mask to form a high concentration impurity diffusion region 37 in the surface of the silicon substrate 31 on both sides of the gate electrode 33 of the peripheral circuit region. To form.

도 2d에 도시한 바와같이 상기 제 2 포토레지스트(36)를 제거하고, 상기 게이트 전극(33)을 포함한 실리콘 기판(31)의 전면에 절연막(38)을 형성한다.As shown in FIG. 2D, the second photoresist 36 is removed, and an insulating film 38 is formed on the entire surface of the silicon substrate 31 including the gate electrode 33.

이어, 상기 절연막(38)상에 제 3 포토레지스트(39)를 도포한 후, 상기 주변회로 영역에만 남도록 노광 및 현상공정으로 패터닝한다.Subsequently, after the third photoresist 39 is coated on the insulating layer 38, the third photoresist 39 is patterned by an exposure and development process so as to remain only in the peripheral circuit region.

도 2e에 도시한 바와같이 상기 패터닝된 제 3 포토레지스트(39)를 마스크로 이용하여 상기 셀 영역의 절연막(38)의 전면에 에치백 공정을 실시하여 상기 셀 영역의 게이트 전극(33)의 양측면에 제 1 측벽 절연막(38a)을 형성한다.As shown in FIG. 2E, using the patterned third photoresist 39 as a mask, an etch back process is performed on the entire surface of the insulating film 38 in the cell region, so that both sides of the gate electrode 33 in the cell region are formed. The first sidewall insulating film 38a is formed in the film.

이어, 상기 제 3 포토레지스트(39)를 제거하고, 상기 주변회로 영역에 형성된 절연막(38)을 마스크로하여 상기 셀 영역의 전면에 암모니아(NH3) 분위기에서 열처리 공정을 실시하여 상기 게이트 전극(33) 및 실리콘 기판(31)의 표면에 불순물 도핑 영역(40)을 형성한다.Subsequently, the third photoresist 39 is removed, and a heat treatment process is performed on the entire surface of the cell region in an ammonia (NH 3 ) atmosphere by using the insulating film 38 formed in the peripheral circuit region as a mask. 33 and the impurity doped region 40 are formed on the surface of the silicon substrate 31.

도 2f에 도시한 바와같이 상기 실리콘 기판(31)의 전면에 제 4 포토레지스트(도면에 도시하지 않음)를 도포한 후, 셀 영역에만 남도록 패터닝하고, 패터닝된 제 4 포토레지스트를 마스크로 이용하여 상기 주변회로 영역의 절연막(38)을 에치백하여 상기 주변회로의 게이트 전극(33)양측면에 제 2 측벽 절연막(38b)을 형성한다.As shown in FIG. 2F, a fourth photoresist (not shown) is applied to the entire surface of the silicon substrate 31, and then patterned to remain only in the cell region, using the patterned fourth photoresist as a mask. The insulating layer 38 of the peripheral circuit region is etched back to form second sidewall insulating layers 38b on both sides of the gate electrode 33 of the peripheral circuit.

이어, 상기 게이트 전극(33)을 마스크로 이용하여 상기 실리콘 기판(31)의 전면에 고농도 불순물 이온을 주입하여 상기 게이트 전극(33) 양측의 실리콘 기판(31) 표면내에 소오스/드레인 불순물 확산영역(41)을 형성한다.Subsequently, a high concentration of impurity ions are implanted into the entire surface of the silicon substrate 31 using the gate electrode 33 as a mask, so that source / drain impurity diffusion regions (S / D impurity diffusion regions) are formed in the surface of the silicon substrate 31 on both sides of the gate electrode 33. 41).

도 2g에 도시한 바와같이 상기 소오스/드레인 불순물 확산영역(41)이 형성된 실리콘 기판(31)에 산소(O2)분위기에서 RTA(Rapid Thermal Annealing) 처리를 실시하여 상기 주변회로 영역의 게이트 전극(33) 및 실리콘 기판(31)의 표면에 산화막(42)을 형성한다.As shown in FIG. 2G, a RTA (Rapid Thermal Annealing) treatment is performed on an silicon (O 2 ) atmosphere in a silicon substrate 31 having the source / drain impurity diffusion region 41 formed therein. 33 and an oxide film 42 on the surface of the silicon substrate 31.

여기서 상기 산소 분위기에서 RTA 처리를 실시할 때 상기 주변회로 영역의 게이트 전극(33) 및 실리콘 기판(31)의 표면에 자연적으로 산화막(42)이 성장된다.When the RTA process is performed in the oxygen atmosphere, an oxide film 42 is naturally grown on the surfaces of the gate electrode 33 and the silicon substrate 31 in the peripheral circuit region.

이어, 상기 실리콘 기판(31)의 전면에 고융점금속(도면에 도시하지 않음)을 증착하고 열처리 공정을 실시하여 상기 셀 영역의 게이트 전극(33) 및 실리콘 기판(31)의 표면에 살리사이드막(43)을 형성하고, 상기 게이트 전극(33) 및 실리콘 기판(31)과 반응하지 않는 고융점금속을 제거한다.Subsequently, a high melting point metal (not shown) is deposited on the entire surface of the silicon substrate 31 and a heat treatment process is performed to form a salicide film on the surface of the gate electrode 33 and the silicon substrate 31 in the cell region. 43 is formed, and the high melting point metal which does not react with the gate electrode 33 and the silicon substrate 31 is removed.

여기서 상기 주변회로 영역은 상기 산화막(42)에 의해 살리사이드막(43)이 형성되는 것을 방지한다.The peripheral circuit region prevents the salicide layer 43 from being formed by the oxide layer 42.

이상에서 설명한 바와같이 본 발명에 의한 반도체 소자의 제조방법에 있어서 내부회로 영역을 블록킹하는 산화막의 형성하는 공정을 생략함으로써 공정을 감소화 시키고, 살리사이드막의 특성 저하를 방지할 수 있는 효과가 있다.As described above, in the method of manufacturing a semiconductor device according to the present invention, the step of eliminating the step of forming the oxide film blocking the internal circuit region can be reduced to reduce the process and prevent the degradation of the salicide film.

Claims (3)

셀 영역과 주변회로 영역으로 정의된 실리콘 기판상의 일정영역에 각각 게이트 절연막 및 게이트 전극을 형성하는 단계; 상기 셀 영역의 게이트 전극 양측의 실리콘 기판 표면내에 저농도 불순물 영역을 형성하고 상기 주변회로 영역의 게이트 전극 양측의 실리콘 기판 표면내에 고농도 불순물 영역을 형성하는 단계; 상기 셀 영역의 게이트 전극 양측면에 제 1 절연막 측벽 및 주변회로 영역의 전면에 절연막을 형성하는 단계; 상기 셀 영역의 게이트 전극 및 실리콘 기판 표면에 불순물 도핑영역을 형성하는 단계; 상기 주변회로 영역의 절연막을 에치백하여 게이트 전극 양측면에 제 2 절연막 측벽을 형성하는 단계; 상기 각 게이트 전극 양측의 실리콘 기판 표면에 소오스/드레인 불순물 확산영역을 형성하는 단계; 상기 실리콘 기판의 전면에 산소 분위기에서 RTA 처리를 실시하는 단계; 상기 셀 영역의 불순물 도핑 영역에 살리사이드막을 형성하는 단계를 포함하여 형성함을 특징으로 하는 반도체 소자의 제조방법.Forming a gate insulating film and a gate electrode in predetermined regions on the silicon substrate defined by the cell region and the peripheral circuit region, respectively; Forming a low concentration impurity region in the silicon substrate surface on both sides of the gate electrode of the cell region and forming a high concentration impurity region in the silicon substrate surface on both sides of the gate electrode of the peripheral circuit region; Forming an insulating film on both sides of the first insulating film sidewall and the peripheral circuit area on both sides of the gate electrode of the cell area; Forming an impurity doped region on the gate electrode and the silicon substrate surface of the cell region; Etching back the insulating film in the peripheral circuit region to form second insulating film sidewalls on both sides of the gate electrode; Forming a source / drain impurity diffusion region on a surface of the silicon substrate on both sides of each gate electrode; Performing RTA treatment on an entire surface of the silicon substrate in an oxygen atmosphere; Forming a salicide film in the impurity doped region of the cell region. 제 1 항에 있어서, 상기 불순물 도핑영역은 NH3분위기에서 열처리를 실시하면 질소(N) 이온이 도핑되어 형성함을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, wherein the impurity doped region is formed by doping nitrogen (N) ions when heat-treated in an NH 3 atmosphere. 제 1 항에 있어서, 상기 RTA 처리할 때 상기 주변회로 영역의 게이트 전극 및 실리콘 기판의 표면에 산화막이 동시에 형성됨을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, wherein an oxide film is simultaneously formed on a surface of the gate electrode and the silicon substrate of the peripheral circuit region during the RTA process.
KR1019970025837A 1997-06-19 1997-06-19 Process for fabricating semiconductor device KR100236046B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019970025837A KR100236046B1 (en) 1997-06-19 1997-06-19 Process for fabricating semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019970025837A KR100236046B1 (en) 1997-06-19 1997-06-19 Process for fabricating semiconductor device

Publications (2)

Publication Number Publication Date
KR19990002276A KR19990002276A (en) 1999-01-15
KR100236046B1 true KR100236046B1 (en) 1999-12-15

Family

ID=19510281

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019970025837A KR100236046B1 (en) 1997-06-19 1997-06-19 Process for fabricating semiconductor device

Country Status (1)

Country Link
KR (1) KR100236046B1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100322891B1 (en) * 1999-12-30 2002-02-08 박종섭 Method For Manufacturing The Gate Electrode Of Semiconductor Device
KR100435897B1 (en) * 2001-12-27 2004-06-12 동부전자 주식회사 Optional salicide layer forming method of semiconductor device

Also Published As

Publication number Publication date
KR19990002276A (en) 1999-01-15

Similar Documents

Publication Publication Date Title
US5918129A (en) Method of channel doping using diffusion from implanted polysilicon
US5817563A (en) Method for fabricating an LDD transistor
KR100236046B1 (en) Process for fabricating semiconductor device
KR100223736B1 (en) Method of manufacturing semiconductor device
KR100670039B1 (en) Method for manufacturing polycrystalline silicon thin film transistor having LED region
KR100702118B1 (en) Method for manufacturing of semiconductor device
KR19990070036A (en) Manufacturing method of semiconductor device
KR100339419B1 (en) Method for manufacturing transistor having ldd structure
KR19990050035A (en) How to form a transistor
KR100311502B1 (en) Method for manufacturing semiconductor device the same
KR100215871B1 (en) Method for fabricating semiconductor device
KR100268865B1 (en) Method for fabricating semiconductor device
KR100304975B1 (en) Semiconductor device and method for fabricating the same
KR100819686B1 (en) Method for manufacturing a transistor
JP3311082B2 (en) Method for manufacturing semiconductor device
KR100250686B1 (en) Manufacturing method of a semiconductor device
KR100325444B1 (en) Method for fabricating metal oxide semiconductor transistor of low doping drain structure
KR20010045138A (en) Manufacturing method for semiconductor device
KR100503379B1 (en) Method for fabricating gate electrode of semiconductor
KR100202642B1 (en) Method for manufacturing mos transistor
KR0144246B1 (en) Transistor Manufacturing Method
KR100231479B1 (en) Method of fabricating field transistor
KR950008259B1 (en) Making method of ldd for semiconductor devices
KR101004812B1 (en) Method for forming silicide of semiconductor device
KR20000050587A (en) Method for forming gate oxide layer of semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20070827

Year of fee payment: 9

LAPS Lapse due to unpaid annual fee