JP3311082B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device having an LDD structure in a MOS type semiconductor integrated circuit.

[0002]

2. Description of the Related Art In a MOS type semiconductor device, an LDD (Lightly Doped Drain) is used as a structure for relaxing a drain electric field and increasing hot carrier resistance.
n) Structures are known. The most common method of forming this LDD structure is to first form a low-concentration impurity region by ion-implanting a low-concentration impurity into a semiconductor substrate using a gate electrode as a mask, and then form a side wall on the gate electrode. After that, using the gate electrode and the side wall as a mask, impurities are ion-implanted into the semiconductor substrate to form a high-concentration impurity region.

FIG. 2 shows the above-mentioned conventional method. In this conventional example, first, as shown in FIG. 2A, a silicon oxide film as a gate insulating film is formed on the surface of a silicon semiconductor substrate 1 by thermal oxidation. Then, a polycrystalline silicon film is deposited on the entire surface, and the polycrystalline silicon film is processed into a pattern of the gate electrode 2. Then, using the gate electrode 2 as a mask, a low-concentration Impurities are introduced by ion implantation.

Next, as shown in FIG. 2B, a silicon oxide film 10 is deposited on the entire surface of the semiconductor substrate 1 on which the low concentration diffusion layer 8 is formed by a method such as CVD.

Then, as shown in FIG. 2C, the entire surface of the silicon oxide film 10 is anisotropically etched by a method such as RIE to form an oxide film sidewall 11 on the gate electrode 2.

Next, as shown in FIG. 2D, high concentration impurities are introduced into the silicon semiconductor substrate 1 by ion implantation using the gate electrode 2 and the oxide film side wall 11 as a mask.

After that, a heat treatment is performed for several minutes at a high temperature in order to recover the defect caused by the ion implantation.

According to the above-described method, as shown in FIG. 2E, the portion having the oxide film side wall 11 becomes the low concentration diffusion layer 8 and the portion having no oxide film side wall 11 becomes the high concentration diffusion layer 9, thereby forming the LDD. A structure is formed.

[0009]

However, in recent years, with the miniaturization of semiconductor devices, the shallow junctions of the source / drain diffusion layers have been required. It is difficult to control the implantation energy for the shallow junction, and the implantation defects caused by the two ion implantations are suppressed while suppressing the junction depth of the source / drain diffusion layers from becoming deeper due to diffusion. There is a problem that it is difficult to sufficiently recover by a heat treatment at a high temperature for a short time.

It is an object of the present invention to provide a method of manufacturing a semiconductor device having a shallow junction corresponding to miniaturization of a semiconductor element by reducing the occurrence of defects due to ion implantation in an LDD structure forming step. .

[0011]

According to a method of manufacturing a semiconductor device of the present invention, a first insulating film and a conductor film are sequentially formed on a semiconductor substrate, and the first and second insulating films are patterned. Forming a second insulating film and a first polycrystalline silicon film sequentially on the entire surface; and performing anisotropic etching of the first polycrystalline silicon film to form a gate electrode. Side walls of the polycrystalline silicon film are formed on both sides of the gate electrode via the second insulating film, and a residual film is formed on a portion of the second insulating film where the first polycrystalline silicon film has been removed. Etching to a predetermined depth to such an extent that a second polycrystalline silicon film is formed on the entire surface; introducing an impurity into the second polycrystalline silicon film and the side wall; Polycrystalline silicon film and said side Characterized by comprising a step of diffusing into the semiconductor substrate by heat treatment impurities introduced.

[0012]

According to the present invention, in the etching step for forming the side wall of the gate electrode, the second insulating film deposited on the semiconductor substrate after the formation of the gate electrode becomes thicker in the part having the side wall and thinner in the part without the side wall. Become. Therefore, when impurities are implanted later using the polycrystalline silicon film deposited on the semiconductor substrate as a mask, the impurity concentration becomes constant at the interface between the second insulating film and the polycrystalline silicon film, but the impurities are removed by a subsequent heat treatment. When thermal diffusion is performed in the second insulating film, the substrate surface concentration of impurities depends on the thickness of the second insulating film.
By further diffusing this impurity into the semiconductor substrate, an LDD structure can be formed in which a portion having a side wall becomes a low concentration diffusion layer and a portion having no side wall becomes a high concentration diffusion layer.

As a result, in the present invention, when forming an LDD structure in a semiconductor substrate, impurities are introduced by thermal diffusion, so that a shallow junction with a small leak current can be formed without generating an injection defect in the semiconductor substrate. Can be formed.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention applied to the manufacture of a MOS transistor will be described below with reference to FIG. 1, the same components as those of the conventional example shown in FIG. 2 are denoted by the same reference numerals.

In this embodiment, as shown in FIG. 1A, a silicon oxide film having a thickness of about 10 to 20 nm is formed on the surface of a silicon semiconductor substrate 1 by thermal oxidation. Then, a polycrystalline silicon film having a thickness of about 150 to 300 nm is deposited by a method such as CVD. Thereafter, patterning of the silicon oxide film and the polycrystalline silicon film formed on the silicon semiconductor substrate 1 is performed by a method such as lithography to form the gate electrode 2.

Next, as shown in FIG. 1B, an insulating film 3 such as a silicon oxide film or a silicon nitride film is formed on the entire surface of the silicon semiconductor substrate 1 to a thickness of about 10 to 30 nm by a method such as CVD. Is deposited.

Next, as shown in FIG. 1C, the thickness of the polycrystalline silicon film 4 is reduced to 300 to 300 by a method such as CVD.
It is deposited to a thickness of about 400 nm.

Next, as shown in FIG. 1D, the polysilicon film 4 is anisotropically etched by a method such as RIE to form polysilicon sidewalls 5 on both sides of the gate electrode 2. At this time, the insulating film 3 is etched in a portion where the polycrystalline silicon film 4 is completely removed, and the thickness of the remaining film due to the etching of the insulating film 3 is set to 5 nm or less.

Next, as shown in FIG. 1E, a polycrystalline silicon film 6 is deposited on the entire surface of the silicon semiconductor substrate 1 to a thickness of about 200 to 350 nm by a method such as CVD.

Next, as shown in FIG. 1F, impurity ions are implanted by the ion beam 7. When arsenic is implanted as an impurity, the acceleration energy is 40 to 70 k.
eV, dose amount of about 5 × 10 ¹⁵ to 1 × 10 ¹⁶ / cm ² ,
When boron fluoride is implanted as an impurity, the acceleration energy is 30 to 50 keV and the dose is 5 × 10 ¹⁵ to 1 × 10 5
The condition is set to about ¹⁶ / cm ² so that the peak concentration of the impurity comes to the surface of the silicon semiconductor substrate 1.

Next, as shown in FIG. 1G, heat treatment is performed by lamp annealing at a temperature of about 1000 to 1100 ° C. for a time of about 10 to 30 seconds. At this time, the ion-implanted impurity diffuses into the silicon semiconductor substrate 1, but the portion of the insulating film 3 having the polycrystalline silicon sidewall 5 is thicker than the portion of the insulating film 3 having no polycrystalline silicon sidewall 5. When impurities are diffused through the insulating film 3, the impurity concentration on the surface of the silicon semiconductor substrate 1 is lower in the thicker portion of the insulating film 3 than in the thinner portion of the insulating film 3, so that the polycrystalline silicon side wall is formed. 5, the low-concentration diffusion layer 8 is formed in the portion where the polycrystalline silicon side wall 5 is not formed.

[0022]

According to the present invention, an LDD using thermal diffusion is provided.
In a method of manufacturing a semiconductor device having a structure, a shallow junction having good junction characteristics can be formed without generating defects due to ion implantation.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing a manufacturing process of an LDD structure according to one embodiment of the present invention.

FIG. 2 is a schematic sectional view showing a manufacturing process of a conventional LDD structure.

[Explanation of symbols]

 Reference Signs List 1 silicon semiconductor substrate 2 gate electrode 3 insulating film 4 polycrystalline silicon film 5 polycrystalline silicon sidewall 6 polycrystalline silicon film 7 ion beam 8 low concentration diffusion layer 9 high concentration diffusion layer

Claims (1)

(57) [Claims] A step of sequentially forming a first insulating film and a conductor film on a semiconductor substrate and patterning them to form a gate electrode; and forming a second insulating film and a first polycrystal on the entire surface. Forming a silicon film sequentially, and anisotropically etching the first polycrystalline silicon film,
Side walls of the polycrystalline silicon film are formed on both sides of the gate electrode with the second insulating film interposed therebetween, and the remaining portion of the second insulating film where the first polycrystalline silicon film has been removed has a remaining film. Etching to a predetermined depth to such an extent that it is formed; forming a second polycrystalline silicon film over the entire surface; introducing an impurity into the second polycrystalline silicon film and the side wall; Diffusing the impurities introduced into the polycrystalline silicon film and the side walls into the semiconductor substrate by heat treatment.