JPH04287332A - Manufacture of semiconductor element - Google Patents

Abstract

PURPOSE:To reduce crystal defect, decrease reverse bias leak current, and improve the withstand voltage of a junction, in the manufacturing method of a semiconductor device. CONSTITUTION:An amorphous layer 14 is formed on both sides of a gate 13 formed on a first conductivity type semiconductor substrate 11 via a gate insulating film 12, by ion-implanting first impurities, which are innert and exert no influence upon the electric characteristics of a semiconductor device 1, in the upper layer of a semiconductor substrate 11. After second conductivity type impurities are ion-implanted in the amorphous layer 14, second impurities composed of one or more kinds out of carbon, nitrogen, oxygen and fluorine are ion-implanted in a crystal defect layer 15 generated on the substrate 11 side from the interface of the amorphous layer 14 and the substrate 11. Then the substrate 11 is heat-treated, and the second impurities are diffused. Thus the crystal defect layer 15 is reduced. At the same time, source drain diffusion layers 17, 18 are formed by diffusing the second conductivity type impurities, and the amorphous layer 14 is single-crystallized.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing semiconductor devices such as MOS transistors.

0002

2. Description of the Related Art Semiconductor devices have been miniaturized both horizontally and vertically with respect to a semiconductor substrate. A method of forming a shallow P+N junction between the source/drain diffusion layer and the semiconductor substrate by vertically miniaturizing the semiconductor substrate will be explained with reference to the manufacturing process diagram of FIG. In the figure, a method of manufacturing a semiconductor device 30 made of a P-channel transistor will be described. First, a gate insulating film 32 is formed on the upper surface of an N-type semiconductor substrate 31 . Subsequently, a gate 33 is placed on the upper surface of the gate insulating film 32.
form. Next, the gate 3 is passed through the gate insulating film 32.
Impurities such as silicon (Si+) are ion-implanted into the upper layer of the semiconductor substrate 31 on both sides of the semiconductor substrate 31 as ions inactive to the semiconductor substrate 31. Then, the upper layer of the semiconductor substrate 31 is made amorphous to form an amorphous layer 34. At this time,
A crystal defect layer 35 is generated closer to the semiconductor substrate 31 than the interface between the amorphous layer 34 and the semiconductor substrate 31.

Next, boron fluoride ions (BF2 + ) are ion-implanted as P-type impurities into the amorphous layer 34 to form a P-type ion-implanted layer 36 in the amorphous layer 34 .

[0004] Thereafter, a lamp annealing process is performed to convert the amorphous layer (double-dashed line) 34 into a single crystal. At the same time, boron (B
) is activated and diffused deeper than the amorphous layer 34, and P+
Source/drain diffusion layers 37 and 38 are formed. The source/drain diffusion layers 37 and 38 are formed to include a crystal defect layer 35.

[0005]

[Problems to be Solved by the Invention] However, in the above method for manufacturing a semiconductor device, since the crystal defect layer exists with a width in the depth direction, it is difficult to completely eliminate all the crystal defect layers in the source/drain diffusion layer. Difficult to include. For this reason, crystal defects in the crystal defect layer are applied to the junction depletion layer, making it impossible to sufficiently reduce reverse bias leakage current. As a result, leakage current occurs and the breakdown voltage of the junction is significantly reduced. The present invention has been made to solve the above problems, and an object of the present invention is to provide a method for manufacturing a semiconductor device having excellent breakdown voltage characteristics.

[0006]

[Means for Solving the Problems] The present invention has been made to achieve the above objects. That is, an inert first impurity that does not affect the electrical characteristics of the semiconductor device is ion-implanted into the upper layer of the semiconductor substrate on both sides of the gate formed on the upper surface of the semiconductor substrate of the first conductivity type via a gate insulating film. to form an amorphous layer. Next, impurities of the second conductivity type are ion-implanted into the amorphous layer at a position shallower than the depth of the amorphous layer. Next, one or more types of second impurities such as carbon, nitrogen, oxygen, or fluorine are ionized into crystal defect layers such as dislocations that occur closer to the semiconductor substrate than the interface between the amorphous layer and the semiconductor substrate. inject. Thereafter, the semiconductor substrate is heat-treated, a second impurity is diffused to reduce crystal defects in the crystal defect layer, a second conductivity type impurity is diffused to form a source/drain diffusion layer, and an amorphous layer is formed. Become a single crystal.

[0007]

[Operation] In the method for manufacturing a semiconductor device described above, one or more types of impurities such as carbon, nitrogen, oxygen, or fluorine are ion-implanted into the crystal defect layer, and then heat treatment is performed to remove the ion-implanted impurities. diffuses into the crystal defect layer and reduces crystal defects such as dislocations. Therefore, when a negative bias voltage is applied to the gate, the reverse bias leak current value becomes small.

[0008]

EXAMPLE An example of the present invention will be explained with reference to the manufacturing process diagram shown in FIG. The figure shows a method of manufacturing a P-channel MOS transistor as an example of the semiconductor device 1. First, in the first step, an element isolation region 2 is formed in the upper layer of a semiconductor substrate 11 made of first conductivity type (N type) single crystal silicon using a LOCOS method or the like.
, 3. These element isolation regions 2 and 3 are improved LOC
It is also possible to form by an OS method, a trench element isolation method, or the like. After exposing the surface of the semiconductor substrate 11 between the element isolation regions 2 and 3 by etching or the like, the surface of the semiconductor substrate 11 is oxidized by, for example, a thermal oxidation method, and a silicon oxide film is formed on the upper surface of the semiconductor substrate 11. Gate insulating film 1
form 2. Next, a poly-Si film (not shown) containing conductivity type impurities at a low concentration is formed on the upper surface of the gate insulating film 12 by, for example, chemical vapor deposition. After that, the poly
- Form the gate 13 with a Si film. Subsequently, silicon (Si+) is ion-implanted as a first impurity into the upper layer of the semiconductor substrate 11 on both sides of the gate 13 through the gate insulating film 12. In this ion implantation, for example, the ion implantation energy is 40 keV and the dose is 2 x 1015 cm-
This will be done under two conditions. Then, an amorphous layer 14 having a depth of approximately 90 nm is formed on the semiconductor substrate 11. In addition to Si+, the first impurity may be any impurity that does not ultimately affect the electrical characteristics of the semiconductor device 1. For example, it is also possible to use argon (Ar), germanium (Ge), etc. be. Further, when the amorphous layer 14 is formed, a crystal defect layer 15 having a width in the depth direction of approximately 50 nm is generated on the semiconductor substrate 11 side from the interface between the amorphous layer 14 and the semiconductor substrate 11.

In the second step, the amorphous layer 1 is implanted at a position shallower than the depth of the amorphous layer 14 by, for example, ion implantation.
4, for example, boron fluoride (BF) is used as a second conductivity type (P type) impurity for forming source/drain diffusion layers
2 +) is ion-implanted. In this ion implantation, for example, the ion implantation energy is 15 keV and the dose is 2.
The test was carried out under the conditions of x1015 cm-2. Then, the ion implantation layer 16 is formed so that the depth of the position where the concentration of boron ions (B+) is highest is about 20 nm. Note that, in addition to BF2 + , a P-type impurity such as boron (B+) can be used as the second conductivity type impurity.

In the third step, by ion implantation, carbon (
C+) is ion-implanted. This ion implantation is performed, for example, under the conditions that the ion implantation energy is 35 keV and the dose is 2×10 13 cm −2 . As the second impurity, one or more of carbon, nitrogen, oxygen, and fluorine can be used.

In the fourth step, for the semiconductor substrate 11,
Heat treatment is performed by lamp annealing at approximately 1000° C. for 15 seconds. Then, crystal defect layer 15 is reduced by ion-implanted carbon (C+). At the same time, the amorphous layer (14) is made into a single crystal, and the BF2 of the ion implantation layer 16 is
+ Boron (B) is diffused to a depth (the concentration of boron is 1
×1017/cm3) is approximately 120 nm
P+ source/drain diffusion layers 17 and 18 are formed. Note that the heat treatment can also be performed by laser annealing, electron beam annealing, etc. in addition to lamp annealing.

Next, as shown in FIG. 2, an interlayer insulating film 18 is formed on the entire surface on the gate 13 side, and a contact hole passing through the gate insulating film 12 is formed in the interlayer insulating film 19 on each P+ source/drain diffusion layer 17, 18. 20 and 21 are formed. At the same time, a contact hole 22 is formed in the interlayer insulating film 19 above the gate 13. and contact holes 20, 21
, 22, for example, an aluminum alloy film is formed on the upper surface of the interlayer insulating film 19 including the interlayer insulating film 19. Thereafter, by photolithography and etching, each source/drain diffusion layer 1 is formed through the contact holes 20 and 21 in the aluminum alloy film.
Source/drain electrodes 23 and 24 connected to the gate electrodes 7 and 18 are formed, and a gate electrode 25 connected to the gate 13 through the contact hole 22 is formed.

The current/voltage characteristics when a negative bias voltage is applied to the gate 13 of the semiconductor device 1 described in the above embodiment will be explained with reference to FIG. In the figure, the vertical axis represents reverse bias leak current, and the horizontal axis represents negative bias voltage. Further, the solid line in the figure shows the current/voltage characteristics of the semiconductor device 1 formed according to the above embodiment, and the broken line shows the current/voltage characteristics of the semiconductor device (30) formed by the method described in the conventional technique. The semiconductor device (30) is manufactured under the same manufacturing conditions as described in the above example except that the carbon ion implantation described in the third step is not performed. As shown in the figure, when the same negative bias voltage is applied, the reverse bias leak current value of the semiconductor device 1 is approximately 1/10 of the reverse bias leak current value of the semiconductor device (30). As a result, by performing the third step, the junction leakage characteristics of the semiconductor device 1 are improved.

In the above embodiment, a P-channel type MOS transistor has been explained as an example, but an N-channel type MOS transistor has been described.
It is also possible to improve the junction leakage characteristics of an S transistor in the same manner. In this case, a second conductivity type (P type) single crystal silicon substrate is used as the semiconductor substrate, and impurities forming the source/drain diffusion layer are of the first conductivity type (N type).
For example, impurities such as arsenic (As+) or phosphorus (P+) are used. Further, as the second impurity, the one described above is used.

[0015]

[Effects of the Invention] As explained above, according to the present invention,
Heat treatment is performed after ion-implanting one or more types of second impurities such as carbon, nitrogen, oxygen, or fluorine into a crystal defect layer that occurs on the semiconductor substrate side from the interface between the amorphous layer and the semiconductor substrate. Then, the second impurity is diffused into the crystal defect layer. Therefore, crystal defects in the crystal defect layer are reduced, and the reverse bias leakage current value is reduced. Therefore, junction leakage in the semiconductor device is reduced, and the withstand voltage of the junction can be improved.

[Brief explanation of the drawing]

FIG. 1 is a manufacturing process diagram of an example.

FIG. 2 is a manufacturing process diagram of an example.

FIG. 3 is an explanatory diagram of current/current characteristics.

FIG. 4 is a manufacturing process diagram of a conventional example.

[Explanation of symbols]

1 Semiconductor device 11 Semiconductor substrate 12 Gate insulating film 13 Gate 14 Amorphous layer 15 Crystal defect layer 17 Source/drain diffusion layer 18 Source/drain diffusion layer

Claims (1)

[Claims] Claim 1: An inert first layer that does not affect the electrical characteristics of the semiconductor device is formed in the upper layer of the semiconductor substrate on both sides of the gate formed on the upper surface of the semiconductor substrate of the first conductivity type with a gate insulating film interposed therebetween. a first step of ion-implanting an impurity to form an amorphous layer; a second step of ion-implanting a second conductivity type impurity into the amorphous layer; and a step of ion-implanting an impurity of a second conductivity type into the amorphous layer; a third step of ion-implanting a second impurity made of one or more of carbon, nitrogen, oxygen, or fluorine into a crystal defect layer generated on the side of the semiconductor substrate from the interface; and heat-treating the semiconductor substrate. , diffusing the second impurity to reduce crystal defects in the crystal defect layer, diffusing the second conductivity type impurity to form a source/drain diffusion layer, and forming the amorphous layer into a single crystal layer; A method for manufacturing a semiconductor device, characterized in that a fourth step of converting into a semiconductor device is performed in order.