JP3108927B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor device.

[Conventional technology]

When the channel length of the TR is shortened and the channel resistance is reduced, the resistance of the impurity diffusion layer forming the source / drain or the parasitic resistance such as the contact resistance between the source / drain region and the wiring material becomes a problem. Salicide technology has been proposed as a means for solving this problem.
Salicide refers to a structure in which silicide is selectively formed on the gate electrode and the source / drain, and the manufacturing method is as shown in FIGS. 2A and 2B. ), Silicide was formed.

Step 1 FIG. 2 (a) After forming an n-type well 202 on a part of a P-type silicon substrate 201 and forming an oxide film 203 for element isolation, a gate oxide film 204 and a gate electrode (polycrystalline silicon) 205 , An N-type region, a low-concentration n-type impurity diffusion layer 206 is formed, and a P-type region is formed with a low-concentration p-type impurity diffusion layer 207.

Next, after forming an insulating film side wall 208 and an ion implantation and permeation oxide film 209, high concentration arsenic ions are implanted into the Nch region, and annealing is performed in an electric furnace at 900 to 1000 ° C. to thereby form a high concentration n-type impurity. The diffusion layer 210 is formed. Further P
High concentration BF2 ions are implanted into the ch region, and annealing is performed at 1000-1100 ° C. for about 30 seconds using a halogen lamp to form a high concentration p-type impurity diffusion layer 214.

Step 2 FIG. 2 (b) After the oxide film for ion implantation is removed by etching with dilute hydrofluoric acid, titanium is formed on the entire surface by a 200-800 ° sputtering method, and annealing is performed at about 700 ° C. using a halogen lamp. At this time, the titanium on the gate electrode 204 and the high concentration impurity diffusion layers 210 and 214 becomes titanium silicide 212,
The titanium on the element isolation oxide film 202 and the insulating film sidewall 208 becomes titanium nitride. The titanium nitride is removed by etching with a mixed solution of ammonia and hydrogen peroxide, and annealing is performed at about 800 ° C. using a halogen lamp.

[Problems to be solved by the invention]

However, the conventional technique described above has a large problem particularly in manufacturing a semiconductor device having a PMOS structure. In the salicide technique, silicide is usually formed by a thermal reaction between metal and silicon formed by a sputtering method. P at the interface
The type impurity concentration is extremely reduced. As a result, silicide
The contact resistance of the p-type impurity diffusion layer increases, and significantly reduces the current driving capability of the transistor.

Therefore, the present invention is intended to solve such a problem, and an object of the present invention is to reduce the contact resistance between silicide and a p-type impurity diffusion layer, and to provide excellent current driving capability for both Nch and Pch. An object of the present invention is to provide a method of manufacturing a salicide-structured semiconductor device.

[Means for solving the problem]

A method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device having a salicide structure, comprising: forming a gate electrode on a semiconductor substrate via a gate oxide film; and forming a sidewall on a side surface of the gate electrode. Performing ion implantation of N-type high-concentration impurities for forming N-type source / drain regions; forming an N-type high-concentration impurity diffusion layer by first annealing; Depositing a metal film to be formed, selectively forming a silicide layer in a predetermined region of the gate electrode and the semiconductor substrate by second annealing, and forming a P-type source / drain region. Ion-implanting high-concentration impurities through the silicide layer, and performing third annealing using a halogen lamp to form a P-type high-concentration impurity diffusion layer. A step of forming, a characterized in that it has in this order.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a sectional view illustrating a manufacturing process of a semiconductor device according to the present invention.

Step 1 FIG. 1 (a) After forming an n-type well 102 on a part of a P-type silicon substrate 101 and forming an element isolation oxide film 103, a gate oxide film 104 and a gate electrode (polycrystalline silicon) 105. , An n-type impurity diffusion layer 106 is formed in the Nch region, and a p-type impurity diffusion layer 107 is formed in the Pch region.

Step 2 FIG. 1 (b) Insulating film sidewall 108, oxide film 1 for ion implantation transmission
After the formation of 09, high-concentration arsenic ions are implanted into the Nch region, and annealing (first annealing) is performed at 900 to 1000 ° C. in an electric furnace to form a high-concentration n-type impurity diffusion layer 110.

Step 3 FIG. 1 (c) After the oxide film 109 for ion implantation and transmission is removed by etching with diluted hydrofluoric acid, titanium 111 is formed on the entire surface by a 200-800 ° sputtering method.

Step 4 FIG. 1 (d) Anneal (second anneal) using a halogen lamp at around 700 degrees. At this time, the gate electrode 105, the low concentration p-type impurity diffusion layer 107 and the high concentration n-type impurity
The titanium 111 of FIG. 10 becomes titanium silicide 112, and the element isolation oxide film 102 and the insulating film side wall 108
The upper titanium becomes titanium nitride 113.

Step 5 FIG. 1 (e) The titanium nitride 113 is removed by etching with a mixed solution of ammonia and hydrogen peroxide, and annealing is performed at about 800 ° C. using a halogen lamp.

Step 6 FIG. 1 (f) Ion implantation of high concentration BF2 (high concentration impurities forming source / drain regions) into the Pch region is performed, and annealing is performed at 1000-1100 ° C. for about 30 seconds using a halogen lamp (third annealing). ) To form a P-type high concentration impurity diffusion layer 114 immediately below titanium silicide.

〔The invention's effect〕

As described above, according to the present invention, a sufficiently low contact resistance can be obtained between the silicide and the p-type impurity diffusion layer because a high concentration of the p-type impurity exists at the interface between the titanium silicide and the p-type impurity diffusion layer. . As a result, there is a great effect that a transistor having excellent current driving capability can be provided.

[Brief description of the drawings]

1 (a) to 1 (f) are cross-sectional views showing the structure of each manufacturing process of a semiconductor device of the present invention. 2 (a) and 2 (b) are cross-sectional views showing the structure of each manufacturing process of a conventional semiconductor device. 101, 201 ... p-type silicon substrate 102, 202 ... n-type well 103, 203 ... oxide film for element isolation 104, 204 ... gate oxide film 105, 205 ... gate electrode (polycrystalline silicon) 106, 206 ... Low-concentration n-type impurity diffusion layers 107 and 207... Low-concentration p-type impurity diffusion layers 108 and 208... Insulating film sidewalls 109 and 209. Impurity diffusion layer (source / drain) 111: titanium 112, 212: titanium silicide 113: titanium nitride 114: high-concentration p-type impurity diffusion layer

──────────────────────────────────────────────────続 き Continued on the front page (58) Investigated field (Int.Cl. ⁷ , DB name) H01L 21/8238 H01L 21/28 301 H01L 21/336 H01L 27/092 H01L 29/78

Claims (1)

(57) [Claims] 1. A method of manufacturing a semiconductor device having a salicide structure, comprising: forming a gate electrode on a semiconductor substrate via a gate oxide film; forming a sidewall on a side surface of the gate electrode; Ion-implanting N-type high-concentration impurities for forming source / drain regions of the type, forming an N-type high-concentration impurity diffusion layer by first annealing, and forming a metal for forming a silicide layer. A step of depositing a film, a step of selectively forming a silicide layer in a predetermined region of the gate electrode and the semiconductor substrate by a second annealing, and a step of removing a P-type high concentration impurity for forming a P-type source / drain region. A step of implanting ions through the silicide layer; and a step of forming a P-type high-concentration impurity diffusion layer by third annealing using a halogen lamp. The method of manufacturing a semiconductor device, characterized in that it comprises in the order.