JP3244066B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a field-effect transistor, and more particularly, to a method for manufacturing a field-effect transistor having a reduced source-drain junction depth.

[0002]

2. Description of the Related Art A conventional field-effect transistor (hereinafter referred to as "the field effect transistor")
A manufacturing method of the “FET” as appropriate) will be described with reference to FIG.

First, as shown in FIG. 4A, a silicon oxide film 2 (4 nm thick) is formed on a semiconductor substrate 1 by a thermal oxidation method, and then a polycrystalline silicon 3 (200 nm thick) is formed thereon.
m).

Next, a photoresist (not shown) is provided on the polycrystalline silicon film 3, and the polycrystalline silicon film 3 and the silicon oxide film 2 are patterned using the photoresist as a mask to form a gate electrode. Subsequently, a silicon oxide film 4 is formed as a sidewall, and a through oxide film (not shown) is further formed (FIG. 4B). Next, boron ions are implanted into the entire surface via the through oxide film (FIG. 4).
(C)), impurities are introduced into the gate electrode, and the source / drain regions 6 are formed (FIG. 4D). Boron implantation conditions are, for example, 4 KeV, 3 × 10 ¹⁵ atoms / c
m ² .

After that, lamp annealing is performed to activate the gate electrode and the source / drain regions 6. The conditions for lamp annealing are usually at a substrate temperature of 900 to 1000 ° C.
And the annealing time is 5 to 10 seconds.

[0006] As described above, the FET is completed.

[0007]

However, in the above prior art, it was difficult to sufficiently diffuse and activate impurities in the gate electrode while reducing the source-drain junction depth.

In order to reduce the junction depth of the source / drain, the ion implantation energy of the dopant is reduced, and the thermal history of lamp annealing is reduced (that is, the heating temperature is reduced or the heating time is shortened). Is very effective. However, according to this method, the dopant cannot be diffused to the lower layer of the gate electrode, and the lower layer of the gate electrode tends to be depleted during the operation of the field effect transistor. This depletion of the gate electrode is equivalent to increasing the thickness of the gate oxide film, and thus hinders the high speed and high integration of the field effect transistor.

On the contrary, in order to introduce the dopant deeply into the lower layer of the gate electrode, it is necessary to increase the ion implantation energy of the dopant or to increase the heat history of lamp annealing (that is, increase the heating temperature or increase the heating time). Is very effective. However, in this method, the source-drain junction depth becomes deep,
This will hinder high integration of the field effect transistor.

In order to solve this problem, it is conceivable that ion implantation into the gate electrode and ion implantation into the source-drain are performed separately, and heat treatment is also performed separately. However, in this method, the number of manufacturing steps is increased. There is a problem that the cost is increased.

SUMMARY OF THE INVENTION The present invention has been made in view of the above, and has as its object to realize an incompatible requirement of introducing a dopant to a layer below a gate electrode and reducing a junction depth between a source and a drain while suppressing an increase in cost. I do.

[0012]

According to the present invention, a first step of forming a gate oxide film and a polycrystalline silicon film on a semiconductor substrate in this order, and a step of forming a silicon source on the polycrystalline silicon film.
Silicon at a dose of 1 × 10 ¹² to 1 × 10 ¹⁵ atoms / cm ²
A second step of implanting atoms to introduce interstitial silicon, a third step of patterning the polycrystalline silicon film into a gate electrode shape, and a fourth step of performing heat treatment after ion implantation of impurities over the entire surface. And a method for manufacturing a semiconductor device.

[0013]

According to a reference example of the present invention , a first step of forming a gate oxide film and a polycrystalline silicon film on a semiconductor substrate in this order, and forming a silicon oxide film on the surface of the polycrystalline silicon film by a thermal oxidation method. A second step of forming an oxide film, a third step of patterning the polycrystalline silicon film into a gate electrode shape, and a fourth step of performing a heat treatment after ion-implanting impurities over the entire surface. A method for manufacturing a semiconductor device is provided.

In any of the above-described semiconductor device manufacturing methods, after the interstitial silicon is introduced into the polycrystalline silicon film in the second step, in the fourth step, the polycrystalline silicon film is transferred to the polycrystalline silicon film together with the silicon substrate surface. Impurities (dopants) are ion-implanted, and the impurities are diffused and activated by heat treatment. Here, thermal diffusion of the dopant in the polycrystalline silicon film forming the gate electrode is promoted by silicon atoms introduced between lattices by ion implantation. On the other hand, since interstitial silicon is not introduced into the silicon substrate, thermal diffusion of the dopant is not promoted. Therefore, thermal diffusion and activation of the dopant in the gate electrode can be sufficiently performed while suppressing an increase in thermal diffusion in the source-drain regions. Therefore, it is possible to realize a shallow source-drain junction to suppress the short channel effect, and to solve the problem that the gate electrode is depleted during the operation of the field effect transistor and the driving capability is reduced.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the present invention, after interstitial silicon is introduced into a polycrystalline silicon film, ion implantation of impurities and heat treatment are performed on the polycrystalline silicon film. The method of introducing interstitial silicon is not particularly limited, but a method of ion implantation of silicon atoms is preferable. This will be described later with reference to examples.

In the present invention, when the interstitial silicon is introduced by ion implantation of silicon atoms, that is, when silicon atoms are implanted into the polycrystalline silicon film in the second step, the amount of silicon atoms implanted is determined in a later step. Although in Ru is appropriately set according to the amount of impurity to be ion-implanted, preferably ^{1 × 10 12 ~1 × 10 15} atoms / cm 2, more preferably to ^{5 × 10 12 ~1 × 10 14} atoms / cm 2 . With such an implantation amount, diffusion and activation of the dopant impurity in the gate electrode can be sufficiently performed by the subsequent heat treatment. At the time of ion implantation of silicon atoms, ion implantation may be directly performed on the polycrystalline silicon film, or ion implantation may be performed via a through oxide film. The energy at the time of ion implantation is not particularly limited, but is preferably 10 to 30 keV, more preferably 1 to 30 keV.
5 to 25 keV. Annealing after implantation is not particularly necessary.

In the reference example of the present invention, when the interstitial silicon is introduced by forming a silicon oxide film, that is, when a silicon oxide film is formed by a thermal oxidation method in the second step, the heating temperature of the thermal oxidation is set to 750 to 750. The temperature is preferably set to 1000 ° C, more preferably 800 to 900 ° C. The heating time is usually 20 to 90 minutes, preferably 3 minutes.
0 to 60 minutes. With such formation conditions, interstitial silicon can be efficiently introduced into the polycrystalline silicon film.

The semiconductor substrate in the present invention refers to a silicon substrate, an SOI substrate or the like.

The present invention is intended to prevent a gate electrode from being depleted while realizing a shallow diffusion layer. Here, the problem of gate depletion becomes more remarkable as the element becomes finer and the gate oxide film becomes thinner. Therefore, the effect of the present invention becomes more remarkable as the gate oxide film becomes thinner. From this viewpoint, the average thickness of the gate oxide film in the invention is preferably 7 nm or less, more preferably 4 nm or less, and particularly preferably 3 nm or less.

The gate electrode in the present invention is formed by forming a polycrystalline silicon film on a gate oxide film, or by forming a polycrystalline silicon film and a high melting point metal film on a gate oxide film in this order. It can be. Here, the high melting point metal is preferably one or more metals selected from the group consisting of cobalt, tungsten, cobalt silicide, and tungsten silicide. This is because such a metal material can effectively reduce the contact resistance of the gate electrode and the diffusion layer, and is excellent in durability against heat treatment at a high temperature.

Such a gate electrode can be formed, for example, through the following steps. That is, first, a gate oxide film is formed on a semiconductor substrate, a polycrystalline silicon film is formed thereon, and then the polycrystalline silicon film is patterned, whereby a gate electrode having the above structure can be formed. Further, after forming a gate oxide film on a semiconductor substrate, forming a polycrystalline silicon film and a high melting point metal film thereon, and patterning the polycrystalline silicon film and the high melting point metal film, the gate electrode having the above structure is formed. Can be formed.

In the present invention, impurities are implanted into the entire surface after the gate electrode is formed. This introduces impurities into the gate electrode and forms an impurity diffusion layer around the gate electrode. As the impurity in the present invention, an element generally used for imparting conductivity to a semiconductor material is used. When a group IV element is used for the substrate material, a group III or group V element is used as an impurity. For example, arsenic, phosphorus, boron, or boron fluoride can be given. Among them, boron and boron fluoride exert the effects of the present invention more remarkably. This is because so-called accelerated diffusion due to heat treatment easily occurs.

In the present invention, after the impurities are ion-implanted on the entire surface in the fourth step, heat treatment is performed. This heat treatment is preferably performed at a substrate temperature of 900 to 1100 ° C., and the processing time is preferably 5 to 30 seconds. By annealing at such a temperature, impurities can be sufficiently diffused and activated. This heat treatment is preferably heat treatment by RTA (Rapid Thermal Annealing), and particularly preferably lamp annealing. In particular, when a shallow diffusion layer is formed, treatment by RTA or lamp annealing is effective.
This is because the activation of the impurity can be performed in a short time, and the distribution of the impurity diffusion layer and the adverse effect on the element on the substrate can be suppressed.

[0025]

(Embodiment 1) This embodiment will be described with reference to FIG. First, a silicon oxide film 2 having a thickness of 4 nm is formed on a silicon substrate 1 by a thermal oxidation method.
A 0 nm polycrystalline silicon film 3 was formed by a vapor phase growth (CVD) method. The silicon oxide film 2 is used as a gate oxide film of the FET, and the polycrystalline silicon film 3 is used as a gate electrode of the FET.

Thereafter, silicon atoms were implanted into the polycrystalline silicon film covering the entire surface of the substrate by ion implantation (FIG. 1).
(a)). The implantation energy is 20 keV and the dose is 1 × 10 ¹³ a
toms / cm ² .

Next, using a photoresist (not shown) as a mask, the polycrystalline silicon film was patterned by a plasma etching method. At this time, the processing line width of the polycrystalline silicon film, that is, the gate length of the FET was 0.1 μm. Thereafter, a silicon oxide film is deposited on the entire surface by a CVD method to a thickness of about 50 nm, and the CVD method is performed so that the upper surface of the polycrystalline silicon film and the silicon substrate surface serving as the source-drain region of the FET are exposed by a highly anisotropic dry etching method. The silicon oxide film was etched (FIG. 1 (b)).

Next, boron was introduced by ion implantation into the patterned polycrystalline silicon film and the exposed silicon substrate (FIG. 1 (c)). Boron implantation conditions were 4 KeV and 3 × 10 ¹⁵ atoms / cm ² .
Subsequently, the semiconductor device is heated to 1000 ° C.10 by the lamp annealing method.
Heating was performed for 2 seconds to diffuse and activate the dopant, thereby forming source / drain regions 6 (FIG. 1 (d)).

Through the above steps, a field effect transistor was completed. According to the method of this embodiment, at the stage of performing the heat treatment by lamp annealing, the interstitial silicon atoms and boron are introduced into the gate electrode, and only boron is introduced into the source / drain region 6. I have. Since the interstitial silicon atoms have the effect of accelerating the thermal diffusion of a dopant such as boron, the dopant diffuses relatively quickly to the lower layer of the gate electrode in the lamp annealing step. On the other hand, since the interstitial silicon atoms do not exist in the source / drain regions 6, the enhanced diffusion of the dopant does not occur. Therefore, it is possible to realize a shallow source-drain junction to suppress the short channel effect, and to solve the problem that the gate electrode is depleted during the operation of the field effect transistor and the driving capability is reduced.

This will be further described with reference to FIG.
FIG. 2 is a quasi static CV curve of a PMOS capacitor of an FET manufactured by the method of the present embodiment and a conventional FET manufactured without performing ion implantation of silicon. In the figure, white circles indicate the measurement results of the FET of the present embodiment, and black circles indicate the measurement results of the FET according to the conventional technique. On the inversion side of the MOS, that is, in the region where the gate bias is a negative voltage in FIG. 2, the capacitance is reduced due to the depletion of the P-type electrode.
The degree of this reduction is remarkably improved by the ion implantation of silicon according to the present invention. In this example, boron is ion-implanted into the gate electrode as a dopant,
Diffusion and activation are performed in a 10-second lamp annealing process. In the present invention, depletion in the lower layer of the gate electrode is reduced because the thermal diffusion of boron is accelerated.

REFERENCE EXAMPLE In the first embodiment, an ion implantation method was used to introduce interstitial silicon atoms. However, a method of forming a silicon oxide film on the surface of a polycrystalline silicon film by a thermal oxidation method may be used. FIG. 3 shows the manufacturing process flow.

First, a silicon oxide film 1 having a thickness of 4 nm is formed on a silicon substrate by a thermal oxidation method, and a silicon oxide film 1 having a thickness of 200 nm is formed thereon.
m polycrystalline silicon film 2 was formed by a vapor phase growth (CVD) method. The silicon oxide film 1 serves as a gate oxide film of the FET.
The polycrystalline silicon film 2 is used as a gate electrode of the FET.

Thereafter, a silicon oxide film was formed on the surface of the polycrystalline silicon film by a thermal oxidation method (FIG. 3A). The oxidation conditions were 800-900 ° C. for 30 minutes, and the oxide film thickness was about 10 nm. In this oxidation reaction, many silicon atoms that have not been bonded to oxygen are released into the polycrystalline silicon film and become interstitial silicon atoms.

Next, the polycrystalline silicon film 2 was patterned by a plasma etching method using a photoresist as a mask. At this time, the processing line width of the polycrystalline silicon film 2, that is, the gate length of the FET is 0.1 μm. Thereafter, a silicon oxide film 5 is deposited on the entire surface by a CVD method to a thickness of about 50 nm, and the upper surface of the polycrystalline silicon film and the silicon substrate surface serving as a source-drain region of the FET are exposed by a highly anisotropic dry etching method. The CVD silicon oxide film was etched (FIG. 3 (b)).

Next, boron was introduced by ion implantation into the patterned polycrystalline silicon film and the exposed silicon substrate (FIG. 3C). The boron implantation conditions were 4 KeV and 3 × 10 ¹⁵ cm ² . Subsequently, the semiconductor device was heated by a lamp annealing method at 1000 ° C. for 10 seconds to diffuse and activate the dopant (FIG. 3 (d)).

Through the above steps, a field effect transistor was completed. According to the method of the present embodiment, at the stage of performing the heat treatment by lamp annealing, interstitial silicon atoms and boron are introduced into the gate electrode, and only boron is introduced into the source / drain region 6. I have. Since the interstitial silicon atoms have the effect of accelerating the thermal diffusion of a dopant such as boron, the dopant diffuses relatively quickly to the lower layer of the gate electrode in the lamp annealing step. On the other hand, since the interstitial silicon atoms do not exist in the source / drain regions 6, the enhanced diffusion of the dopant does not occur. Therefore, it is possible to realize a shallow source-drain junction to suppress the short channel effect, and to solve the problem that the gate electrode is depleted during the operation of the field effect transistor and the driving capability is reduced.

[0037]

According to the present invention, interstitial silicon is introduced into a polycrystalline silicon film constituting a gate electrode in a step before ion implantation into a gate electrode and a semiconductor substrate. Therefore, it is possible to realize a shallow source-drain junction to suppress the short channel effect, and to solve the problem that the gate electrode is depleted during the operation of the field effect transistor and the driving capability is reduced.

[Brief description of the drawings]

FIG. 1 is a process sectional view of a method for manufacturing a semiconductor device according to the present invention.

FIG. 2 shows the F obtained by the method of the present invention and the prior art.
FIG. 9 is a diagram for explaining a difference in the degree of gate depletion of ET.

FIG. 3 is a process sectional view of a method for manufacturing a semiconductor device according to a reference example of the present invention;

FIG. 4 is a process sectional view of a conventional semiconductor device manufacturing method.

[Explanation of symbols]

 Reference Signs List 1 silicon substrate 2 silicon oxide film 3 polycrystalline silicon film 4 silicon oxide film 5 silicon oxide film 6 source / drain region

Continuation of the front page (56) References JP-A-61-191070 (JP, A) JP-A-4-42919 (JP, A) JP-A-6-244421 (JP, A) JP-A-3-34533 (JP) , A) JP-A-62-293727 (JP, A) JP-A-10-189973 (JP, A) JP-A-7-249763 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB Name) H01L 29/78 H01L 21/336 H01L 21/265 H01L 21/28 301

Claims (4)

(57) [Claims] 1. A first step of forming a gate oxide film and a polycrystalline silicon film on a semiconductor substrate in this order, and implanting 1 × 10 ¹² to 1 × 10 ¹⁵ silicon atoms into the polycrystalline silicon film.
a second step of ion-implanting silicon atoms at atoms / cm ² to introduce interstitial silicon, a third step of patterning the polycrystalline silicon film into a gate electrode shape, and ion-implanting impurities on the entire surface. And a fourth step of performing a heat treatment. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the amount of implanted silicon atoms in the second step is 5 × 10 ¹² to 1 × 10 ¹⁴ atoms / cm ² . 3. The impurity to be ion-implanted in the fourth step,
3. The method according to claim 1, which is boron or boron fluoride.
The method for manufacturing a semiconductor device according to any one of the above. 4. The method according to claim 1, wherein the thickness of the gate oxide film is 7 nm or less.