JPH07161988A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To provide a manufacturing method by which thin junction source and drain of a MIS type field-effect transistor are effectively formed and gate insulation breakdown strength is not deteriorated. CONSTITUTION:A manufacturing method includes a step of introducing impurities for forming source and drain regions 5 after a gate electrode 3 is patterned; and a step of forming a thin film insulation film at a high temperature for a short time by a rapid heating and cooling method and simultaneously activating initially impurities. Thus, as an insulation film 6 can be formed at a high temperature, it is possible to form an insulation thin film of a uniform film thickness which does not depend upon semiconductor surface impurity concentration and to simultaneously and entirely realize thin junction and high efficient activation of the source and drain.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to efficiently form the source and drain of a shallow junction of a MIS (Metal-Insulater-Semiconductor) type field effect transistor and to improve the gate breakdown voltage. The present invention relates to a method for forming a gate electrode without deterioration.

[0002]

2. Description of the Related Art As a general method for forming a gate electrode of a MIS field effect transistor and its source and drain, it is known that the gate electrode is formed by the following steps. (1) After forming an element isolation region on a semiconductor substrate, a gate insulating film and subsequently polycrystalline silicon are coated on the element formation region, and then a gate electrode of polycrystalline silicon is patterned. (2) Using the gate electrode as a mask, source and drain impurities are ion-implanted, and then this is furnace-annealed in an inert gas for activation. (3) Subsequently, a MIS field effect transistor is completed through a film of an interlayer insulating film, a contact hole opening, and a wiring forming process. At this time, in order to secure the withstand voltage between the gate electrode and the substrate, particularly the withstand voltage at the end of the gate electrode, a silicon oxide thin film forming step by light oxidation in a dry oxygen atmosphere immediately after the gate electrode is processed ( Hereinafter, it will be referred to as a light oxidation step). Generally, the film thickness of silicon oxide by this light oxidation is as thin as the film thickness of the gate insulating film.
Further, as a method of forming a thin insulating film such as this oxide thin film with good controllability, the furnace temperature at the time of oxidation is lowered, and the oxygen flow rate into the furnace body is diluted with a carrier gas to reduce the oxidation rate. Forming method with improved controllability is used.

Another known example of the above light oxidation method is a method of forming a thermal oxide film by high temperature and short time by rapid heating and cooling, as discussed in JP-A-62-174923. In this known example, the ion implantation process for the source and drain is performed after the thermal oxide film is formed.

Another known example is the Proceeding of International for the purpose of improving the reliability of a MIS field effect transistor having a low impurity concentration drain structure, that is, a so-called LDD (Lightly Doped Drain) structure.
Electron Device Meeting 1991 (Procee
ding of International Electron Device Meeting, 199
1) discussed in paragraphs 649-652,
After forming the source and drain having a low impurity concentration after processing the gate electrode, first, a silicon oxide thin film is formed by the CVD method, then a silicon nitride film is formed by the rapid nitriding method, and then the silicon oxide film is formed by the rapid oxidation method. There is a method of forming.

[0005]

When the silicon oxide film is formed by using the furnace oxidation method at a low temperature in the above-described conventional light oxidation process, the oxide film growth rate generally differs depending on the impurity concentration in silicon. However, due to the accelerated oxidation, the silicon oxide film is formed thin on the low impurity concentration silicon substrate and thick on the high impurity concentration doped polycrystalline silicon gate electrode.

This is shown in FIG. FIG. 2 shows a cross-sectional view when the gate electrode 3 made of polycrystalline silicon in which phosphorus is introduced at a high concentration is processed and then oxidized in a dry oxidizing atmosphere at 850 ° C. for 30 minutes. . in this case,
About 10 ¹⁷ / cm ³ of boron is introduced into the silicon substrate 1, and phosphorus is contained in the polycrystalline silicon gate electrode 3.
²¹ / cm ³ has also been introduced. Therefore, an oxide film having a thickness of about 10 nm is formed on the silicon substrate 1, but an oxide film 7 having a thickness of 50 to 100 nm is formed around the gate electrode 3, and a larger gate bird's beak is also formed. ing. Therefore, when an ultrafine MIS field effect transistor with a channel length of 0.1 μm level is formed in the future, the source / drain regions are separated from the gate electrode by this light oxidation, and the MIS field effect transistor cannot be turned on. Or, in an extreme case, there is a problem that the gate electrode is lost. Further, this accelerated oxidation is more severe as the treatment temperature is lower, and is smaller at the higher temperature. However, there is a problem that the ultra-thin oxide film cannot be formed with good controllability when the temperature is raised by the usual furnace body oxidation method. In addition, if impurities are ion-implanted into the silicon substrate to form the source and drain, and then the annealing temperature is lowered for the purpose of shallow junction, accelerated diffusion of the introduced impurities occurs at the initial stage of annealing. ,
It is known that the lower the annealing temperature, the larger the diffusion layer depth. As a result, there is a problem that the depth of the source / drain diffusion layer becomes larger than desired, and thus the short channel effect becomes more severe. This cannot be ignored when the element size becomes ultrafine at the level of 0.1 μm. Further, there is also a problem that the reduction of the activation annealing temperature greatly reduces the activation rate of the introduced impurities.

If the insulating film as a part of the interlayer insulating film, the sidewall insulating film, or the like is formed by the CVD method without performing the light oxidation step immediately after processing the gate electrode, the dielectric strength at the gate end portion is increased. There was a problem of deterioration. In general, after the gate processing, a cleaning process using a hydrofluoric acid-based aqueous solution or the like is performed before proceeding to the next process. At this time, the gate insulating film at the end of the gate electrode is etched, and an overhang-like portion is always formed. When the gate insulating film becomes thinner as the device size becomes finer, the ratio of the size of this overhang portion becomes remarkable, and if a damaged film or a poor quality film is provided here, the gate insulating breakdown voltage will increase. Was greatly reduced.

Therefore, the object of the present invention is to provide MI
While forming an interlayer insulating thin film with uniform controllability without deterioration of the gate withstand voltage of the S-type field effect transistor,
An object of the present invention is to provide a method for efficiently forming a source and a drain of a shallow junction without increasing the number of steps.

[0009]

The above object is to provide a method for forming a gate electrode and a source / drain region of a MIS field effect transistor, and a step of introducing impurities for the source / drain immediately after patterning the gate electrode. Then, it is achieved by including a high-temperature short-time insulating thin film forming step by a rapid heating and cooling method which also doubles as the first activation of the introduced impurities.

[0010]

In the above-mentioned manufacturing method, the use of the high-temperature short-time oxidation method by rapid heating and cooling means that the insulating film having a uniform thickness is formed on the regions having different impurity concentrations in silicon in order to suppress the accelerated oxidation. I will provide a. Further, by performing the rapid heating / cooling process immediately after the implantation of the impurity ions, it is possible to improve the activation rate of the introduced impurities and suppress the accelerated diffusion of the introduced impurities in the initial stage of annealing. Furthermore, since the rapid heating / cooling step also serves as the light oxidation step for improving the dielectric strength of the gate electrode, the number of processing steps can be reduced.

This will be described in detail with reference to FIGS. 3 (a) and 3 (b). FIG. 3A shows the oxidation temperature dependence of a typical enhanced oxidation rate in oxidation in a dry oxygen atmosphere. Here, the accelerated oxidation rate is defined as a ratio of a silicon oxide film thickness formed on a silicon substrate in which phosphorus is highly diffused and a silicon oxide film thickness formed on a non-doped silicon substrate. That is, the accelerated oxidation rate of 1 indicates that accelerated oxidation did not occur, and the larger the number, the stronger accelerated oxidation occurred. As a result, the lower the oxidation temperature is, the higher the accelerated oxidation rate is,
1000 or more in the vicinity, compared to 10 or more
It is clear that it becomes close to 1 above the temperature of ° C. Therefore, if thermal oxidation at a high temperature of 1000 ° C. or higher is performed using a short-time (second order) thermal oxidation technique by rapid heating and cooling, a uniform ultra-thin silicon oxide film that does not depend on the surface impurity concentration can be obtained.

Further, immediately after ion-implanting the impurities for the source and drain, a high-temperature short-time heat treatment by rapid heating and cooling can be performed to suppress the accelerated diffusion and improve the activation rate. This will be described in detail with reference to FIG. FIG. 3 shows a distribution of activated boron in the depth direction when various heat treatments are performed after implanting 1 × 10 ¹⁴ / cm ² ions of boron at a low energy of about 10 keV. In the figure, comparison is made between normal furnace annealing at 800 ° C for 30 minutes only, and high temperature short time annealing at 1000 ° C for 10 seconds, followed by normal furnace annealing at 800 ° C for 30 minutes. I am doing it. Apparently, the one subjected to the high temperature short time annealing had a shallow diffusion layer depth and a high peak concentration. The large diffusion at 800 ° C. annealing is due to the initial accelerated diffusion that occurs more intensely at lower temperatures. Therefore, in the process step immediately after implanting the impurities, the high temperature short time annealing of about 1000 ° C. should be performed first, and then the low temperature process step is performed. If this order is reversed, the diffusion layer depth is increased. I will leave. Other features and objects of the present invention will be apparent from the following examples.

[0013]

[Embodiment 1] A first embodiment of the present invention will be described below with reference to FIG. FIG. 1 is a diagram schematically showing a manufacturing process for forming an n-channel MIS type field effect transistor as a typical manufacturing method of the present invention. Figure 1 (a)
First, after forming a well region having a surface concentration of about 2 to 4 × 10 ¹⁷ / cm ³ on a p-type 10 Ω-cm silicon substrate 1 and subsequently forming an element isolation region, a gate insulating film 2 made of silicon dioxide, The gate electrode 3 is patterned by coating polycrystalline silicon heavily doped with phosphorus, and further, arsenic 4 is ion-implanted at 2-4 × 10 ¹⁵ / cm ² at a low acceleration voltage of 15 to 20 keV using the gate electrode 3 as a mask. It is a cross-sectional view after the process. Here, the gate insulating film 2 is 4
.About.8 nm and the thickness of the polycrystalline silicon film is 150 to 2
00 nm. Further, since the dry etching with a high selectivity was used for the processing of the gate electrode, the silicon dioxide film on the silicon substrate after the processing had a very slight abrasion of 1 to 2 nm. Next, as shown in FIG. 1B, after cleaning the surface with diluted hydrofluoric acid, a silicon oxide film 6 is formed by a rapid heating and cooling method in an oxygen atmosphere at 1000 ° C. for 10 seconds using a single-wafer lamp annealing furnace. did. At this time, the film thickness of silicon oxide on the source / drain 5 was 4 to 8 nm, whereas it was 6 to 10 nm on the side wall of the gate electrode 3, and the accelerated oxidation was drastically reduced. Also, almost no gate bird's beak occurred. After that, a known interlayer insulating film coating, a wiring forming process, and the like were performed to complete the process. In addition, after the rapid oxidation step, in an interlayer insulating film forming step, etc.
Normal low temperature furnace body annealing was also performed. As described above, a fine MIS field effect transistor could be formed with good controllability. In particular, in the high impurity concentration source and drain regions, a junction depth of about 50 nm and a shallow junction and an activation rate of almost 100% were realized. As a result, it was possible to reduce the short channel effect and improve the current driving capability by reducing the source / drain parasitic resistance. Furthermore, in this example, the junction leakage current could be greatly reduced by adding the low temperature furnace body annealing that was added last. The material of the gate electrode 3 may be a metal, a multi-layer film of metal and silicon, etc., and the gate insulating film material may be another high dielectric material (silicon nitride film, tantalum oxide film, etc.). Further, although the present embodiment deals with an n-channel field effect transistor, it may be applied to a p-channel by changing the conductivity type of impurities. Further, although the thin-film insulating film 6 is a silicon oxide film in the above-mentioned embodiment, after this, 1100
A silicon nitride film may be formed by a rapid heating / cooling method in a nitrogen atmosphere at ° C, and then a silicon oxide film may be formed again by a rapid heating / cooling method. The gist of the present invention is
It suffices that the first heat treatment after introducing the source / drain impurities is a high-temperature short-time treatment and a thermal oxide film forming step.

After processing the gate electrode, the source,
A thin silicon oxide film of about 10 nm may be coated by a CVD method at an ultralow temperature (500 ° C. or less) between the step of ion-implanting impurities for drain and used as a through oxide film at the time of ion-implantation. This can prevent contamination during ion implantation. However, from the viewpoint of improving the gate breakdown voltage, this oxide film needs to be removed before the high temperature short time oxidation step. Furthermore, if the remaining film of the silicon oxide film on the substrate at the time of processing the gate electrode is removed by isotropic etching before forming the main CVD oxide film, a more uniform source / drain depth can be obtained. Large irregularities are formed on the surface of the silicon oxide film remaining after the processing of the gate electrode due to the difference in etching rate due to the presence of crystal grain boundaries in the polycrystalline silicon film. Therefore, if this is used as a through oxide film at the time of ion implantation, the projection range at the time of ion implantation will locally vary. Therefore, re-forming the through oxide film can greatly reduce this variation. The through oxide film may be formed by a high temperature short time oxidation method.

[Second Embodiment] Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 4 shows the manufacturing method of the present invention.
It shows a case where it is applied to a method of manufacturing a MIS field effect transistor having a DD structure. First, the first embodiment similarly to the p-type 10 [Omega-cm after the element isolation region formed on the silicon substrate 20 of, 0.5 to 1 × boron as punch-through stopper 23 in about 40~60keV 10 ¹⁴ /
cm ² ion implantation is performed. Subsequently, a gate insulating film 21 made of silicon dioxide, polycrystalline silicon doped with phosphorus at a high concentration is coated, and the gate electrode 22 is patterned. Then, with the gate electrode 22 as a mask, arsenic is applied at 20 keV.
Ion implantation of 5 to 1 × 10 ¹⁴ / cm ² was performed. Figure 4 (a)
Shows a cross-sectional view at this time. Here, the gate insulating film 21 has a thickness of 4 to 8 nm, and the polycrystalline silicon film 22 has a thickness of 150 to 200 nm. In addition, since dry etching with a high selectivity was used for processing the gate electrode, the silicon dioxide film on the silicon substrate after the processing is cut by 1 to
It was as very small as 2 nm. Next, as shown in FIG. 4B, after cleaning the surface with diluted hydrofluoric acid, a silicon oxide film 25 is formed by a rapid heating and cooling method in an oxygen atmosphere at 1000 ° C. for 10 seconds using a single-wafer lamp annealing furnace. did. At this time, while the silicon oxide film thickness on the low impurity concentration source / drain 24 is 4 to 8 nm, the gate electrode 22
The accelerated oxidation was drastically reduced to 6 to 10 nm on the side wall.
Also, almost no gate bird's beak occurred. Next, as shown in FIG. 4 (c), a silicon dioxide film is formed to a thickness of 100 to 120 nm by using a known chemical vapor deposition method (CVD method),
This silicon oxide film is processed by the film thickness by anisotropic dry etching. As a result, the sidewall spacer 26 made of a silicon oxide film can be formed on the sidewall of the gate electrode 22. At this time, the width of the sidewall spacer 26 was 90 to 110 nm. Then, the same CVD method is used to coat a silicon dioxide thin film 27 with a thickness of 10 to ¹⁵ nm, and thereafter, arsenic 28 is used with the gate electrode 22 and the sidewall insulating film 26 as a mask to 2 to 5 × 10 ¹⁵ / cm 2.
² Ion implantation. Next, as shown in FIG. 4 (d), by a rapid heating and cooling method using a single-wafer type lamp annealing furnace, 1000 ° C. in an inert gas (eg, argon or nitrogen) atmosphere.
Heat treatment was performed for 5 seconds to activate the introduced impurities. After that, a known interlayer insulating film forming process, a wiring forming process and the like are performed to complete the process. After the rapid heat treatment, a normal low temperature furnace body annealing at 800 to 850 ° C. was also performed in the interlayer insulating film forming step and the like. From the above, the gate length is 0.1
An m-level MIS field effect transistor could be formed with good controllability. In particular, the low impurity concentration source / drain region 24 can form a shallow junction with a junction depth of about 30 nm, and the high impurity concentration source / drain region 29 can form a shallow junction with a junction depth of about 50 nm, and The activation rate was almost 100%. As a result, it was possible to reduce the short channel effect and improve the current driving capability by reducing the source / drain parasitic resistance. Further, in this embodiment, the first
By adding the low temperature furnace body annealing that was added last as in the example of 1, the junction leakage current could be greatly reduced.

[Third Embodiment] Next, a third embodiment of the present invention will be described with reference to FIG. FIG. 5 shows the manufacturing method of the present invention.
It shows a case where the present invention is applied to a manufacturing method for forming a complementary MIS field effect transistor having an n-type and p-type bipolar polycide gate electrode structure. First, p-type 1
A p-type well 31 and an n-type well 32 are formed on a 0 Ω-cm silicon substrate 30 by ion-implanting each impurity and subsequent thermal diffusion at high temperature for a long time, and then a thick silicon oxide film 33 for element isolation is formed as desired. Formed in the area. Further, boron is ion-implanted into the p-type well 31 region and phosphorus is ion-implanted into the n-type well 32 region at 40 to 60 keV at 0.5 to 1 × 10 ¹⁴ / cm ² to form a punch-through stopper layer 34, respectively.
35 was formed. FIG. 5 (a) shows a sectional view at this time. Here, the thickness of the element isolation silicon oxide film 33 was 400 to 500 nm. Also, the above n, p
The implantation of each impurity into the mold region was performed on the resist mask using a known lithography technique. Next, FIG.
As shown in (b), the gate insulating film 3 made of silicon dioxide
After forming 6 to 4 to 8 nm, non-doped polycrystal or amorphous silicon 37 and 38 is formed to 50 to 100 nm, tungsten silicide 39 is formed to 100 to 150 nm, and a silicon oxide film 40 is formed to 10 to 20 nm. Was coated using the CVD method of. Then, p-type well 3
Phosphorus is used for the polycrystalline or amorphous silicon 37 on one region,
Boron is introduced into the polycrystalline or amorphous silicon 38 on the n-type well 32 by ion implantation of 0.5 to 1 × 10 ¹⁶ / cm ² . Next, as shown in FIG. 5C, the gate electrode made of the above-described multilayer film is patterned by using a known lithography technique. At this time, the impurities introduced into the polycrystalline or amorphous silicons 37 and 38 are not activated before processing. As a result, it is possible to prevent a difference in etching rate due to a difference between n-type and p-type. Then, using these gate electrodes and the oxide film for element isolation as a mask, arsenic 41 is provided on the n-channel side and boron 42 is provided on the p-channel side at 10 to 20 keV at 2 to 4 × 10 ¹⁵ / cm ^2.
I ion-implanted. Finally, as shown in FIG. 5 (d), the surface was washed with diluted hydrofluoric acid as in the above-mentioned example, and then the single-wafer-type lamp annealing furnace was used.
Silicon oxide film 4 by rapid heating and cooling method at 0 ° C for 10 seconds
Formed 3. At this time, the film thickness of silicon oxide on the source / drain 44 was 4 to 8 nm, whereas it was 6 to 10 nm on the side walls of the gate electrodes 37 and 38, and the accelerated oxidation was drastically reduced. Also, almost no gate bird's beak occurred. According to this example, the same effect as that of the above example was obtained, and the high temperature activation of impurities in the gate electrode was also performed, so that the number of steps could be further reduced. further,
When the ion implantation method is used as a method for introducing impurities into the polycide gate electrode, there is a problem that as the gate insulating film becomes thinner, depletion on the gate electrode side causes a decrease in MIS capacitance. It was a great improvement.

[Fourth Embodiment] Next, another embodiment of the present invention will be described with reference to FIG. It is shown that the manufacturing method of the present embodiment is also effective when regions having different impurity concentrations are formed on the same silicon film or an exposed silicon film, and then a silicon oxide film is simultaneously formed on these regions.
FIG. 6 shows an n-channel MI made of thin film polycrystalline silicon.
It shows a case where the present invention is applied to a manufacturing method for forming an S-type field effect transistor. In the present embodiment, the case where the gate electrode is formed under the thin film polycrystalline silicon which becomes the channel is shown. First, after forming a gate electrode 51 made of polycrystalline silicon on an insulating film 50 made of a silicon oxide film, a CVD process is performed as a gate insulating film 52.
Method or thermal oxidation method to form a silicon oxide film of 20 to 30n
m coating, followed by annealing in a nitrogen atmosphere at 850 to 900 ° C. After that, a polycrystalline silicon thin film 53 for a channel was coated by a CVD method to a thickness of 50 to 80 nm. FIG. 6A shows a sectional view at this time. Next, as shown in FIG. 6B, phosphorus is ion-implanted into the polycrystalline silicon thin film 53 to be a channel in an amount of 0.5 to 1 × 10 ¹³ / cm ^2, and the source is used as a resist mask by a known lithography technique. As an impurity for the region and the drain region, arsenic was ion-implanted in an amount of 0.5 to 1 × 10 ¹⁵ / cm ² . At this time, a thin silicon oxide film of about 10 nm may be formed as a through oxide film on the polycrystalline silicon thin film 53 to serve as a channel by a CVD method at the time of ion implantation. However, in this case, this is removed before the next step. Next, as shown in FIG. 6C, after cleaning the surface with diluted hydrofluoric acid as in the above-described embodiment, a rapid heating and cooling method at 1000 ° C. for 10 seconds in an oxygen atmosphere is performed using a single-wafer lamp annealing furnace. Thus, a silicon oxide film 56 is formed. At this time, the thickness of the silicon oxide film 56 was 15 to 20 nm on the source / drain 57, while it was 10 to 15 nm on the channel polycrystalline silicon, and thus the accelerated oxidation hardly occurred. When this is formed by a conventional low temperature furnace body oxidation method, a thick silicon oxide film is formed on the source and drain with high impurity concentration by accelerated oxidation,
The drain part was gone. According to this embodiment, in the case of forming a silicon oxide film on the same polycrystalline silicon film having regions having different impurity concentrations,
It was possible to provide a substantially uniform film without causing accelerated oxidation according to the impurity concentration. Furthermore, since the interface between the back surface of the channel and the insulating film can be improved, the characteristics of the thin film transistor can be greatly improved. Although this embodiment is a method of manufacturing a thin film transistor made of polycrystalline silicon, it can be similarly applied to a thin film transistor made of single crystal silicon and the same effect can be obtained. Therefore, the manufacturing method of the present invention is very effective even when regions having different impurity concentrations are formed on the same silicon film or on an exposed silicon film and then a uniform silicon oxide film is simultaneously formed on these regions. Become.

[0018]

According to the present invention, a uniform insulating film can be formed on a semiconductor surface having regions having different impurity concentrations, and at the same time, highly efficient activation of introduced impurities and shallow junction thereof can be realized at the same time. Therefore, when this is applied to the method of forming the gate electrode, the source and the drain of the MIS field effect transistor, it is possible to realize the shallow junction of the source and the drain, the high efficiency activation, and the improvement of the gate withstand voltage at the same time. A semiconductor device that operates at high speed can be obtained by a simplified process even at the level of 0.1 μm.

[Brief description of drawings]

FIG. 1 is a process drawing for forming a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a conventional known example.

FIG. 3 is a diagram showing temperature dependence of accelerated oxidation rate and activation rate by high-temperature short-time heat treatment and rapid heating / cooling.

FIG. 4 is a process drawing for forming the second embodiment of the present invention.

FIG. 5 is a process drawing for forming a third embodiment of the present invention.

FIG. 6 is a sectional view showing a fourth embodiment of the present invention.

[Explanation of symbols]

1, 20, 30, 50, ... Silicon substrate, 24 ... N-type low impurity concentration source, drain, 5, 29, 44, 57, ... N-type high impurity concentration source, drain, 2, 21, 36, 52 ... Gate Insulating film, 3, 22, 37, 38, 51 ... Polycrystalline silicon gate electrode, 6, 25, 43, 56 ... Silicon thermal oxide thin film, 26 ... Side wall spacer.

Continuation of the front page (51) Int.Cl. ⁶ Identification number Internal reference number FI Technical display location H01L 29/43 8826-4M H01L 29/62 G (72) Inventor Shizuka Oyu 1-280 Higashi-Kengokubo, Kokubunji, Tokyo Address: Central Research Laboratory, Hitachi, Ltd. (72) Inventor Nagatoshi Oki, 5-201-1, Kamimizuhonmachi, Kodaira-shi, Tokyo Inside Hiritsu Cho-LS Engineering Co., Ltd. (72) Inventor: Hiroshi Ishida 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Within Hitate Cho-LS Engineering Co., Ltd. (72) Inventor Toshiaki Yamanaka 1-280, Higashi-Kengokubo, Kokubunji-shi, Tokyo Inside Hitachi Central Research Laboratory ( 72) Inventor Koji Hashimoto 1-280, Higashi Koigokubo, Kokubunji, Tokyo Metropolitan Research Center, Hitachi, Ltd.

Claims (9)

[Claims] 1. An insulated gate field effect transistor comprising a source region and a drain region provided on a semiconductor substrate, and a gate electrode exerting a field effect on a channel between the source region and the drain region. In the method of manufacturing a semiconductor device having, a step of introducing impurities for forming the source region and the drain region after processing the gate electrode, and subsequently, rapid heating that also serves as a first activation heat treatment of the introduced impurities. And a step of forming a thin insulating film at a high temperature in a short time by a cooling method. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the thin film insulating film is a silicon oxide film. 3. A step of forming a thin film insulating film by a low temperature CVD method between the step of processing the gate electrode and the step of introducing impurities for forming the source region and the drain, and a high temperature short by rapid heating and cooling. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of removing the insulating film before the thermal oxide film forming step for a certain period of time. 4. A source region and a drain region provided on a semiconductor substrate, and a gate electrode exerting a field effect on a channel between the source region and the drain region.
A method of manufacturing a semiconductor device having an insulated gate field effect transistor, wherein the drain region has an LDD structure, wherein a step of introducing impurities for forming the source region and the drain region after processing the gate electrode, Subsequently, a step of forming a thin film insulating film at a high temperature in a short time by a rapid heating and cooling method, which also serves as the first activation heat treatment of the introduced impurities, a step of forming a sidewall spacer on the side wall of the gate electrode, and thereafter, A method of manufacturing a semiconductor device, comprising the step of forming a high concentration impurity region of the drain region using the gate electrode and the sidewall as a mask. 5. The method of manufacturing a semiconductor device according to claim 1, wherein the thin film insulating film is a silicon oxide film. 6. The method of manufacturing a semiconductor device according to claim 1, wherein the gate electrode has a high concentration of impurities introduced by ion implantation. 7. The method of manufacturing a semiconductor device according to claim 6, wherein the thin film insulating film is a composite film of polycrystalline silicon, metal and metal silicide. 8. A thin insulating film is formed at a high temperature in a short time by a rapid heating and cooling method, which comprises a step of forming two or more regions having different impurity concentrations on a semiconductor surface, and subsequently a first heat treatment for activating the impurities. And a step of forming the semiconductor device. 9. The method of manufacturing a semiconductor device according to claim 8, wherein the semiconductor is polycrystalline silicon.