JP3238551B2 - Method for manufacturing field effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a field effect transistor, and more particularly to a CM having a MOSFET.
OS device, mainly its n-channel MOSFET
And a method for producing the same.

[0002]

2. Description of the Related Art In recent years, as semiconductor devices have been miniaturized, and as MOSFETs have been reduced in size, the gate length has become shorter. The depth (xj) has to be reduced.

As described above, the gate length is reduced, and the MOS
Since the on-resistance of the FET decreases while xj becomes shallower, the sheet resistance of the source / drain increases. Therefore, in a MOSFET having a gate length in a submicron region, the sheet resistance of the source / drain cannot be ignored with respect to the ON resistance of the MOSFET, and the driving force of the MOSFET is reduced by the parasitic resistance of the source / drain region. Will be noticeable.

To solve this problem, there is a salicide technique for reducing the sheet resistance by siliciding the source / drain and the gate in a self-aligned manner.

FIG. 3 is a sectional view showing a manufacturing process of such a MOSFET having a conventional salicide structure.

(1) First, as shown in FIG.
An N-type impurity (phosphorus or the like) is introduced into a part of the mold 100Si substrate 1 by using normal photolithography (hereinafter, abbreviated as photolithography), etching, and ion implantation to form an N-well region 2. Next, a field oxide film 3 is formed by a normal LOCOS method. Thermal oxidation is performed in a dry oxidation atmosphere to form a gate oxide film 4 on the surface of the Si substrate 1, a polycrystalline silicon film to be a gate electrode is deposited on the entire surface, and patterning of the gate electrode 5 is performed using a normal photolitho etching technique. I do.

In a normal photolithography process, a Pch (P-channel) MOSFET formation region is covered with a photoresist 6, and phosphorus or arsenic which becomes an LDD (Lightly Dope) layer (low concentration diffusion layer) n ^- layer 7 is accelerated over the entire surface. 1-4 × 10 ¹³ ions / at an energy of 30-50 keV
By implanting by cm ² ion implantation, Nch (N
Channel) An n ^- layer 7 is formed only in the MOSFET region.

Next, a silicon oxide film or a silicon oxide film containing boron, phosphorus or the like is formed on the entire surface by atmospheric pressure CVD (chemical vapor deposition), and FIG. 3B is formed by anisotropic ion etching. As shown in FIG. 6, a sidewall film 8 is formed on the side wall of the gate electrode 5.

Next, as described above, the Pch MOSFET and the Nch MOSFET are respectively covered with a photoresist, and the Nch and Pch sides are respectively ion-implanted by the ion implantation method.
An arsenic-implanted region 9 (n ⁺ layer) and a boron-implanted region 9 ′ (p ⁺ layer) are implanted as impurities serving as source / drain regions.

Next, as shown in FIG.
After performing a heat treatment at 1000 ° C. to activate the impurities in the source / drain regions 9, the refractory metal film 10 is formed.

Then, in the range of 600 to 1000 ° C.,
By performing the two-step short-time heat treatment, silicide is formed between the refractory metal film 10 and the polycrystalline silicon film of the gate electrode 5 and the silicon active layer of the source / drain region 9 as shown in FIG. A high-melting-point metal silicide film 11 is formed in a self-aligned manner.

During this step, the unreacted high-melting point metal 12 is selectively removed by etching using a mixed solution of aqueous ammonia and aqueous hydrogen peroxide, as shown in FIG. A MOSFET having a salicide structure is completed.

[0013]

However, in the above-mentioned conventional method of manufacturing a MOSFET having a salicide structure, the junction of the diffusion layer of the source / drain region is reduced in order to suppress the short channel effect as the element is miniaturized. There is a problem that the depth (xj) becomes shallow, the distance between the bottom surface of the silicided layer and the junction becomes short, and the junction leakage current increases.

Further, the surface of the silicide on the source / drain region and the gate electrode has a problem that an oxide is generated when exposed to the air, and a sufficient ohmic contact cannot be obtained when connecting to a metal wiring. Was.

Further, since the silicidation is performed after the source / drain regions are formed, the impurity concentration at the interface between the silicide and the diffusion layer is lowered by the heat treatment for planarizing the interlayer insulating film, thereby causing parasitic resistance and causing a MOS transistor. However, there is a problem that the current driving capability is reduced.

Further, when the source / drain regions are formed, the ion implantation is performed in a state where the side wall is formed, and the side wall remains without being removed until the end of the process. Impurity in the sidewall film diffuses into the source / drain region due to heat treatment in a later step, making the impurity profile of the source / drain region at the gate electrode end nonuniform, resulting in a short channel effect and deterioration of hot carrier resistance. was there.

When the source / drain region and the gate electrode are silicided, the upper portion of the sidewall is hardly silicided, but the surface of the sidewall slightly undergoes a silicidation reaction. Sometimes, the reaction layer cannot be removed enough,
There is a problem that the gate electrode and the source / drain region are short-circuited.

The present invention has been made to solve the above problems.
Provided is a method for manufacturing a field-effect transistor having a salicide structure that eliminates the above-described increase in junction leak current and parasitic resistance, effectively suppresses a short channel effect, and can further suppress a hot carrier effect. The purpose is to:

[0019]

According to the present invention, there is provided a method for manufacturing a field effect transistor, comprising the steps of: forming a gate on a first insulating film formed on a main surface of a semiconductor substrate; Forming an electrode; and forming the first electrode including the gate electrode.
Forming a second insulating film on the first insulating film, forming a side wall portion facing the second insulating film covering a side wall of the gate electrode with a third insulating film, to leave the second insulating film covering at the second insulating film and the side wall portion for covering the side wall of the electrode, etching the second insulating film, exposed
Removing the first insulating film, the main surface of the semiconductor substrate;
Exposing the gate electrode and the exposed
Forming a refractory metal film on the main surface of the semiconductor substrate.
And heat treatment, the refractory metal film and silicon
A step of forming a silicide film and a first ion implantation step of implanting impurity ions into the main surface of the semiconductor substrate except for a region covered with the gate electrode, the sidewall portion, and the remaining second insulating film. A step of removing the sidewall portion; a second ion implantation step of implanting impurity ions into the main surface of the semiconductor substrate except for a region covered with the gate electrode and the remaining second insulating film; A step of removing the remaining second insulating film; a third ion implantation step of implanting impurity ions into the main surface of the semiconductor substrate except for a region covered with the gate electrode; Is activated to form a source region and a drain region.

[ 2 ] In the method for manufacturing a field effect transistor according to the above [ 1 ], after the third ion implantation step, a step of nitriding the exposed surface of the silicide, and thereafter, performing the heat treatment step. Features.

[3] In the method of manufacturing a field effect transistor, a step of forming a gate electrode on a first insulating film formed on a main surface of a semiconductor substrate, and a second insulating film on a side wall of the gate electrode Forming a sidewall portion by removing the first insulating film,
Exposing a main surface of the substrate, and exposing the gate electrode
And a refractory metal film on the exposed semiconductor substrate main surface.
Forming step and heat treatment to form a
A step of forming a silicide film by recon and a first step of implanting impurity ions into the main surface of the semiconductor substrate except for a region covered with the gate electrode and the sidewall portion;
An ion implantation step, a step of removing the side wall portion, a second ion implantation step of implanting impurity ions into the main surface of the semiconductor substrate except for a region covered with the gate electrode, and thereafter, performing a heat treatment. A step of activating impurity ions to form a source region and a drain region is performed.

[4] In the method for manufacturing a field-effect transistor according to [ 3 ], after the second ion implantation step, a step of nitriding the exposed surface of the silicide film;
Thereafter, the heat treatment step is performed.

[0023]

According to the present invention, as described above, the source / drain regions are silicided outside the relatively long sidewalls, and the diffusion layers are deep only in those regions. An increase in junction leak current can be suppressed without increasing the channel effect.

Further, since the silicidation of the source / drain regions is performed before forming the diffusion layers, the silicidation reaction can be stably generated at a low temperature without being affected by the natural oxide film. Therefore, it is possible to stably realize a sufficiently low resistance with good reproducibility.

Furthermore, since there is no oxygen knock-on due to the mask oxide film at the time of ion implantation into the source / drain regions,
In the heat treatment of the silicidation reaction, the silicidation reaction can be uniformly generated at a low temperature.

More specifically, the ion implantation dose for forming the source / drain is suppressed to a range in which the junction depth is made sufficiently shallow and the current driving capability is not reduced. In addition, a MOSF with a sufficient short-channel effect is suppressed and the driving capability is high.
ET becomes feasible.

Further, the formation of a deep diffusion layer in the silicidation region utilizes solid-phase diffusion from a silicide film.
A smooth interface is obtained in which the interface between the silicide and the diffusion layer is not uneven, the impurity concentration at the interface between the silicide and the diffusion layer is kept high, and the ohmic junction can be stably realized with good reproducibility.

Further, after the silicidation, a shallow diffusion layer is formed, LDD (n ^-) so that ion implantation is performed for the layer formation, a flattening annealing of the interlayer insulating film to activate the impurity in the ion implantation Even if they are performed simultaneously, it is possible to compensate for the decrease in the impurity concentration at the interface between the silicide and the diffusion layer, and a sufficient ohmic junction can be realized between the silicide and the diffusion layer.

[0029]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a sectional view of a manufacturing process of a field-effect transistor according to a first embodiment of the present invention (Part 1), and FIG. 2 is a sectional view of a manufacturing process of the field-effect transistor (Part 2).

(1) First, as shown in FIG.
LO is placed on the silicon substrate 21 with the (100) plane orientation of the mold.
In order to form an element isolation region by the COS method, a field oxide film 22 is formed to about 4000 °.

(2) Next, as shown in FIG. 1B, the gate oxide film 23 is
It is formed about 0 °. Next, a polycrystalline silicon film is formed to a thickness of about 3000 ° using a low pressure CVD method. Next, a gate electrode 24 wiring made of a polycrystalline silicon film is formed by using a usual photolithography technique and an etching technique. Next, the silicon active layer surface 25a and the polycrystalline silicon film surface 25b
An oxide film is formed thereon in a dry oxidation atmosphere at a temperature of about 800.degree.

Next, a silicon nitride film 26 is formed on the entire surface to a thickness of about 500 to 1000 ° by LPCVD. Next, a silicon oxide film is formed in a thickness of about 2000 to 3000 ° using the LPCVD method or the normal pressure CVD method. Then, using a reactive (anisotropic) ion etching method,
Only the silicon oxide film is etched, and the side walls 27a, 2 made of the silicon oxide film are formed on the side walls of the gate electrode 24.
7b is formed.

(3) Next, as shown in FIG. 1C, the silicon nitride film 26 other than the side wall of the gate electrode 24 is formed by wet etching or reactive ion etching.
Is removed by etching to form double side walls 31a, 31b, 27a, 27b including L-type side walls, and using this as a mask, a silicon active layer is formed using a buffered hydrofluoric acid solution containing a surfactant. The oxide film on the surface 25a and the polycrystalline silicon film surface 25b is removed by etching. Next, the natural oxide film on the silicon active layer surface 25a and the polycrystalline silicon film surface 25b is etched away by plasma surface cleaning in a gas atmosphere of an Ar + H ₂ gas mixture.

Next, without continuously exposing the silicon substrate to the atmosphere, the entire surface is
Refractory metal (Ti, Co, W, Ni, Mo, etc.)
It is formed at about 0-500 °. Next, the gate electrode 24 made of a polycrystalline silicon film is formed using a two-step short-time heat treatment method.
A refractory metal silicide film, for example, a TiSi ₂ film of about 600 ° is formed in a self-aligned manner on the upper surface and on the surface 25a of the silicon active layer serving as a source / drain region. The first-stage short-time heat treatment is performed at about 600 to 700 ° C. in an N ₂ gas atmosphere for 30 seconds.

Next, using a mixture of aqueous ammonia (NH ₃ OH), aqueous hydrogen peroxide (H ₂ O ₂ ) and water (H ₂ O), TiN on silicide and on the side wall and field oxidation at room temperature. Unreacted Ti and TiN on the film are removed by etching. Next, the second-stage short-time heat treatment is performed at 700 to
This is performed at about 900 ° C. in an N ₂ gas atmosphere for 30 seconds to form stoichiometrically stable TiSi ₂ films 28a, 28b, 29.

Next, an impurity (P) for forming a source / drain region is subjected to an acceleration energy of 40 keV and a dose of 1 × 1.
0 and ^{14 ~1 × 10 15 ions / cm} 2, with normally used (3~5 × 10 ¹⁵⁾ lower dose than ions / cm ^2, the ion implantation and the silicide film and the silicon substrate near the interface, deep junction N ^- diffusion layers 30a and 30b are formed.

(4) Next, as shown in FIG. 1D, the sidewalls 27a and 27b of the silicon oxide film are removed by etching using a reactive ion etching method. Next, using the L-type side walls 31a and 31b as a mask, an acceleration energy of 110 keV is applied below the side walls.
Under the conditions of a dose amount of 3 to 5 × 10 ¹⁵ ions / cm ² , ions for forming source / drain regions of the n ⁺ diffusion layers 32a and 32b having shallow junctions, for example, As ions are implanted.

(5) Next, the L-type side walls 31a,
As shown in FIG. 2A, 31b is removed by etching using a reactive ion etching method. Next, the silicon oxide film on the surface of the silicon active layer and the side wall of the polycrystalline silicon film is removed by etching using buffered hydrofluoric acid containing a surfactant. Then, impurities (P) for forming the LDD layers (n ⁻ layers) 33a and 33b for suppressing the hot carrier effect are subjected to 2 to 4 × 10 ¹³ ions by oblique rotation ion implantation at a large oblique angle (about 45 °). The ion implantation is performed under the conditions of a dose of about / cm ² and an acceleration energy of 30 keV. Next, a heat treatment is performed for a short time in an N ₂ (or NH ₃ ) gas atmosphere at about 800 ° C. for 30 seconds to nitride the silicide film surface and the polycrystalline silicon film sidewall (not shown).

(6) Next, as shown in FIG.
Using a PCVD method, a silicon oxide film 34 is
It is formed about 0 °. Next, a silicon nitride film 35 is formed on the entire surface at about 500 ° by LPCVD. next,
A silicon oxide film 36 and a silicon oxide film 37 containing impurities (B, P) are continuously formed on the entire surface by the normal pressure CVD method. Next, annealing is performed to flatten the silicon oxide film 37 containing impurities and to activate impurities in the source / drain regions.

(7) Next, as shown in FIG. 2 (c), the source / source
A contact hole 38 is formed on the drain region or on the wiring of the gate electrode 24. Next, using a sputtering method, a metal formed of a two-layer or more stacked film is formed, and a usual photolithography technique and an etching technique are used.
A metal wiring 39 is formed.

Next, a second embodiment of the present invention will be described with reference to the drawings.

FIG. 4 is a sectional view showing a manufacturing process of a field-effect transistor according to a second embodiment of the present invention.

In the second embodiment, a source / drain region similar to that of the first embodiment is formed by using one relatively long side wall.

(1) First, as shown in FIG.
LO is placed on the silicon substrate 41 having the (100) plane orientation of the mold.
In order to form an element isolation region by the COS method, a field oxide film 42 is formed to about 4000 °. Next, the gate oxide film 43 is formed at a temperature of 100 ° C. in a highly clean dry oxidation atmosphere.
Degree formed. Next, a polycrystalline silicon film is formed to a thickness of about 3000 ° using a low pressure CVD method. Next, a wiring of the gate electrode 44 made of a polycrystalline silicon film is formed by using a usual photolithography technique and an etching technique. Next, on the silicon active layer surface 45a and the polycrystalline silicon film surface 45b,
An oxide film is formed in a dry oxidation atmosphere at a temperature of about 800 ° C. Next, a silicon oxide film is formed in a thickness of about 2500 to 4000 ° using the LPCVD method or the normal pressure CVD method. Then, using a reactive ion etching method,
By etching only the silicon oxide film, sidewalls 46a and 46b are formed on the side walls of the gate electrode 44.

(2) Next, as shown in FIG.
Using the side walls 46a and 46b as a mask, the silicon oxide film other than the side walls of the gate electrode 44 is etched away by wet etching or reactive ion etching. Next, the oxide film on the silicon active layer surface 45a and the polycrystalline silicon film surface 45b is removed by etching using a buffered hydrofluoric acid solution containing a surfactant. Next, the natural oxide film on the silicon active layer surface 45a and the polycrystalline silicon film surface 45b is etched and removed by plasma surface cleaning in a gas atmosphere of an Ar + H ₂ gas mixture.

Next, without continuously exposing the silicon substrate to the atmosphere, the entire surface is
Refractory metal (Ti, Co, W, Ni, Mo, etc.)
It is formed at about 0-500 °. Next, a refractory metal silicide film, for example, a TiSi ₂ film is formed on the gate electrode 44 and the surface 45b of the silicon active layer serving as a source / drain region in a self-alignment manner by a two-step short-time heat treatment method.
Degree formed. In addition, the first-stage short-time heat treatment
This is performed at about 0 to 700 ° C. in an N ₂ gas atmosphere for 30 seconds.

Next, using a mixture of aqueous ammonia (NH ₃ OH), aqueous hydrogen peroxide (H ₂ O ₂ ) and water (H ₂ O), TiN on silicide and on the sidewalls and field oxidation at room temperature. Unreacted Ti and TiN on the film are removed by etching. Next, the second-stage short-time heat treatment is performed at 700 to
This is performed in an N ₂ gas atmosphere at about 900 ° C. for 30 seconds to obtain a stoichiometrically stable silicide film, ie, a TiSi ₂ film 47.
a, 47b and 48 are formed.

Next, an impurity (P) for forming a source / drain region is doped with an acceleration energy of 40 keV and a dose of 1 × 1.
0 and ^{14 ~1 × 10 15 ions / cm} 2, with normally used (3~5 × 10 ¹⁵⁾ lower dose than ions / cm ^2, the ion implantation and the silicide film and the silicon film substrate near the interface of the junction Deep n ^- diffusion layers 49a and 49b are formed.

(3) Next, as shown in FIG.
The side walls 46a and 46b of the silicon oxide film are removed by etching using a reactive ion etching method.
Further, the silicon oxide film on the surface of the silicon active layer and the side wall of the polycrystalline silicon film is removed by etching using buffered hydrofluoric acid containing a surfactant. Next, the acceleration energy 60
Under the conditions of keV and a dose of 3 to 5 × 10 ¹⁵ ions / cm ² , the source and drain of the n ⁺ diffusion layers 50a and 50b having shallow junctions are formed.
Ions for forming a drain region, for example, As ⁺
Ion implantation.

(4) Next, as shown in FIG.
LDD layer (n ^- layer) 51 for suppressing hot carrier effect
a, 51b to form an impurity (P) at a large oblique angle (4
About 5 °) 2-4 × 10 by oblique rotation ion implantation
¹³ ions / cm ² dose, acceleration energy 3
Ion implantation is performed under the condition of 0 keV. Next, a heat treatment is performed for a short time in an N ₂ (or NH ₃ ) gas atmosphere at about 800 ° C. for 30 seconds to nitride the silicide film surface and the polycrystalline silicon film sidewall (not shown).

(5) After that, FIG. 2B of the first embodiment.
Then, the steps shown in FIG. 2C are performed to complete the field-effect transistor.

As described above, in the second embodiment, the first
Without using the L-type sidewall used in the embodiment of FIG.
A source / drain region having a D structure is formed. Deep n ^- diffusion layer 4 under the silicide film after formation of the silicide film
9a and 49b are the same as in the first embodiment. Using the gate electrode 44 as a mask, n ⁺ diffusion layers 50a and 50b having shallow junctions are formed at an incident angle of 0 °, and thereafter, the LDD layers (n ⁻ layers) 51a and 51
The feature is that b is formed.

Next, a third embodiment of the present invention will be described with reference to the drawings.

FIG. 5 is a sectional view showing a manufacturing process of a field-effect transistor according to a third embodiment of the present invention.

(1) First, as shown in FIG.
LO is placed on the silicon substrate 61 having the (100) plane orientation of the mold.
A field oxide film 62 is formed to about 4000.degree. To form an element isolation region by the COS method. Next, the gate oxide film 63 is formed in a dry oxidation atmosphere with high cleanliness by 100.degree.
Degree formed. Next, a polycrystalline silicon film is formed to a thickness of about 3000 ° using a low pressure CVD method. Next, a gate electrode 64 wiring made of a polycrystalline silicon film is formed by using a usual photolithography technique and an etching technique.

Next, an oxide film is formed on the silicon active layer surface 65a and the polycrystalline silicon film surface 65b in a dry oxidation atmosphere at a temperature of about 800.degree. Next, LPCVD
The silicon nitride film 66 is formed on the entire surface by
It is formed about 00 °. Next, the silicon oxide film is formed in a thickness of 2000 to 30 by using the LPCVD method or the normal pressure CVD method.
It is formed about 00 °. Then, using a reactive (anisotropic) ion etching method, the silicon oxide film 6 containing impurities is formed.
Only 7 is etched to form sidewalls 67a and 67b on the side walls of the gate electrode.

(2) Next, as shown in FIG.
Double sidewall 71 including L-shaped sidewall
Using the masks a, 71b, 67a, and 67b as masks, the silicon nitride film 66 other than the side walls of the gate electrode 64 is etched away by wet etching or reactive ion etching. Next, the oxide film on the silicon active layer surface 65a and the polycrystalline silicon film surface 65b is etched away using a buffered hydrofluoric acid solution containing a surfactant. Next, the natural oxide film on the silicon active layer surface 65a and the polycrystalline silicon film surface 65b is etched and removed by plasma surface cleaning in a gas atmosphere of an Ar + H ₂ gas mixture.

Next, without continuously exposing the silicon substrate to the atmosphere, the entire surface is
Refractory metal (Ti, Co, W, Ni, Mo, etc.)
It is formed at about 0-500 °. Next, a gate electrode 64 made of a polycrystalline silicon film is formed by using a two-step short-time heat treatment method.
A refractory metal silicide film, for example, a TiSi ₂ film of about 600 ° is formed in a self-aligned manner on the upper surface and on the surface 65a of the silicon active layer serving as a source / drain region. Note that the first-stage short-time heat treatment is performed at about 650 ° C. in an N ₂ gas atmosphere for 30 seconds.

Next, using a mixture of aqueous ammonia (NH ₃ OH), aqueous hydrogen peroxide (H ₂ O ₂ ) and water (H ₂ O), TiN on silicide and on the sidewalls and field oxidation at room temperature. Unreacted Ti and TiN on the film are removed by etching. Next, the second-stage short-time heat treatment is performed at 700 to
This is performed in an N ₂ gas atmosphere at about 900 ° C. for 30 seconds to form stoichiometrically stable TiSi ₂ films 68a, 68b, and 69.

Next, an impurity (P) for forming a source / drain region is subjected to an acceleration energy of 40 keV and a dose of 1 × 1.
0 and ^{14 ~1 × 10 15 ions / cm} 2, with normally used (3~5 × 10 ¹⁵⁾ lower dose than ions / cm ^2, the ion implantation and the silicide film and the silicon film substrate near the interface of the junction Deep n ^- diffusion layers 70a and 70b are formed.

(3) Next, as shown in FIG. 5C, the side walls 67a and 67b made of a silicon oxide film are removed by etching using a reactive ion etching method. Next, using the L-type sidewalls 71a and 71b as a mask, an acceleration energy of 110 ke
Under the condition of V and a dose of 3 to 5 × 10 ¹⁵ ions / cm ² , ions for forming source / drain regions of the n ⁺ diffusion layers 72 a and 72 b having shallow junctions, for example, As ions are implanted.

(4) Next, as shown in FIG.
LDD layer (n ⁻ layer) 73 for suppressing hot carrier effect
The impurities (P) for forming the a
About 5 °) 2-4 × 10 by oblique rotation ion implantation
¹³ ions / cm ² dose, acceleration energy 3
Ion implantation is performed under the condition of 0 keV. Next, a heat treatment is performed for a short time in an N ₂ (or NH ₃ ) gas atmosphere at about 800 ° C. for 30 seconds to nitride the silicide film surface and the polycrystalline silicon film side wall (not shown).

(5) After that, FIG. 2B of the first embodiment.
Then, the steps shown in FIG. 2C are performed to complete the field-effect transistor.

As described above, the third embodiment is a modification of the first embodiment using the double sidewall including the L-type sidewall. The difference from the first embodiment is
LDD layer (n ⁻ layer) 73 for suppressing hot carrier effect
a, 73b are formed.

That is, the L-type side walls 71a, 71
While leaving 1b, first, n ⁺ diffusion layers 72a and 72b having shallow junctions are formed by ion implantation at an incident angle of 0 °.
Further, while the L-type sidewalls 71a and 71b are left, the LDD layer (n ⁻
The layers 73 a and 73 b are formed so as to overlap the gate electrode 64.

In the above embodiment, an n-channel MOSFET has been described.
It goes without saying that the same applies to the case of ET.

The present invention is not limited to the above-described embodiment, but various modifications are possible based on the spirit of the present invention, and these are not excluded from the scope of the present invention.

[0069]

As described in detail above, according to the present invention, (1) the source / drain regions are silicided outside the relatively long sidewalls, and the diffusion layer depth is only in those regions. Since the depth is increased, an increase in junction leak current can be suppressed without increasing a short channel effect of the transistor.

(2) Since the silicidation of the source / drain region is performed before the diffusion layer is formed, the silicidation reaction is stably generated at a low temperature without being affected by the natural oxide film. As a result, a sufficiently low resistance can be stably realized with good reproducibility.

(3) Since there is no knock-on of oxygen by the mask oxide film at the time of ion implantation into the source / drain regions,
In the heat treatment of the silicidation reaction, the silicidation reaction can be uniformly generated at a low temperature.

[0072] (4) More specifically, sufficiently shallow source and drain formation ion implantation dose junction depth, and since that is controlled in a range as not to lower the current driving capability, fine also in MOSFET, sufficient short-channel effect is suppressed, and highly driving capability of MOSF
ET becomes feasible.

(5) The formation of a deep diffusion layer in the silicidation region utilizes solid-phase diffusion from a silicide film.
It is possible to obtain a smooth interface in which the interface between the silicide and the diffusion layer is not uneven, and to stably realize the ohmic junction with high impurity concentration at the interface between the silicide and the diffusion layer with high reproducibility.

(6) Since ion implantation for forming a shallow diffusion layer and forming an LDD (n ⁻ ) layer is performed after the silicidation, the activation of impurities in the ion implantation is performed by flattening annealing of the interlayer insulating film. Even if it is performed at the same time, it is possible to compensate for the decrease in the impurity concentration at the interface between the silicide and the diffusion layer, and a sufficient ohmic junction can be realized between the silicide and the diffusion layer.

In particular, in addition to the above-described effects, the L-type sidewall does not cause variation in the sidewall width due to etching, so that the electrical gate length does not vary and the MOSFET having a small variation in threshold voltage can be stably used. Can be formed. Further, since the ion implantation for forming the LDD (n ⁻ ) layer is performed directly on the surface of the silicon active layer obliquely and obliquely by a rotary ion implantation method without a mask oxide film, oxygen in the mask oxide film is injected into the silicon substrate. Can be prevented from being inactivated due to knock-on.

Further, in particular, in addition to the above-mentioned effects, shallow n ⁺
By making the diffusion layer region of the junction overlap with the gate electrode, it is possible to avoid generation of a drain leak current due to an interband tunnel.

Further, in particular, n ^{− in the} source / drain region
After forming a layer, an n ⁺ layer and an LDD (n ⁻ ) layer, the surface of the silicide, the surface of the polycrystalline silicon film and the surface of the silicon active layer are simultaneously subjected to nitriding and crystal recovery of the silicide film by a low-temperature and short-time heat treatment to relieve film stress. Since the heat treatment is performed, redistribution of the impurities in the diffusion layer does not occur due to the subsequent heat treatment, and aggregation of the silicide film does not occur, so that a sufficient low-resistance diffusion layer and an ohmic junction can be formed.

Further, in particular, since the interlayer insulating film has a four-layer structure of a silicon oxide film, a silicon nitride film, a silicon oxide film and a silicon oxide film containing impurities from the lower layer, the film stress on the silicide film is relaxed, The heat resistance of the silicide film against the thermal process becomes sufficient. In addition, the LPCVD method or the plasma CV
Since the silicon nitride film obtained by the method D is included, the atmosphere for heat treatment for flattening the surface of the interlayer insulating film can be used in all atmospheres of N ₂ , O ₂ , and wet O ₂ gas. In particular, by using a wet O ₂ gas atmosphere, planarization can be performed at a lower temperature than N ₂ treatment.

Further, since the surface of the silicide film is made of TiN, the TiN surface is not oxidized after the formation of the contact hole, and a sufficient ohmic contact can be obtained in bonding with the metal wiring. Further, the current step of removing the natural oxide film at the bottom of the minute contact hole by HF dip after the formation of the contact hole can be used as it is. The HF is preferably a buffered hydrofluoric acid solution containing a surfactant.

[Brief description of the drawings]

FIG. 1 is a sectional view (part 1) of a process for manufacturing a field-effect transistor according to a first embodiment of the present invention.

FIG. 2 is a sectional view (part 2) of a process for manufacturing a field-effect transistor according to the first embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a manufacturing process of a MOSFET having a conventional salicide structure.

FIG. 4 is a cross-sectional view illustrating a manufacturing process of a field-effect transistor according to a second embodiment of the present invention.

FIG. 5 is a cross-sectional view illustrating a manufacturing process of a field-effect transistor according to a third embodiment of the present invention.

[Explanation of symbols]

21, 41, 61 Silicon substrate 22, 42, 62 Field oxide film 23, 43, 63 Gate oxide film 24, 44, 64 Gate electrode 26, 35, 66 Silicon nitride film 27a, 27b, 46a, 46b, 67a, 67b
Side walls 28a, 28b, 29, 47a, 47b, 48, 68
a, 68b, 69 TiSi ₂ films 30a, 30b, 49a, 49b, 70a, 70b
N ^- diffusion layers 31a, 31b, 71a, 71b having a deep junction L-type sidewalls 32a, 32b, 50a, 50b, 72a, 72b
N ⁺ diffusion layers with shallow junctions 33a, 33b, 51a, 51b, 73a, 73b
LDD layer (n ^- layer) 34, 36, 37 Silicon oxide film 38 Contact hole 39 Metal wiring

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 29/78 H01L 21/336 H01L 21/8238 H01L 27/092

Claims (4)

(57) [Claims] (A) forming a gate electrode on a first insulating film formed on a main surface of a semiconductor substrate; and (b) forming a second electrode on the first insulating film including the gate electrode.
(C) forming a side wall portion facing the second insulating film covering a side wall of the gate electrode with a third insulating film; and (d) forming the gate electrode. to leave the second insulating film and said second insulating film covering at the side wall portion covering the side wall of a step of etching the second insulating film, said first exposed (e) Removing the insulating film of the semiconductor
Exposing the main surface of the body substrate; and (f) the exposed gate electrode and the exposed semiconductor.
Forming a refractory metal film on the main surface of the substrate; and (g) heat treating the refractory metal film and silicon by heat treatment.
Forming a silicide film; and (h) implanting impurity ions into the main surface of the semiconductor substrate except for the gate electrode, the sidewall portion, and a region covered with the remaining second insulating film. (I) removing the sidewall portion; and (j) implanting impurity ions into the main surface of the semiconductor substrate except for the region covered with the gate electrode and the remaining second insulating film. (K) removing the remaining second insulating film; and (l) implanting impurity ions into the main surface of the semiconductor substrate except for a region covered with the gate electrode. a third ion implantation step, (m) then activating the impurity ions by heat treatment, field effect you want to said applying step for forming a source region and a drain region Method of manufacturing a Njisuta. After wherein said third ion implantation step, a step of nitriding the exposed said silicide surface, then, a method of manufacturing a field effect transistor of claim 1, wherein the performing the thermal treatment process. (A) forming a gate electrode on a first insulating film formed on a main surface of the semiconductor substrate; and (b) forming a side wall portion of a second insulating film on a side wall of the gate electrode. And (c) removing the exposed first insulating film to remove the semiconductor.
Exposing the main surface of the body substrate; and (d) the exposed gate electrode and the exposed semiconductor.
Forming a refractory metal film on the main surface of the substrate; and (e) heat-treating the refractory metal film and silicon by heat treatment.
Ri and forming a silicide film, a first ion implantation step of implanting impurity ions into the semiconductor substrate main surface except an area coated with (f) the gate electrode and the side wall portion, (g) the (H) a second ion implantation step of implanting impurity ions into the main surface of the semiconductor substrate except for a region covered with the gate electrode; and (i) subsequently, the impurity is formed by heat treatment. A method for manufacturing a field effect transistor, comprising the step of activating ions to form a source region and a drain region. 4. A method for manufacturing a field effect transistor according to claim 3 , wherein after the second ion implantation step, a step of nitriding the exposed surface of the silicide film is performed, and thereafter, the heat treatment step is performed. .