JP2563798B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

Info

Publication number
JP2563798B2
JP2563798B2 JP62124914A JP12491487A JP2563798B2 JP 2563798 B2 JP2563798 B2 JP 2563798B2 JP 62124914 A JP62124914 A JP 62124914A JP 12491487 A JP12491487 A JP 12491487A JP 2563798 B2 JP2563798 B2 JP 2563798B2
Authority
JP
Japan
Prior art keywords
oxide film
film
semiconductor substrate
nitride film
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP62124914A
Other languages
Japanese (ja)
Other versions
JPS63289832A (en
Inventor
正浩 竹内
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP62124914A priority Critical patent/JP2563798B2/en
Publication of JPS63289832A publication Critical patent/JPS63289832A/en
Application granted granted Critical
Publication of JP2563798B2 publication Critical patent/JP2563798B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Element Separation (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置の製造方法に関し、特に素子分
離方法に関する。
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to an element isolation method.

〔従来の技術〕[Conventional technology]

従来の、半導体装置の素子分離方法を、第2図(a)
〜(f)を用いて説明する。まず第2図(a)のように
第1導電型の半導体基板上に酸化膜2を形成後、窒化膜
3を形成する。次に第2図(b)のように写真触刻法に
より前記窒化膜3の不要部分を除去する。次に第2図
(c)のように前記半導体基板と同一導電型不純物をイ
オン注入する。その後、熱酸化を行ない第2図(d)の
ように前記窒化膜を除去した部分に素子分離用酸化膜4
を形成する。このとき前記半導体基板1の前記酸化膜4
との界面付近の不純物濃度は、前記半導体基板1の基板
不純物濃度より濃くなる。この部分が、いわゆるチャン
ネルストッパと呼ばれる領域となる。次に第2図(e)
のように前記酸化膜2と前記窒化膜3を除去する。次に
熱酸化により酸化膜6を形成し、続いて多結晶シリコン
膜7を形成した後、写真触刻法により不要な多結晶シリ
コン膜を除去して第2図(f)のようにmosトランジス
タを形成する。
A conventional element isolation method for a semiconductor device is shown in FIG.
This will be described with reference to (f). First, as shown in FIG. 2A, an oxide film 2 is formed on a semiconductor substrate of the first conductivity type, and then a nitride film 3 is formed. Next, as shown in FIG. 2B, unnecessary portions of the nitride film 3 are removed by photolithography. Next, as shown in FIG. 2C, the same conductivity type impurities as those of the semiconductor substrate are ion-implanted. After that, thermal oxidation is performed, and as shown in FIG. 2D, the element isolation oxide film 4 is formed on the portion where the nitride film is removed.
To form. At this time, the oxide film 4 of the semiconductor substrate 1
The impurity concentration near the interface with and becomes higher than the substrate impurity concentration of the semiconductor substrate 1. This portion becomes a so-called channel stopper. Next, FIG. 2 (e)
As described above, the oxide film 2 and the nitride film 3 are removed. Next, an oxide film 6 is formed by thermal oxidation, and then a polycrystalline silicon film 7 is formed. Then, an unnecessary polycrystalline silicon film is removed by photolithography to remove the mos transistor as shown in FIG. 2 (f). To form.

〔発明が解決しようとする問題点〕[Problems to be solved by the invention]

しかし、前述の従来技術では素子分離用酸化膜4を形
成するとき、高温で長時間の酸化を行なうため、チャン
ネルストッパ領域5の不純物が第2図(f)のようにmo
s型トランジスタの能動領域の表面付近まで拡散してし
まいmos型トランジスタのスレッショルド電圧を変化さ
せる、いわゆる狭チャンネル効果が起きてしまうという
問題点を有する。
However, when the element isolation oxide film 4 is formed in the above-mentioned conventional technique, since the oxidation is performed at a high temperature for a long time, impurities in the channel stopper region 5 are mo as shown in FIG.
There is a problem in that the so-called narrow channel effect occurs that the threshold voltage of the mos type transistor is changed by diffusing to the vicinity of the surface of the active region of the s type transistor.

そこで本発明はこのような問題点を解決するもので、
その目的とするところはチャンネルストッパを形成して
もチャンネルストッパ領域の不純物がmosトランジスタ
の能動領域の表面付近まで拡散しないようにすることに
ある。
Therefore, the present invention solves such a problem,
The purpose is to prevent impurities in the channel stopper region from diffusing to the vicinity of the surface of the active region of the mos transistor even if the channel stopper is formed.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の半導体装置の製造方法は、(a)半導体基板
中に基板と同一導電型の不純物を注入する工程、(b)
前記半導体基板上に第1の酸化膜を形成する工程、
(c)前記第1の酸化膜上にシリコン窒化膜を形成する
工程、(d)前記シリコン窒化膜の一部分を除去する工
程、(e)前記シリコン窒化膜が除去された部分に素子
分離用のシリコン酸化膜を形成する工程、(f)前記
(d)工程で除去されていないシリコン窒化膜と、前記
第1の酸化膜を除去する工程、(g)能動領域上にmos
トランジスタを形成する工程、を有する半導体装置の製
造方法であって、前記(a)工程の前記不純物の注入
は、前記不純物が素子分離領域では前記素子分離用のシ
リコン酸化膜と前記半導体基板との界面に位置し、かつ
前記能動領域では前記能動領域表面付近まで拡散しない
深さに位置する所定の条件で実施されることを特徴とす
る。
The method of manufacturing a semiconductor device according to the present invention includes (a) a step of implanting an impurity of the same conductivity type as that of the substrate into the semiconductor substrate, (b)
Forming a first oxide film on the semiconductor substrate,
(C) a step of forming a silicon nitride film on the first oxide film, (d) a step of removing a part of the silicon nitride film, and (e) a part for element isolation in the part where the silicon nitride film is removed. A step of forming a silicon oxide film, (f) a step of removing the silicon nitride film not removed in the step (d) and the step of removing the first oxide film, and (g) a mos on the active region.
A method of manufacturing a semiconductor device, comprising the step of forming a transistor, wherein in the step (a) of implanting the impurities, the impurities are separated into a silicon oxide film for element isolation and the semiconductor substrate in an element isolation region. It is characterized in that it is carried out under a predetermined condition of being located at the interface and at a depth where it does not diffuse to the vicinity of the surface of the active region in the active region.

〔実施例〕〔Example〕

本発明による実施例を第1図(a)〜(f)を用いて
詳しく説明する。まず第1図(a)のように第1導電型
の半導体基板、たとえばP型シリコン基板中に前記半導
体基板と同一導電型不純物、たとえばボロンをイオン注
入により1×1011cm-2〜1×1014cm-2のドーズ量で、不
純物のピークが0.2μm〜1μmとなるようなエネルギ
ーで打込む。その後800℃〜1000℃の温度でアニールを
行ない前記イオン注入したボロンを活性化する。次に第
1図(b)のように熱酸化によりシリコン酸化膜2を10
0Å〜1000Å形成後、CVD法によりシリコン窒化膜3を50
0Å〜2000Å形成する。次に第1図(c)のように写真
触刻法により前記シリコン窒化膜3の不要部分を除去す
る。次に熱酸化を行ない、第1図(d)のように前記シ
リコン窒化膜を除去した部分に素子分離用シリコン酸化
膜4を5000Å〜20000Å形成する。その後第1図(e)
のように前記シリコン酸化膜2と前記シリコン窒化膜3
を除去する。次に第1図(f)のように熱酸化により10
0Å〜1000Åのシリコン酸化膜6を形成し、続いてCVD法
により1000Å〜5000Åの多結晶シリコン膜7を形成した
後、写真触刻法により不要な多結晶シリコン膜を除去し
て第1図(f)のようにmosトランジスタを形成する。
An embodiment according to the present invention will be described in detail with reference to FIGS. First, as shown in FIG. 1A, an impurity of the same conductivity type as the semiconductor substrate, for example, boron is ion-implanted into a semiconductor substrate of the first conductivity type, for example, a P-type silicon substrate, by ion implantation to reach 1 × 10 11 cm −2 to 1 ×. Implanting is performed with energy so that the impurity peak is 0.2 μm to 1 μm at a dose amount of 10 14 cm −2 . Then, annealing is performed at a temperature of 800 ° C. to 1000 ° C. to activate the ion-implanted boron. Next, as shown in FIG. 1 (b), the silicon oxide film 2 is removed by thermal oxidation.
After forming 0Å to 1000Å, the silicon nitride film 3 is formed to 50 by CVD method.
0Å ~ 2000Å form. Next, as shown in FIG. 1C, the unnecessary portion of the silicon nitride film 3 is removed by photolithography. Next, thermal oxidation is performed to form a device isolation silicon oxide film 4 at 5000Å to 20000Å in the portion where the silicon nitride film is removed as shown in FIG. 1 (d). After that, Fig. 1 (e)
Like the silicon oxide film 2 and the silicon nitride film 3
Is removed. Next, as shown in Fig. 1 (f), 10
A silicon oxide film 6 of 0Å to 1000Å is formed, and then a polycrystalline silicon film 7 of 1000Å to 5000Å is formed by a CVD method, and then an unnecessary polycrystalline silicon film is removed by a photolithography method. A mos transistor is formed as in f).

〔発明の効果〕〔The invention's effect〕

以上述べたように、本発明によれば、チャンネルスト
ッパとなる不純物濃度の濃い部分は、素子分離領域では
素子分離酸化膜と半導体基板の界面付近にあり、mosト
ランジスタの能動領域では半導体基板の深い部分にで
き、能動領域の表面付近までは、この不純物は拡散しな
い。このため従来のチャンネルストッパの効果を持ちな
がらmosトランジスタの狭チャンネル効果は起こらない
という効果を有する。
As described above, according to the present invention, the portion having a high impurity concentration that serves as a channel stopper is near the interface between the element isolation oxide film and the semiconductor substrate in the element isolation region, and deep in the semiconductor substrate in the active region of the mos transistor. This impurity does not diffuse up to near the surface of the active region. Therefore, the narrow channel effect of the mos transistor does not occur while having the effect of the conventional channel stopper.

【図面の簡単な説明】[Brief description of drawings]

第1図(a)〜(f)は、本発明の実施例による半導体
装置の製造工程断面図、第2図(a)〜(f)は従来法
による半導体装置の製造工程断面図を示す。 1……半導体基板 2……酸化膜 3……窒化膜 4……素子分離用酸化膜 5……チャンネルストッパ領域 6……ゲート酸化膜 7……ゲート電極
1 (a) to 1 (f) are sectional views of a semiconductor device according to an embodiment of the present invention, and FIG. 2 (a) to 2 (f) are sectional views of a semiconductor device according to a conventional method. 1 ... Semiconductor substrate 2 ... Oxide film 3 ... Nitride film 4 ... Element isolation oxide film 5 ... Channel stopper region 6 ... Gate oxide film 7 ... Gate electrode

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】(a)半導体基板中に基板と同一導電型の
不純物を注入する工程、 (b)前記半導体基板上に第1の酸化膜を形成する工
程、 (c)前記第1の酸化膜上にシリコン窒化膜を形成する
工程、 (d)前記シリコン窒化膜の一部分を除去する工程、 (e)前記シリコン窒化膜が除去された部分に素子分離
用のシリコン酸化膜を形成する工程、 (f)前記(d)工程で除去されていないシリコン窒化
膜と、前記第1の酸化膜を除去する工程、 (g)能動領域上にmosトランジスタを形成する工程、 を有する半導体装置の製造方法であって、 前記(a)工程の前記不純物の注入は、前記不純物が素
子分離領域では前記素子分離用のシリコン酸化膜と前記
半導体基板との界面に位置し、かつ前記能動領域では前
記能動領域表面付近まで拡散しない深さに位置する所定
の条件で実施されることを特徴とする半導体装置の製造
方法。
1. A process of implanting an impurity of the same conductivity type as that of a substrate into a semiconductor substrate, a process of forming a first oxide film on the semiconductor substrate, and a process of forming the first oxide film. A step of forming a silicon nitride film on the film, (d) a step of removing a part of the silicon nitride film, (e) a step of forming a silicon oxide film for element isolation in the part where the silicon nitride film is removed, (F) a silicon nitride film not removed in the step (d) and a step of removing the first oxide film; (g) a step of forming a mos transistor on the active region; In the step (a) of implanting the impurities, the impurities are located at the interface between the silicon oxide film for element isolation and the semiconductor substrate in the element isolation region, and in the active region the active region. Spread near the surface Method of manufacturing a semiconductor device characterized in that it is carried out under predetermined conditions to be located at a depth that does not.
JP62124914A 1987-05-21 1987-05-21 Method for manufacturing semiconductor device Expired - Lifetime JP2563798B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62124914A JP2563798B2 (en) 1987-05-21 1987-05-21 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62124914A JP2563798B2 (en) 1987-05-21 1987-05-21 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPS63289832A JPS63289832A (en) 1988-11-28
JP2563798B2 true JP2563798B2 (en) 1996-12-18

Family

ID=14897244

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62124914A Expired - Lifetime JP2563798B2 (en) 1987-05-21 1987-05-21 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP2563798B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5132241A (en) * 1991-04-15 1992-07-21 Industrial Technology Research Institute Method of manufacturing minimum counterdoping in twin well process

Also Published As

Publication number Publication date
JPS63289832A (en) 1988-11-28

Similar Documents

Publication Publication Date Title
EP0090940B1 (en) Method of forming emitter and intrinsic base regions of a bipolar transistor
CA1063731A (en) Method for making transistor structures having impurity regions separated by a short lateral distance
US4629520A (en) Method of forming shallow n-type region with arsenic or antimony and phosphorus
JP2663402B2 (en) Method for manufacturing CMOS integrated circuit device
US4841347A (en) MOS VLSI device having shallow junctions and method of making same
JPH09199719A (en) Manufacture of semiconductor device
US4362574A (en) Integrated circuit and manufacturing method
JPH0645343A (en) Semiconductor device provided with borosilicate glass spacer and its manufacture
JP2563798B2 (en) Method for manufacturing semiconductor device
JPS624339A (en) Semiconductor device and manufacture thereof
JP2843037B2 (en) Method for manufacturing semiconductor device
JPH0575041A (en) Cmos semiconductor device
JP2897215B2 (en) Method for manufacturing semiconductor device
JPS5837990B2 (en) Manufacturing method of semiconductor device
JP2505159B2 (en) Method for manufacturing semiconductor device
JP3244066B2 (en) Method for manufacturing semiconductor device
JP3317220B2 (en) Method for manufacturing semiconductor device
JPH07120793B2 (en) Method for manufacturing semiconductor device
JP3108927B2 (en) Method for manufacturing semiconductor device
JP2570292B2 (en) Method for manufacturing semiconductor device
JPS60134472A (en) Manufacture of semiconductor device
JP3041886B2 (en) Method for manufacturing semiconductor device
JPH065750B2 (en) Method for manufacturing semiconductor device
JPS6367778A (en) Manufacture of semiconductor device
JPH06224380A (en) Manufacture of semiconductor device

Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term
FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20070919

Year of fee payment: 11