JP3317220B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a shallow impurity layer.

[0002]

2. Description of the Related Art In recent years, with the miniaturization of LSIs, the depth of impurity regions formed in a semiconductor substrate has been gradually reduced. As a semiconductor device that requires such a structure,
Hereinafter, a conventional method for manufacturing a semiconductor device will be described with reference to FIGS.

First, an insulating film 110 is formed on a silicon single crystal substrate 100 as a semiconductor substrate by, for example, thermal oxidation, nitridation, CVD, or the like. Subsequently, a semiconductor film or a metal film is formed by a CVD method or a PVD method. In the case of a semiconductor film, a film of, for example, silicon polycrystal or amorphous silicon is formed. In the case of a metal film, for example, a semiconductor film having electrical conductivity by doping phosphorus or boron into the semiconductor film is formed. Next, after a fine pattern is formed using a photolithography method, the semiconductor film or the metal film is etched by a dry etching method or the like, and fine processing is performed. Thus, the insulating film 110 is formed on the semiconductor substrate 100.
Through which the conductive film such as a semiconductor or a metal remains 120
(Specifically, it becomes a gate electrode), and a portion 130 which has already been removed by etching is formed. Note that an electrical isolation region 140 is usually formed on the silicon substrate (FIG. 2A).

Next, in the above state, the first
In order to form a junction, impurities are introduced using the remaining conductive film portion 120 as a mask. In the case of a silicon substrate, for example, arsenic is used for doping N-type, and boron is used for doping P-type. Here, description is made using P-type boron. For example, when forming a 0.25 micron MOS transistor, the doping depth required here is about 120 nm. For this purpose, it is necessary to dope boron with an effective energy of about 10 keV using an ion implantation method or a plasma implantation method, and then to perform heat treatment for electrical activation. More specifically, boron is implanted at an energy of 10 keV into boron by 1 × 10 by ion implantation or plasma implantation (doping).
^A first impurity doping layer 145 is formed by introducing a dose of ¹⁴ (atoms / cm ² ) (FIG. 2B).

Then, impurities are introduced to form a second junction having a deeper junction. Specifically, first, C
An insulating film is formed by a VD method. This insulating film is used as a spacer for forming an electrode by selective doping when the remaining conductive film is used as a gate electrode of a MOS transistor. Specifically, the deposited insulating film is etched back by plasma, and a film remaining on the side wall of the conductive film is used as a spacer 170 (FIG. 2C). After that, impurities, for example, boron are doped at 30 keV and the dose is 1 × by ion implantation or plasma implantation (doping).
A dose of 10 ¹⁶ (atoms / cm ² ) is implanted and finally 100
Anneal at 0 ° C. for 10 seconds. The junctions thus formed are the first junction 175 which is a shallow junction and the second junction 180 which is a deep junction (FIG. 2D).

[0006]

As described above, according to the conventional method of manufacturing a semiconductor device, in a semiconductor device having a shallow junction and a deep junction, impurities are introduced for forming each junction. The heat treatment described above simultaneously activates the impurities. That is, the source / drain region which is a deep junction and the source / drain extension which is a shallow junction are activated simultaneously.

As the miniaturization and the improvement of the characteristics of the semiconductor device further progress in the future, the junction depth of the diffusion layer at the extended portion of the source and the drain becomes extremely shallow, and the heat treatment is performed at a higher speed, at a lower temperature and in a shorter time. The present inventor has found that it is difficult to recover defects due to doping of impurities below the spacer on the side wall of the electrode. If the above problems occur, as a result, problems such as deterioration of reliability, increase of junction leak current, and decrease of drain current value occur.

In view of the above problem, the present invention provides a method of manufacturing a semiconductor device which can easily recover a defect generated when doping is performed to form an impurity region even in a semiconductor device having a shallow junction. Its primary purpose is to provide a method.

[0009]

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention comprises a first step of forming a gate electrode on a semiconductor substrate and a first step of forming a gate electrode using the gate electrode as a mask. A second step of introducing a second impurity, a third step of performing a first heat treatment for recovering a defect generated in the semiconductor substrate in the second step after the second step, After the third step, a fourth step of forming a side spacer on the side surface of the gate electrode, a fifth step of introducing a second impurity part using the gate electrode and the side spacer as a mask, After the step, a second step for activating the first impurity and the second impurity is performed.
And a sixth step of performing the heat treatment.

According to this structure, since the heat treatment is performed in a state where the side spacer is not formed, a defect generated at the time of introducing the first impurity can be easily removed.

Further, the present invention provides the above-mentioned configuration,
Heat treatment temperature is lower than the second heat treatment,
Preferably, the first heat treatment is a heat treatment by rapid thermal annealing.

[0012]

DETAILED DESCRIPTION OF THE INVENTION The inventor of the present invention has found that the reason for the inability to sufficiently recover defects in the shallow junction region shown in FIG. 2 is that a region where a shallow junction is formed during heat treatment for activation is performed. It was found that a side spacer, which is an insulating film pattern, was present on the upper part of the substrate, and that the side spacer eliminated an escape area (a defect comes out) where the defect was recovered.

Therefore, the present inventor solves the above problem by performing a heat treatment for defect recovery after doping of impurities for forming a shallow junction and before forming a side spacer. I thought about solving it.

Hereinafter, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described in detail with reference to FIG. In the following, description will be made by taking a MOS transistor having a shallow junction as an example. However, the present invention relates to a semiconductor having a shallow junction and a region on which a film such as an insulating film is formed thereafter. The present invention can be applied to a device manufacturing method.

First, an insulating film 110 (specifically, a silicon oxide film) is formed on a silicon single crystal substrate 100 as a semiconductor substrate by, for example, thermal oxidation, nitridation, CVD, or the like. Subsequently, a semiconductor film or a metal film is formed by a CVD method or a PVD method. In the case of a semiconductor film, for example, polycrystalline silicon or amorphous silicon is used, and in the case of a metal film, a film having electrical conductivity by doping with phosphorus or boron is formed. The carrier concentration at this time is 1 × 10 ¹⁹
It is desirable to control within the range of 1 × 10 ²¹ . Subsequently, after a fine pattern is formed by a photolithography method or the like, the semiconductor film or the metal film is etched by a dry etching method or the like and subjected to fine processing, so that the semiconductor or metal film is formed on the semiconductor substrate via an insulating film. Of the remaining conductive film 120 (specifically, the gate electrode of the MOS transistor) and the portion 1 already removed by etching
30 are formed. Further, an electrical isolation region 140 may be formed in the silicon substrate (FIG. 1A).

Next, in this state, a first impurity for forming a shallow junction is introduced. For that purpose, a doping method using energetic particles, an ion implantation method, or a plasma implantation method is used. Subsequently, heat treatment is performed so as to suppress unnecessary thermal diffusion at the time of electrical activation and maintain a sufficiently shallow profile. Therefore, a first annealing is performed on the impurities introduced by the ion implantation method or the plasma implantation (doping) method by using a rapid thermal annealing process. This heat treatment attempts to substantially recover lattice defects of the semiconductor substrate caused by the introduction of energetic particles (doping of impurities for forming a shallow junction). The junction formed as described above is the first junction 177 having few lattice defects (FIG. 1).
(B)). At this time, there is no need to completely activate the first impurity introduced by the first annealing. This is because the first annealing is intended to recover a defect generated by the introduction of the first impurity.

More specifically, in the case of a silicon substrate, for example, arsenic is used for doping N-type and boron is used for doping P-type. Here, the description is made using P-type boron (for example, B ₁₀ H ₁₄ is used as a gas). Assuming a process at the time of manufacturing a semiconductor device, for example, when forming a 0.15 micron MOS device, the doping depth required here is about 80 nm. For this purpose, the effective energy of boron is determined using a doping method using energetic particles, an ion implantation method or a plasma implantation method.
It is necessary to perform doping at about keV, and it is necessary to perform heat treatment so as to suppress unnecessary thermal diffusion and maintain a sufficiently shallow profile during subsequent electrical activation. Therefore, the ion implantation method or the plasma implantation (doping) method
Boron is introduced at an energy of less than 0 keV, for example, 2 keV in a range of 1 × 10 ¹³ to 1 × 10 ¹⁶ (atoms / cm ² ), for example, about 1 × 10 ¹⁴ (atoms / cm ² ).
Subsequently, first annealing is performed for 1 second to 1 minute, for example, at 800 ° C. for 20 seconds using a so-called rapid thermal process. By this heat treatment, lattice defects of the silicon single crystal received by the introduction of energetic particles can be substantially recovered.

Next, in this state, a second impurity for forming a deep junction is introduced. Specifically, first, CV
An insulating film is formed by Method D. The purpose of this is to use an insulating film as a spacer for forming an electrode by selective doping when the remaining conductive film is used as a gate electrode of a MOS transistor. Specifically, the deposited insulating film is etched back by plasma to form a film remaining on the side wall of the conductive film as a spacer 170 (FIG. 1).
(C)). Thereafter, as shown in FIG. 1D, impurities such as boron are ion-implanted or plasma-implanted (doped) to an energy of 2 keV or more, for example, 10 ke.
At a dose of V, a dose of, for example, 1 × 10 ¹⁶ (atoms / cm ² ) is implanted in a range of 1 × 10 ¹⁴ to 1 × 10 ¹⁷ (atoms / cm ² ), and then a second annealing is performed at, for example, 1000 ° C. for 10 seconds. .
The junction formed by this heat treatment is the second junction 180, and the second annealing completely activates the first impurity and the second impurity.

As described above, according to the present invention, the impurity introduction for forming a shallow junction is performed, and thereafter, the heat treatment is performed before an insulating film pattern is formed on this region. The defect generated at the time can be easily escaped. It is not preferable to perform the heat treatment at this time so that the introduced impurities are sufficiently activated.
This is because, if heat treatment for sufficiently activating the impurities is performed, accelerated diffusion of the impurities introduced by the defects occurs, and it becomes difficult to form a shallow junction.
Therefore, this heat treatment is preferably a heat treatment for the purpose of recovering a defect in a region into which an impurity is introduced to form a shallow junction. In such a case, for example, the temperature of the first annealing (heat treatment) may be lower than the temperature of the second annealing (heat treatment). In addition,
In the above embodiment, the first heat treatment is performed by rapid thermal annealing. However, in a normal heat treatment, impurities may diffuse more than necessary. It is preferable to carry out by thermal annealing.

In the above example, boron has been described as an example of an impurity.
When Sb is used at a voltage of kV or less, it is preferable to perform the first impurity introduction at a voltage of 20 kV or less.

[0021]

According to the present invention, by performing lattice defect removal and recovery at a relatively low temperature immediately after the introduction of the first impurity, high-speed diffusion caused by the lattice defect can be achieved during subsequent electrical activation at a high temperature. Therefore, a very shallow junction can be formed at a high concentration.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a manufacturing process of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view of a manufacturing process of a conventional semiconductor device.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 silicon substrate 120 conductive film remaining portion 130 conductive film removed portion 140 isolation region 145 first impurity doping layer 170 side spacer 175 first junction (shallow junction) 177 first junction with few lattice defects 180 second junction ( Deep junction) 500 semiconductor substrate

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 29/78 H01L 21/336

Claims (2)

(57) [Claims] A first electrode for forming a gate electrode on a semiconductor substrate;
A second step of introducing a first impurity using the gate electrode as a mask; and a step of recovering a defect generated in the semiconductor substrate in the second step after the second step. A third step of performing a first heat treatment using a rapid thermal process under a condition that the first impurity is not completely activated, and forming a side spacer on the side surface of the gate electrode after the third step. A fourth step;
A fifth step of introducing a second impurity using the gate electrode and the side spacer as a mask, and a second step for activating the first impurity and the second impurity after the fifth step. And a sixth step of performing a heat treatment. 2. The method according to claim 1, wherein the temperature of the first heat treatment is lower than the temperature of the second heat treatment.