JPH06224380A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the depletion of a boundary surface between a gate oxide film and a gate electrode without an increase in the number of processes by forming a silicon film under specific conditions using Si2H6, and by activating each impurity introduced into each of the regions which constitute an n-type element and a p-type element. CONSTITUTION:A p-type well 31 is formed in a region where an n-type element is formed, and an n-type well 30 is formed in a region where a p-type element is formed. A wafer is then subjected to thermal oxidation, so that a gate oxide film 5 is formed on an element formation region of a semiconductor substrate 1. A silicon film 3 is formed over the entire surface of the gate oxide film 5 thus formed using Si2H6 in the atmosphere at the temperature below 580 deg.C. The silicon film 3 is patterned, so that a gate electrode is formed. After the formation of the gate electrode, an n-type impurity is introduced into the region where an n-type element is formed, and a p-type impurity is introduced into the region where a p-type element is formed. These impurities are then activated, and hence it is possible to form the silicon film 3 in an amorphous state.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to the use of metal / metal on the same substrate.
An n-type transistor having an oxide / semiconductor structure (hereinafter referred to as “nMOSFET”) and a p-type transistor having a metal / oxide / semiconductor structure (hereinafter referred to as “pMO”)
SFET ')).

[0002]

2. Description of the Related Art Conventionally, a gate electrode of a complementary MOSFET having both an nMOSFET and a pMOSFET on the same substrate is used as a material for forming a gate electrode such as a polycrystalline silicon film, and an n-type impurity such as phosphorus or arsenic (Type dopant) was ion-implanted or solid layer diffused, and then patterned to form. The nMOSFET is a surface channel type and the pMOSFET is a buried channel type. That is, the conventional complementary MOSFET has an nM
The gate electrodes of both the OSFET and the pMOSFET are n-type, and the source / drain of the nMOSFET is n-type.
The pMOSFET has a structure in which the source and drain are p-type.

However, in recent years, miniaturization and high integration of semiconductor devices have progressed, and along with this, miniaturization of elements has been vigorously performed. For example, the minimum line width is 0.5 μm.
A fine MOSFET of m or less is used. And, in the above-mentioned minute MOSFET, it is essential to suppress the short channel effect. Therefore, a p-type gate electrode of the pMOSFET has been used, and a surface-channel pMOSFET having a higher capability of suppressing the short channel effect than the buried channel type has been used.

In the complementary MOSFET, the nMO
Bijian Davari et al. Have described IEEE Transaction on electron device, vol.39, p as a technology for making both the SFET channel and the pMOSFET channel a surface channel type.
967,1992 ', and Wen Lin et al.
-State Electronics, VOL.32, p956, 1989 'are examples.

These techniques are composed of the following steps. First, after forming a polycrystalline silicon film which is a gate electrode forming material, this is patterned to form a gate electrode. Next, an n-type impurity is selectively ion-implanted into a region where an nMOSFET is formed to form an n-type gate electrode and n-type source / drain. Then p
P-type impurities are selectively ion-implanted into the region where the MOSFET is formed to form a p-type gate electrode and p-type source / drain. That is, each MOSFET has a source
Ion implantation for forming the drain and impurity ion implantation for reducing the resistance of the gate electrode are simultaneously performed. For this reason, in the source / drain, the surface impurity concentration becomes sufficiently high, and a shallow junction is formed, but on the other hand, the carrier concentration of the gate electrode becomes low and the sheet resistance becomes high. Therefore, in this technique, after the impurities are ion-implanted, the wafer is heat-treated at a high temperature of 900 ° C. or higher to silicify the surfaces of the gate electrode and the source / drain to reduce the sheet resistance.

[0006]

[Problems to be Solved by the Invention]
The conventional example introduced by jian Davari and Wen Lin has a problem that the interface between the gate oxide film and the gate electrode (polycrystalline silicon film) is depleted during channel formation. This is because the activation rate of impurities (dopants) in the polycrystalline silicon film (gate electrode) is extremely low as compared with the activation rate in the single crystal silicon film (semiconductor substrate). is there.

[0007] That is, JYW Seto is the electrical pro
pertis of polycrystaline siliconfilms, J.Appl.Phy
s., vol.46, p52473 to 5254, 1975 ', when impurities are ion-implanted into a polycrystalline silicon film and a single crystalline silicon film at the same concentration, carriers in the polycrystalline silicon film are It is reported that the concentration becomes about 1/10 of the carrier concentration in the single crystal silicon film. It is considered that this is because the impurities ion-implanted into the polycrystalline silicon film segregate at the grain boundaries of the polycrystalline silicon film.

Therefore, for example, when impurities are ion-implanted into the gate electrode and the source / drain at an impurity concentration of 1 × 10 ¹⁵ / cm ² , the source / drain is about 1 × 10 ²⁰ / cm ^3. The carrier concentration of the gate electrode is 1 × 10 ¹⁹ pieces / cm 2.
It is about ³ . Here, for example, when the thickness of the gate oxide film is 9 nm, the carrier concentration necessary for the gate electrode is 1 × 10 ²⁰ / cm ³ or more. If the carrier concentration of the gate electrode is less than this, a depletion layer is generated at the interface between the gate oxide film and the gate electrode (polycrystalline silicon film) when the transistor is operating, and the transconductance of the transistor is extremely lowered. . Therefore, M
There is a problem that the operation of the OSFET becomes slow.

Therefore, in order to improve the activation rate of the impurities implanted into the gate electrode (polycrystalline silicon film), a heat treatment is performed to increase the ion implantation amount of the impurities or to activate the impurities. It is also considered to raise the temperature. However, when the ion implantation amount of the impurities is increased or the temperature of the heat treatment is increased,
Since the source-drain junction becomes deeper and the punch-through breakdown voltage decreases, there is a problem that it cannot be applied to a fine MOSFET.

In addition to the impurity ion implantation process for forming the source / drain, a method of selectively implanting impurities into the gate electrode to increase the carrier concentration of the gate electrode can be considered. There was a problem that it became complicated and productivity was lowered. The present invention has an object to solve such various problems, prevents the interface between the gate oxide film and the gate electrode from being depleted without increasing the number of steps, and Surface-channel type n with large transconductance
It is an object of the present invention to provide a method for manufacturing a semiconductor device including a MOSFET and a pMOSFET on the same substrate.

[0011]

In order to achieve this object, the present invention has an n-type transistor having a metal / oxide / semiconductor structure and a metal / oxide / semiconductor structure on the same substrate. In a method of manufacturing a semiconductor device for forming a p-type transistor, Si ₂ H ₆ is used on the entire surface of a gate oxide film formed on an element formation region of a semiconductor substrate.
A first step of forming a silicon film in an atmosphere of 0 ° C. or lower,
A second step of patterning the silicon film to form a gate electrode, and after forming the gate electrode, introducing an n-type impurity into a region for forming an n-type element and introducing a p-type impurity into a region for forming a p-type element. And a fourth step of activating the impurities, the present invention provides a method of manufacturing a semiconductor device.

Further, the present invention provides a method for manufacturing a semiconductor device, characterized in that after the silicon film is formed, the silicon film is heat-treated at a temperature of 600 ° C. or higher.
In addition, in a method of manufacturing a semiconductor device in which an n-type transistor having a metal / oxide / semiconductor structure and a p-type transistor having a metal / oxide / semiconductor structure are formed on the same substrate, an element of a semiconductor substrate is provided. A first step of forming a polycrystalline silicon film on the entire surface of the gate oxide film formed on the formation region, a second step of introducing Si ions or Ge ions into the polycrystalline silicon film, and the Si ions or Ge ions The third step of forming a gate electrode by patterning the polycrystalline silicon film into which n has been introduced, and after forming the gate electrode, an n-type impurity is added to a region where an n-type element is formed and an n-type impurity is added to a region where a p-type element is formed. It is intended to provide a method for manufacturing a semiconductor device, which includes a fourth step of introducing a p-type impurity and a fifth step of activating the impurity.

Furthermore, the present invention provides a method for manufacturing a semiconductor device, characterized in that the polycrystalline silicon film having Si ions or Ge ions introduced therein is heat-treated at a temperature of 600 ° C. or higher.

[0014]

According to the first aspect of the invention, Si is formed on the entire surface of the gate oxide film formed on the element formation region of the semiconductor substrate.
_A silicon film is formed using ₂ H ₆ in an atmosphere of 580 ° C. or lower, the silicon film is patterned, a gate electrode is formed, and then an n-type impurity is formed in a region where an n-type element is formed and a p-type element is formed. The silicon film can be formed in an amorphous state by introducing a p-type impurity into the region to be activated and then activating the impurity. Therefore, the activation rate of impurities in the silicon film can be about 10 times the activation rate in the polycrystalline silicon film.

That is, the silicon film formed under the above conditions is
Since it becomes an amorphous silicon film, its crystals can be coarsened and grain boundaries can be reduced. Therefore, since the impurities segregated at the grain boundaries are small, the carrier concentration of the gate electrode can be increased. Therefore, depletion of the interface between the gate oxide film and the gate electrode can be prevented during the operation of the transistor. Therefore, it is possible to suppress a decrease in the transconductance of the MOSFET.

When the film forming temperature of the silicon film exceeds 580 ° C., nuclei are generated in the silicon film, resulting in 600 ° C.
After the above heat treatment, the crystals in the silicon film become finer and it becomes difficult to increase the carrier concentration of the gate electrode. Further, when SiH ₄ is used without using the Si ₂ H ₆ and the film forming temperature is 580 ° C. or less, the film forming rate is lowered and the film cannot be formed efficiently. It reduces productivity.

Therefore, it is preferable that the silicon film is formed of Si ₂ H ₆ in an atmosphere of 580 ° C. or lower. Further, since the carrier concentrations of the gate electrode and the source / drain can be made approximately the same, a sufficiently low sheet resistance can be obtained without silicifying the surface of the gate electrode and the surface of the source / drain as in the conventional case. Therefore, the process can be simplified.

According to the second aspect of the invention, after the silicon film is formed, the silicon film is coated with 600
By performing the heat treatment at a temperature of ℃ or more, the crystal grain size of the silicon film can be made coarser and the grain boundaries can be reduced more reliably. Further, according to the invention of claim 3,
An area where an n-type element is formed after Si ions or Ge ions are introduced into a polycrystalline silicon film formed on the entire surface of a gate oxide film on an element formation region of a semiconductor substrate and patterned to form a gate electrode. Of the impurities in the polycrystalline silicon film into which the Si ions or the Ge ions have been introduced by activating the impurities by introducing the n-type impurities into the region and the p-type impurities into the region forming the p-type element. The activation rate can be about 10 times the activation rate in the polycrystalline silicon film.

That is, by introducing Si ions or Ge ions into the polycrystalline silicon film, the crystals of the polycrystalline silicon film can be coarsened and grain boundaries can be eliminated. Therefore, since impurities are not segregated at the grain boundaries, the carrier concentration of the gate electrode can be increased. Therefore, it is possible to prevent a depletion layer from being formed at the interface between the gate oxide film and the gate electrode during the operation of the transistor. Therefore, MOSFET
It is possible to suppress the decrease of the transconductance of.

Further, since the carrier concentrations of the gate electrode and the source / drain can be made approximately the same, a sufficiently low sheet resistance can be obtained without silicifying the surface of the gate electrode and the surface of the source / drain as in the conventional case. Can be obtained. Further, according to the invention described in claim 4, the polycrystalline silicon film into which the Si ions or the Ge ions are introduced is heat-treated at a temperature of 600 ° C. or higher, so that the crystal grains of the silicon film can be more reliably formed. The diameter can be coarsened and grain boundaries can be eliminated.

[0021]

(Embodiment 1) Next, Embodiment 1 according to the present invention will be described with reference to the drawings. 1 to 6 are
FIG. 5 is a partial cross-sectional view showing a part of the manufacturing process of the semiconductor device according to the first embodiment of the invention.

In the step shown in FIG. 1, in a p-type semiconductor substrate 1 having a plane orientation (100), a p-well 31 is formed in a region where an n-type element is formed and an n-well 3 is formed in a region where a p-type element is formed.
Form 0. Next, the field oxide film 2 is formed in the element isolation region of the semiconductor substrate 1 by a known method, and then the inversion prevention layer 4 is formed below the field oxide film 2 formed in the region where the p-type element is formed. To do. Next, the wafer is thermally oxidized to form a gate oxide film 5 having a film thickness of about 7 nm on the element formation region of the semiconductor substrate 1. Then, using Si ₂ H ₆ gas at a film forming temperature of 480 ° C.,
A silicon film 3 having a thickness of about 150 nm is formed on the entire surface of the wafer. The silicon film 3 becomes an amorphous silicon film by being formed under the above conditions.

Next, in the process shown in FIG. 2, the process shown in FIG.
The silicon film 3 obtained in the above step is patterned to obtain the n-type
On the area where elements are formed and on the area where p-type elements are formed
To form a gate electrode 6 having a gate length of 0.35 μm
It Then, a registration is performed on the n-type device region of the wafer.
The strike film 9 is applied, and the p-type element is formed using this as a mask.
B as a p-type impurity in the formed region.⁺(Boron), note
Quantity = 1 x 10¹³Pieces / cm ², Injection energy = 10K
Ion implantation at eV, p^-Diffusion layer 7 and p^-Diffusion layer 8,
The p-type gate electrode 16 is formed.

Next, in the step shown in FIG. 3, after removing the resist film 9 formed in the step shown in FIG. 2, the resist film 9 is applied on the region of the wafer where the p-type element is to be formed,
Using this as a mask, P ⁺ (phosphorus) is implanted as an n-type impurity into a region where an n-type element is to be formed, and the implantation amount is 4 × 10 ¹³ / c.
m ² , ion implantation energy = 30 KeV, and
^- forming a diffusion layer 11 ^- diffusion layer 10 and n.

Next, in the step shown in FIG. 4, the resist film 9 formed in the step shown in FIG. 3 is removed, sidewalls are formed on each gate electrode, and then on the region of the wafer where the n-type element is to be formed. A resist film 9 is applied to the surface of the substrate, and using this as a mask, B is used as a p-type impurity in a region where a p-type element is formed.
Injection amount of F ₂ ⁺ (boron fluoride) = 2 × 10 ¹⁵ pieces / c
m ² and ion energy = 40 KeV, ion implantation is performed, and p
⁺ Diffusion layer 12 and p ⁺ diffusion layer 14 and P-type gate electrode 1
6 is formed. At this time, since the gate electrode 6 is formed of the amorphous silicon film 3, the amount of B segregated at the grain boundaries is small and diffuses into the silicon film 3. Therefore, it is possible to obtain the p-type gate electrode 16 in which the carrier concentration is extremely increased as compared with the case where the gate electrode made of the conventional polycrystalline silicon film is formed.

Next, in the step shown in FIG. 5, after removing the resist film 9 formed in the step shown in FIG. 4, the resist film 9 is applied on the region of the wafer where the p-type element is to be formed,
Using this as a mask, As ⁺ (arsenic) as an n-type impurity is ion-implanted into the region where an n-type element is to be formed, with an implantation amount of 3 × 10 ¹⁵ / cm ² and an implantation energy of 40 KeV, and a p ⁺ diffusion layer is formed. 12, p ⁺ diffusion layer 14 and n-type gate electrode 26 are formed. At this time, since the gate electrode 6 is formed of the amorphous silicon film 3, the P is
The amount segregated at the grain boundaries is small and diffuses into the silicon film 3. Therefore, the n-type gate electrode 2 having an increased carrier concentration
6 can be obtained.

Next, the ion-implanted wafer is loaded into a diffusion furnace, and the wafer is heat-treated at 850 ° C. for 30 minutes. In this way, the impurities are activated and p
^- source 13 consisting of a diffusion layer 7 and the p ⁺ diffusion layer 12, p
^- a drain 15 composed of the diffusion layer 8 and the p ⁺ diffusion layer 14,
Source 1 composed of n ⁻ diffusion layer 10 and n ⁺ diffusion layer 17
8, the drain 21 including the n ⁻ diffusion layer 11 and the n ⁺ diffusion layer 19 was formed.

Next, in the step shown in FIG. 6, on the gate electrodes 16 and 26, on the sources 13 and 18, and on the drain 15.
After removing the oxide film formed on the electrodes 21 and 21, a titanium film having a film thickness of about 20 nm is formed on the entire surface. Then, the wafer on which the titanium film is formed is loaded into a rapid heating device, and the wafer is subjected to heat treatment at 650 ° C. for 30 seconds, so that the gate electrodes 16 and 26, the sources 13 and 18 are formed.
The titanium film formed on the upper and drains 15 and 21 is silicidized, and the titanium silicide film 22 is formed on this portion. Next, in the silicidation, after removing the unreacted titanium film with ammonia hydrogen peroxide solution,
The wafer is loaded into the rapid heating device again, and the wafer is heat-treated at 800 ° C. for 30 seconds. Then, an interlayer insulating film 23 is formed on the entire surface of the wafer.

Thereafter, desired steps such as opening of contact holes are performed to complete the semiconductor device having the complementary MOSFET. In this example, in the process shown in FIG.
_Although the silicon film 3 was formed at a film forming temperature of 480 ° C. using ₂ H ₆ gas, the present invention is not limited to this.
It may be formed at a film forming temperature of 580 ° C. or lower using Si ₂ H ₆ gas.

Further, in the present embodiment, B ⁺ and BF ₂ ⁺ are ion-implanted as p-type impurities into the region where the p-type element is formed, but the present invention is not limited to this, and other types of p-type impurities are ion-implanted. May be injected. The ion implantation conditions (implantation amount, implantation energy, etc.) may be determined as desired. Also,
In this embodiment, P ⁺ and As ⁺ are ion-implanted as n-type impurities into the region where the n-type element is formed. However, the present invention is not limited to this, and other types of n-type impurities may be ion-implanted. Ion implantation conditions (implantation amount, implantation energy, etc.) are
It may be determined as desired.

Furthermore, in the present embodiment, the wafer after the ion implantation in the step shown in FIG. 5 was subjected to the heat treatment at 850 ° C. for 30 minutes, but the present invention is not limited to this, and the heat treatment is not limited to this.
Using a rapid heating device, at a temperature of about 900 to 1100 ° C,
The heat treatment method may be determined as desired, such as performing heat treatment for 10 to 60 seconds. The size of the element described in this embodiment is an example, and may be changed and formed as desired.

Next, as a comparison, in the process shown in FIG. 1, instead of forming a silicon film, SiH ₄ gas was used, and 6
After forming a polycrystalline silicon film having a film thickness of about 150 nm at a film forming temperature of 20 ° C., the subsequent steps shown in FIG.
A semiconductor device having a complementary MOSFET was completed (comparative example). Next, the sheet resistance of the complementary MOSFET (invention) obtained in Example 1 and the sheet resistance of the comparative example were measured for the n-type element formation region and the p-type element formation region. n
FIG. 9 shows the measurement results of the sheet resistance in the mold element formation region.
10 shows the measurement result of the sheet resistance in the pn-type element formation region.

From FIGS. 9 and 10, it was confirmed that the sheet resistance of the invention product shows an extremely low value as compared with the sheet resistance of the comparative example. From this, it was proved that the product of the present invention can obtain a high carrier concentration by implanting the same amount of impurities into the gate electrode as in the gate and drain. Second Embodiment Next, a second embodiment according to the present invention will be described with reference to the drawings.

In the process shown in FIG. 1 of the first embodiment,
After forming the silicon film 3, the wafer on which the silicon film 3 is formed is heat-treated in an inert gas atmosphere at 600 ° C. for 2 hours. Next, the steps after FIG. 2 performed in the first embodiment are performed to complete the semiconductor device having the complementary MOSFET.

In this embodiment, the wafer on which the silicon film 3 is formed is heat-treated in an inert gas atmosphere at 600 ° C. for 2 hours. However, the temperature is not limited to this and the heat-treatment temperature is 600. It may be at least ° C. Also, the heat treatment time may be determined as desired. (Third Embodiment) Next, a third embodiment according to the present invention will be described with reference to the drawings.

7 and 8 are partial cross-sectional views showing a part of the manufacturing process of the semiconductor device according to the third embodiment of the present invention.
In the step shown in FIG. 7, in the p-type semiconductor substrate 1 having the plane orientation (100), the p-well 31 is formed in the region where the n-type element is formed.
An n well 30 is formed in a region where a p-type element will be formed. Next, the field oxide film 2 is formed in the element isolation region of the semiconductor substrate 1 by a known method, and then the inversion prevention layer 4 is formed below the field oxide film 2 formed in the region where the p-type element is formed. To do. Next, the wafer is thermally oxidized to form a film having a thickness of 7 on the element formation region of the semiconductor substrate 1.
A gate oxide film 5 of about nm is formed. Then SiH
A polycrystalline silicon film 33 having a thickness of about 150 nm is formed on the entire surface of the gate oxide film 5 at a film forming temperature of 620 ° C. using ₄ gases.

Next, in the step shown in FIG. 8, monovalent silicon ions (Si ⁺ ) are implanted into the polycrystalline silicon film 33 obtained in the step shown in FIG. 7 at an implantation amount = 5 × 10 ¹⁵ / cm ^2. Ion implantation is performed with implantation energy = 40 KeV to form a polycrystalline silicon film 34 in which Si is implanted. By doing so, the crystals of the polycrystalline silicon film 33 can be coarsened and the grain boundaries can be reduced.
Therefore, it is possible to prevent the ion-implanted impurities from being segregated at the grain boundaries during the impurity ion implantation performed later. Therefore, the carrier concentration in the gate electrode formed later can be increased.

Then, the subsequent steps shown in FIG. 2 of the first embodiment are performed to complete the semiconductor device having the complementary MOSFET. Although Si ⁺ is ion-implanted in the polycrystalline silicon film 33 in the step shown in FIG. 8 in the present embodiment, the present invention is not limited to this, and Ge ⁺ may be ion-implanted. Also, Si
⁺ The Ge ⁺ ion implantation conditions may be determined as desired. (Fourth Embodiment) Next, a fourth embodiment according to the present invention will be described with reference to the drawings.

In the process shown in FIG. 2 of the third embodiment,
The wafer on which the polycrystalline silicon film 34 in which Si is implanted is formed is subjected to heat treatment in an inert gas atmosphere at 600 ° C. for 2 hours. Next, the steps after FIG. 2 performed in the first embodiment are performed to complete the semiconductor device having the complementary MOSFET.

In this embodiment, the wafer on which the Si-implanted polycrystalline silicon film 34 is formed is
Heat treatment was performed for 2 hours in an inert gas atmosphere at ℃,
Not limited to this, the temperature of the heat treatment may be 600 ° C. or higher. Also, the heat treatment time may be determined as desired. Next, a film thickness of 7 is formed on the semiconductor substrate separated between the elements.
A gate oxide film having a thickness of about nm was formed, and then a silicon film was formed on the gate oxide film under the film forming conditions shown in Table 1. Then, under the conditions shown in Table 1, impurities are ion-implanted into the silicon film, and then heat treatment is performed at 850 ° C. for 30 minutes to activate the impurities, and four types of MOSFE are activated.
T (Sample 1 to Sample 4) was created.

Next, quasi-static capacity measurement was performed on the samples 1 to 4. In this measurement, the capacitance (Cinv) when the semiconductor substrate is strongly inverted is divided by the capacitance (Cox) of the semiconductor substrate in the storage state (Cinv / Co).
x) was determined. The results are shown in Table 1. In addition, the Ci
The nv / Cox value has a transconductance and a layer during operation of the MOSFET (during channel formation). Generally, if Cinv / Cox is 0.98 or more, the gate oxide film is formed during operation of the MOSFET. It is known that the interface between the gate electrode and the gate electrode is less likely to be depleted. That is, it is known that a sufficiently high transconductance can be secured. On the other hand, if the Cinv / Cox is 0.
It is known that when it is 95 or less, the transconductance of the MOSFET is lowered and it is not suitable for actual use.

[0042]

[Table 1]

From Table 1, samples 1 and 2 (that is, samples obtained by the method for forming a silicon film according to the present invention) are C
The inv / Cox value was 0.98 or more, and it was confirmed that a sufficiently high transconductance could be secured.
This is because the silicon film was formed at a film forming temperature of 580 ° C. or lower using Si ₂ H ₆ gas, so that the silicon film has an amorphous structure, the crystal grains after crystallization become coarse, and the grain boundary area becomes large. This is because the impurity ions that were ion-implanted were not segregated at the grain boundaries because they were small, and the carrier concentration in the gate electrode increased.

On the other hand, in the comparative example, Cinv / Cox is used.
It was confirmed that the value was 0.95 or less, and the transconductance of the MOSFET was lowered, which was not suitable for actual use. This is because the SiH ₄ gas was used and the silicon film was formed at a film formation temperature of 620 ° C., so that the silicon film had a polycrystalline structure and the ion-implanted impurities were segregated at the formed grain boundaries.

Sample 4 has a Cinv / Cox value of 0.99 and a sufficiently high transconductance can be secured, but since the ion implantation amount is large, MOSFE
T causes punch-through, which makes it impossible to use in practice. Next, the maximum value of transconductance (mS / mm) of the complementary MOSFETs obtained in Examples 1 to 4 and the comparative example and the maximum value of transconductance (mS / mm) of the comparative example obtained in Example 1 were obtained. mm) was measured. Note that V _DS = 3V.

The results are shown in Table 2.

[0047]

[Table 2]

From Table 2 the complementary MOSFE according to the invention
T (Examples 1 to 4) was able to obtain a very high transconductance as compared with the comparative example.

[0049]

As described above, according to the first aspect of the present invention, Si ₂ H ₆ is used on the entire surface of the gate oxide film formed on the element formation region of the semiconductor substrate in an atmosphere of 580 ° C. or lower. After forming a silicon film by, patterning the silicon film and forming a gate electrode, after introducing an n-type impurity into a region for forming an n-type element and a p-type impurity in a region for forming a p-type element By activating the impurities, the silicon film can be formed as a polycrystalline silicon film having coarse crystal grains. Therefore, the activation rate of impurities in the silicon film can be about 10 times the activation rate in the polycrystalline silicon film. Therefore, as a result of increasing the carrier concentration of the gate electrode,
It is possible to prevent a depletion layer from being formed at the interface between the gate oxide film and the gate electrode during the operation of the transistor.
Therefore, it is possible to suppress a decrease in the transconductance of the MOSFET.

According to the second aspect of the invention, after the silicon film is formed, the silicon film is subjected to heat treatment at a temperature of 600 ° C. or higher, so that in addition to the above effect, the silicon film can be more reliably processed. The crystal grain size of can be coarsened. Further, according to the third aspect of the invention, Si ions or Ge ions are introduced into the polycrystalline silicon film formed on the entire surface of the gate oxide film on the element formation region of the semiconductor substrate, and this is patterned to form a gate. After forming the electrodes,
After introducing an n-type impurity in a region for forming an n-type element and a p-type impurity in a region for forming a p-type element, and then activating the impurity, a polycrystalline material into which the Si ion or Ge ion is introduced The activation rate of impurities in the silicon film can be about 10 times the activation rate in the polycrystalline silicon film. Therefore, as a result of being able to increase the carrier concentration of the gate electrode, it is possible to prevent depletion at the interface between the gate oxide film and the gate electrode during the operation of the transistor. Therefore, it is possible to suppress a decrease in the transconductance of the MOSFET.

According to the invention described in claim 4,
By performing heat treatment on the polycrystalline silicon film into which the Si ions or Ge ions are introduced at a temperature of 600 ° C. or higher, in addition to the above effect, the crystal grain size of the silicon film can be more reliably and efficiently coarsened, The world can be lost.

[Brief description of drawings]

FIG. 1 is a partial cross-sectional view showing a part of a manufacturing process of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a partial cross-sectional view showing a part of the manufacturing process of the semiconductor device according to the first embodiment of the invention.

FIG. 3 is a partial cross-sectional view showing a part of the manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 4 is a partial cross-sectional view showing a part of the manufacturing process of the semiconductor device according to the first embodiment of the invention.

FIG. 5 is a partial sectional view showing a part of the manufacturing process of the semiconductor device according to the first embodiment of the invention.

FIG. 6 is a partial cross-sectional view showing a part of the manufacturing process of the semiconductor device according to the first embodiment of the invention.

FIG. 7 is a partial cross-sectional view showing a part of the manufacturing process of the semiconductor device according to the third embodiment of the present invention.

FIG. 8 is a partial cross-sectional view showing a part of the manufacturing process of the semiconductor device according to the third embodiment of the present invention.

FIG. 9 is a diagram showing sheet resistance values in an n-type element formation region according to Example 1 of the present invention and an n-type element formation region of a comparative example.

FIG. 10 is a diagram showing sheet resistance values in a p-type element formation region according to Example 1 of the present invention and a p-type element formation region of a comparative example.

[Explanation of symbols]

 1 semiconductor substrate 2 field oxide film 3 silicon film 5 gate oxide film 13 source 15 drain 18 source 21 drain

Claims (4)

[Claims] 1. A method for manufacturing a semiconductor device, which comprises forming an n-type transistor having a metal / oxide / semiconductor structure and a p-type transistor having a metal / oxide / semiconductor structure on the same substrate. 1. A first step of forming a silicon film on the entire surface of the gate oxide film formed on the element formation region using Si ₂ H ₆ in an atmosphere of 580 ° C. or less, and patterning the silicon film to form a gate electrode A second step, a third step of introducing an n-type impurity into a region for forming an n-type element and a p-type impurity in a region for forming a p-type element after forming the gate electrode, and a third step of activating the impurity 4. A method of manufacturing a semiconductor device, comprising: 4 steps. 2. The method of manufacturing a semiconductor device according to claim 1, wherein after the silicon film is formed, the silicon film is heat-treated at a temperature of 600 ° C. or higher. 3. A method for manufacturing a semiconductor device, which comprises forming an n-type transistor having a metal / oxide / semiconductor structure and a p-type transistor having a metal / oxide / semiconductor structure on the same substrate. 1. A first step of forming a polycrystalline silicon film on the entire surface of the gate oxide film formed on the element forming region, a second step of introducing Si ions or Ge ions into the polycrystalline silicon film, and a Si ion or A third step of forming a gate electrode by patterning the polycrystalline silicon film into which Ge ions are introduced, and after forming the gate electrode,
A fourth step of introducing an n-type impurity into a region for forming an n-type element and a p-type impurity into a region for forming a p-type element, and a fifth step of activating the impurity are characterized by being included. Manufacturing method of semiconductor device. 4. The method of manufacturing a semiconductor device according to claim 3, wherein the polycrystalline silicon film having Si ions or Ge ions introduced therein is heat-treated at a temperature of 600 ° C. or higher.