JPH08330441A - Manufacture of mos transistor - Google Patents

Abstract

PURPOSE: To prevent the enhanced diffusion of B in the p<+> type gate electrode of a PMOS and provide a shallow junction. CONSTITUTION: The F incorporated into the active area in an Si substrate is useful for attainment of a shallow junction depth xj of a B diffusion layer, but the F in a p<+> type gate electrode is harmful against the diffusion promotion of B which is an impurity. Therefore, F<+> ion implantation is performed by using the resist mask 8, which used for patterning gate electrodes 7n and 7p, without modification. At that time, F<+> is introduced not to the gate electrode 7p but to the active area. Then, the resist mask 8 is removed, and ion implantation of not BF2 <+> but B<+> is performed in the PMOS forming area. A shallow LDD area 10 is formed in the active area by the present F<+> , and in the gate electrode 7p, fluctuation of B concentration in the gate electrode 7p is suppressed. Thus, fluctuation of the threshold voltage Vth and the subthreshold swing increase of the PMOS are suppressed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a MOS transistor, and more particularly to a p-type MOS transistor (PMO).
While suppressing the diffusion of boron (B) from the p-type gate electrode of S) or the penetration of B of the gate oxide film,
The present invention also relates to a method of simultaneously achieving a shallow junction in the drain region.

[0002]

2. Description of the Related Art A complementary MOS transistor (CMOS) in which an n-type MOS transistor (NMOS) and a p-type MOS transistor (PMOS) coexist on the same substrate.
Has an advantage that power consumption is low because current flows only when both transistors are turned on, and high-speed operation is possible because miniaturization and high integration are easy. Widely used as an LSI component device. In recent years, M with a gate length of 0.1 μm or less
Since the room temperature operation of the OS transistor has been confirmed, it is surely expected that the high integration and miniaturization of the CMOS circuit will continue to progress in the future.

By the way, conventionally, as the constituent material of the gate electrode of the PMOS, n is the same as that of the gate electrode of the NMOS.
Materials such as a ⁺ type polysilicon film, or a polycide film or a polymetal film in which a refractory metal silicide film or a refractory metal film is stacked on the ⁺ type polysilicon film have been used. This is n ⁺
This is because the type polysilicon film can withstand a high temperature process well, and since the channel profile is a buried type, the high bulk mobility can be utilized to accelerate the operation. However, in the buried channel type MOS transistor, there is a problem that punch-through easily occurs because the tips of the depletion layers protruding from the source / drain regions approach each other in the deep portion of the substrate due to the influence of the gate electric field.
Therefore, in the generation in which the design rule is reduced to deep submicron or less, it is difficult to suppress the short channel effect in the buried channel type, and therefore the adoption of the surface channel type is desired. If the gate electrode of the PMOS is formed by using the p ⁺ type polysilicon film, a surface channel type profile can be realized.

There are other reasons why the p ⁺ type polysilicon film is desired as the gate electrode material of the PMOS. NMOS, P
In the conventional CMOS using the n ⁺ -type polysilicon film for any of the MOS gate electrodes, there is a work function difference between the NMOS and the PMOS, and this difference causes a threshold voltage V
_th is asymmetric. Therefore, the threshold voltage V _th of both transistors is set to be almost equal (usually 1 V or less) by shallowly ion-implanting boron into the channel region of the PMOS. However, if the impurity concentration on the substrate surface is increased by ion implantation for adjusting the threshold voltage V _th, the carrier mobility near the substrate surface is lowered, which is disadvantageous for speeding up the operation. It is essential to lower it. Therefore, if the p ⁺ -type polysilicon film having a large work function is used as the gate electrode of the PMOS, the threshold voltage V _th can be made symmetrical between the NMOS and the PMOS without increasing the channel impurity concentration. This means that
When the basic gate is formed as the MOS inverter, the input / output characteristics of the transistor are made symmetrical, which leads to improvement of the symmetry of the signal transfer characteristics.

By the way, in the manufacturing process of a MOS transistor, it is necessary to minimize the number of processes, so that the introduction of impurities into the gate electrode and the introduction of impurities into the source / drain regions may be performed in a common process. Regarding this process, taking the manufacturing process of LDD type CMOS as an example,
Description will be made with reference to FIGS. 11 to 14.

First, a p-type Si substrate (p-Sub) 21
Field oxides 22, n according to the procedure known above.
Type well (n-Well) 23 and gate oxide film 24
Are sequentially formed. Subsequently, a tungsten (W) -polycide film is deposited on the entire surface of the substrate, and this film is anisotropically etched through a resist mask (not shown) to form a gate electrode 27n in each of the NMOS formation region and the PMOS formation region. , 27p are formed. here,
The gate electrodes 27n and 27p are composed of non-doped (non-impurity-containing) polysilicon films 25n and 25p and a tungsten silicide film (WS) in order from the lower layer side.
ix) films 26n and 26p are laminated. However, the subscript n is the constituent element of the NMOS and the subscript p is the PMOS
It is a component of. Further, after removing the resist mask used for etching, the entire NMOS formation region is covered with a resist mask 28, and low concentration ion implantation of BF ₂ ⁺ is performed in the PMOS formation region. By this low-concentration ion implantation, the polysilicon film 25p is made p ⁻ -type and the p ⁻ -type LDD region 29 is formed in the Si substrate 21. FIG. 11 shows a state in which the steps up to this point have been completed.

By the way, the reason why BF ₂ ⁺ is used as the ion species in the above-mentioned low-concentration ion implantation for the PMOS formation region is that the range is controlled to be smaller than that of B ⁺ because of the dissociation characteristics and large mass of the ion species. Is advantageous in achieving a shallow junction or preventing channeling, and F has the effect of reducing the trap density inside the gate oxide film 24.

After the low-concentration ion implantation into the PMOS formation region is completed as described above, the resist mask 28 is removed and the resist mask 30 covering the PMOS formation region is removed.
Are newly formed, and low-concentration As ⁺ ion implantation is performed on the NMOS formation region. By this low concentration ion implantation,
The polysilicon film 25n is made n ⁻ -type, and the n ⁻ -type LDD region 31 is formed in the Si substrate 21. Figure 12
It shows a state in which the steps up to this point have been completed.

Next, the resist mask 30 is removed and an insulating film such as a SiOx film is deposited on the entire surface of the substrate.
This is anisotropically etched back to form gate electrodes 27n, 2
The sidewall 32 is formed on the sidewall surface of 7p. Further, the NMOS formation region is covered with a resist mask 33, and high-concentration ion implantation of BF ₂ ⁺ is performed. By this high-concentration ion implantation, the polysilicon film 25p is made p ⁺ -type, and the p ⁺ -type source / drain region 34 is formed in the Si substrate 21.
To form. FIG. 13 shows a state in which the steps up to this point have been completed.

Further, the resist mask 33 is removed, P
Similarly, the formation of a resist mask 35 covering the MOS formation region and the high-concentration As ⁺ ion implantation into the NMOS formation region are sequentially performed. By this high-concentration ion implantation, the polysilicon film 25n is made n ⁺ -type, and the n ⁺ -type source / drain regions 36 are formed in the Si substrate 21. 14
Indicates the state in which the steps up to this point have been completed.

According to the process described above, the polysilicon films 25n, 2 forming the gate electrodes 27n, 27p are formed.
Since impurity introduction into 5p and impurity introduction for forming LDD type source / drain regions can be carried out simultaneously, a large number of steps are required due to a reduction in the number of steps as compared with, for example, a process of ion-implanting impurities into a polysilicon film before patterning. Economic effect can be obtained.

[0012]

Incidentally, in the PMOS, various adverse effects due to diffusion of B from the p ⁺ type gate electrode have been pointed out as the design rule becomes finer. That is, in the manufacturing process of a MOS transistor, source / drain activation, SALICE (self-aligned silicidation) process, reflow of interlayer insulating film, etc.
Heat treatment is performed at various stages, but due to this heat load, p
^If B in the ⁺ type gate electrode diffuses and is taken into the gate oxide film, or penetrates the gate oxide film and diffuses into the Si substrate, the threshold voltage V _th of the PMOS increases and the subthreshold swing of This causes an increase or a decrease in reliability of the gate oxide film. Moreover, F
Is known to promote the diffusion of B and promote such inconvenience. Therefore, although BF ₂ ⁺ ion implantation in which F is introduced at the same time as B is advantageous in forming a shallow junction in the substrate, it must be said that it is disadvantageous from the viewpoint of preventing B diffusion from the gate electrode. I don't get it.

Ion implantation using B ⁺ instead of BF ₂ ⁺ is likely to be effective in preventing B diffusion because F is not taken into the gate electrode at the same time as B.
In fact, from the p ⁺ type gate electrode formed by the ion implantation of B ⁺ , even if the diffusion of B occurs, it does not penetrate through the gate oxide film, and is stabilized in the gate oxide film.

However, in recent years highly miniaturized MOS
In a transistor, a gate composed of a single layer of polysilicon film
Electrodes are rarely used and often gate delay
In order to suppress the elongation, the W-polycide film as described above is used.
The processed gate electrode is adopted. However, this
The WSix film forming the upper layer side of the W-polycide film does not pass through.
Usually, a considerable amount of F derived from the film-forming source gas is contained.
Easily supplies F to the lower polysilicon film.
U Especially WF₆ SiH_Four Return with (Monosilane: MS)
The original MS reduction low pressure CVD method was used to form the WSix film.
Is 10²⁰/ Cm³ F is left on the order,
There is a great risk of supplying F. Therefore, polycide
In the gate electrode, even if the introduction of p-type impurities is B⁺ 
Effectively prevents B diffusion even if ion implantation is performed
Is difficult to do. Of course, B ⁺ In ion implantation, S
It is also impossible to form a shallow junction in the i substrate.

A similar problem is that WF is formed on the polysilicon film.
W- laminated with W films grown at low temperature using ₆ as the source gas
It also occurs in the polymetal film. B from the gate electrode
A method considered to be effective in suppressing diffusion is to lower the heat treatment temperature or shorten the heat treatment time. But,
In the former case, the recovery of crystal defects caused by ion implantation or dry etching may be insufficient, which may lead to an increase in leak current. In the latter case, the activation of impurities may be insufficient and the resistance of the diffusion layer or wiring layer may be reduced. May increase.

Further, in order to suppress the penetration of B, N
A method of performing rapid thermal nitridation (RTN) of a gate oxide film in a nitriding atmosphere of H ₃ or N ₂ O has been proposed. However, these methods lead to problems such as deterioration in transistor characteristics due to increase in film thickness of the gate insulating film and decrease in carrier mobility, and decrease in reliability of the gate insulating film due to increase in fixed charges and interface states, and are not necessarily a good measure. Absent.

Further, a method of reducing the crystal grain boundaries by increasing the crystal grain size of the polysilicon film and thereby suppressing the diffusion of B is described in the 1990 IEEE Symposium on VLSI Technology (1990 Symposium o
n VLSI Technology, IEEE) Published in Abstracts p.111-112. In this method, after patterning an amorphous silicon film to form a gate electrode, impurities are introduced into the gate electrode and the source / drain regions at the same time,
The subsequent impurity activation annealing and reflow of the interlayer insulating film are performed at 900 ° C. for 15 minutes to change the amorphous silicon into a polysilicon film having a larger crystal grain size than usual. However, since the progress of crystallization from amorphous silicon to polysilicon largely depends on the annealing conditions after the amorphous silicon film is formed, only this method can achieve crystal grain growth excellent in reliability and reproducibility. It is difficult to achieve.

Thus, p⁺ B expansion from the gate electrode
All of the conventional measures to prevent
The reality is that Therefore, the present invention provides a shallow junction depth.
X _j Achievement of
Method of manufacturing MOS transistor capable of preventing dispersion
The purpose is to provide the law.

[0019]

A method of manufacturing a MOS transistor according to the present invention is proposed to achieve the above-mentioned object, and a step of forming a gate electrode material film including a semiconductor layer on a semiconductor substrate. And a step of forming a gate electrode by etching the gate electrode material film through an etching mask, and an ion that does not impart a specific conductivity type to the semiconductor substrate while leaving the etching mask. Ion implantation is performed on the substrate, and after the etching mask is removed, B ⁺ ions are implanted on the semiconductor substrate and the gate electrode.

Since the etching mask must be removable later, it is preferable to use a resist mask. Considering only the formation of the gate electrode, it is possible to use an offset oxide film formed on the gate electrode in the same pattern as the etching mask. However, in this case, it is practically impossible to remove the etching mask in a later step, so that the ion implantation is performed with the etching mask left. However, if the offset oxide film is left on the gate electrode, it is necessary to set a large range when ion-implanting B ⁺ into the gate electrode, and at the same time, the source / drain regions formed at the same time. The junction depth x _j also increases. Therefore, it is preferable to use a resist mask that can be easily removed by ashing as the etching mask used in the present invention.

Since the etching mask also functions as an ion implantation mask for preventing ions that do not impart a specific conductivity type to the semiconductor substrate in the subsequent process from being introduced into the gate electrode, the range of such ions is limited. It is necessary to have a sufficiently large film thickness. If the resist film thickness is adopted in a normal semiconductor process, there will be no problem.

When a Si substrate is used as the semiconductor substrate, for example, C ⁺ , N ⁺ , F ⁺ can be used as the ions that do not impart a specific conductivity type to the semiconductor substrate. Among them, F ⁺ is particularly preferable because it has a function of suppressing the diffusion of B in the Si substrate even when it is separately ion-implanted from B ⁺ , as confirmed by the conventionally known co-ion implantation. is there.

The gate electrode material film may of course be a single-layer polysilicon film, but may be a high melting point metal silicide film or a composite film including a high melting point metal film. Typical examples of this composite film include a polycide film in which a polysilicon film and a refractory metal silicide film are laminated in this order, and a polymetal film in which a polysilicon film and a refractory metal film are laminated in this order.

As the refractory metal silicide film, W
Six film, TiSix film, MoSix film, TaSix
Conventionally known films such as a film, a PtSix film, and a NiSix film can be used, but a typical film among them is the WSix film. The WSix film is generally formed by converting WF ₆ into SiH ₄ (monosilane: MS) or SiCl ₂ H ₂ (dichlorosilane:
The film is formed by low pressure CVD that reduces with DCS). However, the monthly Semiconductor World December 1992 p. As described in 216 (published by Press Journal), the DCS reduction method produces 10 ¹⁷ / F of residual F in the film.
In the present invention, the DCS reduction method is particularly suitable because it can be reduced to the order of cm ³ . It is not always clear why the DCS reduction method can reduce the residual F by about three orders of magnitude compared to the MS reduction method, but the film formation temperature in the DCS reduction method is higher than that in the MS reduction method (around 360 ° C.). It is also considered that one of the reasons is that the temperature is high (around 650 ° C).

On the other hand, as the refractory metal film, a W film,
Conventionally known films such as Ti film, Mo film, Ta film, Pt film, and Ni film can be used. These films are low pressure CVD
The film can be formed by the method, plasma CVD method, or sputtering method.

[0026]

As described above, F in Si substrate is useful for achieving a shallow junction, but p ⁺ containing B as an impurity is used.
F in the mold gate electrode is harmful because it promotes the diffusion of B. In the present invention, after the patterning of the gate electrode is completed, the etching mask used for the patterning is used as it is as an ion implantation mask for ion implantation of F ⁺ , whereby F can be contained only in the Si substrate. Further, after this, the etching mask is removed and B ⁺ ion implantation is performed, so that source / drain regions having a small junction depth x _j are formed in the Si substrate.
On the other hand, it is possible to suppress the change in B concentration in the gate electrode. Therefore, it is possible to improve the high speed of the PMOS and prevent the fluctuation of the threshold voltage V _th , the increase of the subthreshold swing, and the deterioration of the reliability of the gate oxide film.

When the gate electrode contains a refractory metal silicide film, if this film is formed by the DCS reduction method of WF ₆ , the enhanced diffusion of B due to the residual F can be effectively suppressed. it can. Therefore, the present invention is also extremely effective for manufacturing a PMOS having a polycide gate electrode.

[0028]

EXAMPLES Specific examples of the present invention will be described below. This embodiment applies the present invention to the manufacture of a CMOS having a polycide gate electrode. The process of this embodiment will be described with reference to FIGS.

First, a field oxide film 2 is formed on a p-type Si substrate (p-Sub) 1 by a known LOCOS method to perform element isolation, and then P ⁺ is ion-implanted into a PMOS formation region to form an n-type. Well (n-Well) 3 was formed.
The ion implantation conditions are, for example, an ion acceleration energy of 330 keV and a dose amount of 8 × 10 ¹² / cm ² . Further, although not shown, ion implantation for preventing punch-through (so-called pocket implantation) is performed to form a buried layer in the deep portion of the n-type well 3, and the threshold voltage V _{th is also used.}
Ion implantation for adjustment (so-called channel implantation) was performed to form a channel region in the surface layer portion of the n-type well 3.

Further, pyrogenic oxidation was performed at 850 ° C. to form a gate oxide film 4 having a thickness of about 8 nm on the surface of the active region. FIG. 1 shows a state in which the steps up to this point have been completed. Next, the polysilicon film 5 and W are formed on the entire surface of the substrate.
A W-polycide film 7 in which the Six film 6 was sequentially laminated was formed. Here, the polysilicon film 5 may be formed as a polycrystalline body from the beginning, but here, from the viewpoint of grain size control, it is first formed as an amorphous body and this is formed as WSix.
The film 6 was formed by a method of crystallizing the film 6 by various heat loads in the subsequent steps such as film formation and impurity activation. The initial amorphous body was formed into a film having a thickness of about 70 nm by performing low pressure CVD at 550 ° C. using SiH ₄ as a raw material gas.

One of the WSix films 6 is WF ₆ / SiCl
_{Using 2} H ₂ mixed gas as raw material gas, low pressure CVD at 680 ° C.
By performing the method, a film having a thickness of about 70 nm was formed. In this DCS reduction method, the residual F in the WSix film 6 is reduced to 1 ×
It could be suppressed to the order of 10 ¹⁷ / cm ³ . This was extremely important in suppressing the diffusion of B introduced into the polysilicon film 5p by ion implantation described later.

Further, a resist mask 8 for patterning the gate electrode was formed in both the NMOS formation region and the PMOS formation region. The resist mask 8 is made of, for example, a chemically amplified photoresist material and K.
By using the rF excimer laser stepper,
It was formed to a thickness of about 1 μm and a width of about 0.25 μm.
FIG. 2 shows a state in which the steps up to this point have been completed.

Next, as shown in FIG. 3, the polycide film 7 was dry-etched through the resist mask to form gate electrodes 7n and 7p. Here, the subscript n is a component of NMOS, and the subscript p is PMOS.
Represents a component of each. As an example, the dry etching was performed using a magnetic field microwave plasma etching apparatus and a Cl ₂ / O ₂ mixed gas. Here, O ₂ was added in order to quickly remove the WSix film 6 in the form of WClxOy, and to form a SiOx-based sidewall protection film on the pattern sidewall surface to realize anisotropic processing.

Next, as shown in FIG.
With the mask 8 left, F ⁺ ion implantation was performed on the entire surface of the substrate. The ion implantation conditions at this time are, for example, an ion acceleration energy of 25 keV and a dose of 4 × 10 ¹⁵ /
It was set to cm ² . F ⁺ in the above ion implantation The range of
It is about 55 nm. This value is set according to the skirt position (for example, the position of standard deviation σ) of the distribution of B atoms in the depth direction in the ion implantation of B ⁺ for forming the source / drain regions described later. As a result, F ⁺ was introduced into the active region, but was not introduced into the gate electrodes 7n and 7p shielded by the thick resist mask 8.

Next, as shown in FIG. 5, the resist mask 8 is removed by ashing, the NMOS formation region is newly covered with the resist mask 9, and low concentration B ⁺ ion implantation of B ⁺ is performed in the PMOS formation region. I went. The ion implantation condition at this time is, for example, an ion acceleration energy of 5
The keV and dose amount were set to 2 × 10 ¹³ / cm ² . As a result, the p ⁻ -type LDD region 10 was formed in the active region of the PMOS formation region, and at the same time, the gate electrode 7p was made p-type.

Then, as shown in FIG. 6, this time P
The MOS formation region is covered with a resist mask 11, and NM
As ⁺ low-concentration ion implantation was performed in the OS formation region. The ion implantation conditions at this time are, for example, an ion acceleration energy of 5 keV and a dose amount of 2 × 10 ¹³ / cm ² .
As a result, an n ⁻ -type L is formed in the active region of the NMOS formation region.
While the DD region 12 is formed, the gate electrode 7n is n
Stylized.

Next, the resist mask 11 is removed, and SiOx is formed on the entire surface of the substrate by, for example, the low pressure CVD method.
By depositing a film to a thickness of about 150 nm and then anisotropically etching back this film, the gate electrode 7n,
The LDD sidewall 13 was formed on the sidewall surface of 7p. FIG. 7 shows a state in which the steps up to this point have been completed.

Next, as shown in FIG. 8, the NMOS formation region was covered with a resist mask 14, and high concentration B ⁺ ion implantation was performed on the PMOS formation region. The ion implantation condition at this time is, for example, an ion acceleration energy of 10
The keV and the dose amount were 3 × 10 ¹⁵ / cm ² . As a result, the source / drain region 15 having the LDD structure was formed in the active region of the PMOS formation region, and at the same time, the gate electrode 7p was made p ⁺ -type.

Next, as shown in FIG. 9, a PMOS type
Forming area is covered with resist mask 16 to form NMOS
As in the area⁺ High-concentration ion implantation was performed. At this time
The ion implantation condition is, for example, an ion acceleration energy of 1
0 keV, dose 3 × 10 ^Fifteen/ Cm² And to this
Has an LDD structure in the active region of the NMOS formation region.
The source / drain region 17 is formed at the same time as the gate
The gate electrode 7n is n⁺ Stylized.

Thereafter, rapid thermal annealing (RTA) is performed, for example, at 1050 ° C. for 10 seconds to activate the impurities in the source / drain regions 15 and 17. Further, an interlayer insulating film was deposited, a contact hole was opened, and an upper layer wiring was formed according to a conventional method to complete a CMOS.

Here, FIG. 10 shows a profile of B in the PMOS in the depth direction. For comparison, the case where the gate oxide film of B penetrates is shown by a dashed line. B in the gate electrode originally does not penetrate through the gate oxide film. However, when a large amount of F remains, B _x
It is believed that the formation of O _y (boron oxide) is hindered and reaches the Si substrate. As a result, the surface layer portion of the Si substrate has a high concentration as shown by the chain line, and the channel impurity concentration deviates from the designed value. I will end up. However, in the present invention, since F ⁺ is ion-implanted while avoiding the gate electrode, as shown by the solid line, B is kept at a high concentration in the gate electrode up to the vicinity of the interface with the gate oxide film. It did not penetrate through the oxide film. Therefore, the channel impurity concentration could be maintained at the designed value (here, 10 ¹⁶ / cm ³ ). Further, in the present invention, since F ⁺ is ion-implanted in the active region in advance, accelerated diffusion of B can be suppressed in the PMOS, and the source / drain region 15 having a sufficiently small junction depth x _j is formed. I was able to.

In this embodiment, the ion implantation of F ⁺ is performed by N
The same was done for the MOS formation region, but this had no effect on the diffusion profile of As ⁺ . After that, an interlayer insulating film was deposited, a connection hole was opened, and an upper layer wiring was formed by a conventional method to complete a CMOS. The CMOS manufactured in this example exhibited stable high-speed operation without causing an increase in resistance, a change in threshold voltage Vth, and an increase in interface state.

The specific embodiment of the present invention has been described above, but the present invention is not limited to this embodiment. For example, although the W-polycide film is illustrated as the constituent material of the gate electrode in the above-described embodiments, a polycide film including a polysilicon film, a polymetal film, or a refractory metal silicide film other than WSix may be used. . As the CMOS construction substrate, not only the p-type Si substrate having the n-type well as described above, but also an n-type Si substrate having a p-type well formed, or both p-type and n-type wells are formed. A ν type (low concentration n type) Si substrate may be used. Furthermore, the order of performing the ion implantation for the NMOS and the PMOS may be the reverse of the above. In addition, design rules, details of the substrate structure, ion implantation conditions, CVD conditions, dry etching conditions and the like can be changed as appropriate.

[0044]

As is clear from the above description, according to the present invention, since F ⁺ is present in the Si substrate and is not present in the gate electrode, a shallow junction can be formed in the Si substrate. At the same time, accelerated diffusion of B from the p-type gate electrode of the PMOS can be suppressed. Therefore, a high performance surface channel type PMOS with suppressed short channel effect
Can be manufactured. Moreover, the present invention is extremely economical because it does not involve any additional steps compared with the conventional process and does not require new capital investment or device modification.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view showing a state in which element isolation, well formation, and gate oxidation are performed on a p-type Si substrate in a CMOS manufacturing process to which the present invention is applied.

FIG. 2 is a schematic cross-sectional view showing a state in which a W-polycide film and a resist mask for patterning a gate electrode are formed on the entire surface of the substrate of FIG.

FIG. 3 is a schematic cross-sectional view showing a state in which a gate electrode is formed by dry etching the W-polycide film using the resist mask of FIG. 2 as an etching mask.

FIG. 4 is a schematic cross-sectional view showing a state where F ⁺ ions are implanted on the entire surface of the substrate using the resist mask of FIG. 3 as an ion implantation mask.

5 is a schematic cross-sectional view showing a state in which an NMOS formation region of the base body of FIG. 4 is covered with a resist mask, and low concentration B ⁺ ion implantation is performed in a PMOS formation region to form an LDD region.

6 is a schematic cross-sectional view showing a state in which the PMOS formation region of the substrate of FIG. 5 is covered with a resist mask, and low concentration As ⁺ ion implantation is performed in the NMOS formation region to form an LDD region.

7 is a schematic cross-sectional view showing a state in which an LDD sidewall is formed on the sidewall surface of the gate electrode of FIG.

8 is a schematic cross-sectional view showing a state in which the NMOS formation region of the base body of FIG. 7 is covered with a resist mask, and high concentration B ⁺ ion implantation is performed in the PMOS formation region to form source / drain regions. .

9 is a schematic cross-sectional view showing a state where the PMOS formation region of the substrate of FIG. 8 is covered with a resist mask, and high concentration As ⁺ ion implantation is performed in the NMOS formation region to form source / drain regions. .

FIG. 10 is a graph showing the profile of boron (B) in the depth direction in comparison with the case of the present invention and the case where a gate oxide film penetration occurs.

FIG. 11 is a schematic diagram illustrating a conventional CMOS manufacturing process in which P
BF ₂ ⁺ low concentration ion implantation is performed in the MOS formation region
It is a typical sectional view showing the state where the DD field was formed.

12 is a schematic cross-sectional view showing a state in which an LDD region is formed by performing low-concentration ion implantation of As ⁺ into the NMOS formation region of the base body of FIG. 11. FIG.

13 is a schematic cross-sectional view showing a state where source / drain regions are formed by performing high-concentration ion implantation of BF ₂ ⁺ into the PMOS formation region of the base body of FIG.

14 is a schematic cross-sectional view showing a state where As ⁺ high-concentration ion implantation is performed in the NMOS formation region of the base body of FIG. 13 to form source / drain regions.

[Explanation of symbols]

1 p-type Si substrate 5n, 5p polysilicon film 6n, 6p WSix film 7n, 7p gate electrode 8 resist mask (for patterning the gate electrode) 13 sidewall 15 (PMOS) source / drain region 17 (NMOS) Source / drain region

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 21/336

Claims (4)

[Claims] 1. A step of forming a gate electrode material film including a semiconductor layer on a semiconductor substrate, a step of forming a gate electrode by etching the gate electrode material film through an etching mask, and the etching. A step of ion-implanting into the semiconductor substrate ions that do not impart a specific conductivity type to the semiconductor substrate while leaving the mask, and boron ions are added to the semiconductor substrate and the gate electrode after removing the etching mask. A method of manufacturing a MOS transistor including a step of implanting ions. 2. The method of manufacturing a MOS transistor according to claim 1, wherein a silicon substrate is used as the semiconductor substrate, and fluorine ions are used as the ions that do not impart a specific conductivity type to the semiconductor substrate. 3. The film forming method, wherein the gate electrode material film includes a refractory metal silicide film or a refractory metal film, and the refractory metal silicide film or the refractory metal film can minimize residual fluorine in the film. The M according to claim 1, which is formed into a film.
Manufacturing method of OS transistor. 4. The refractory metal silicide film is a tungsten silicide film, and the film is formed of WF ₆ and SiCl.
_The method of manufacturing a MOS transistor according to claim 3, wherein the film is formed by CVD using a source gas containing ₂ H ₂ .