JP2001177092A - Method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce pn junction leakage at a low voltage in a MOSFET. SOLUTION: An n-type dopant with an LDD-level concentration is added to regions 7 at both the sides of a gate electrode 5 of a (p) well 3. Then, a fluorine ion is ion-implanted into the regions 7. After that, the wafer is retained at 700-720 deg.C under an inert gas atmosphere.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device.

[0002]

2. Description of the Related Art In recent years, with the increase in the degree of integration and high-speed operation of semiconductor integrated circuits, MOSFETs (metal-oxide semiconductors) have been developed.
With the miniaturization of the semiconductor field effect transistor, the gate length tends to be short (for example, 500 nm or less) and the gate oxide film has a small thickness (for example, 10 nm or less). In addition, the pn junction depth of the source / drain region is made shallower (for example, 100 nm or less).

Japanese Patent Application Laid-Open No. 61-90431 discloses that after a fluorine-containing ion is implanted into a predetermined region on a silicon substrate (both sides of a gate electrode and a region where a source / drain is formed), It is described that an n-type dopant or a p-type dopant is ion-implanted into this region to form a source / drain region, and thereafter a dopant activation treatment is performed. According to this method, a silicon crystal is made amorphous by ion implantation of ions containing fluorine atoms, and a dechanneling phenomenon (a phenomenon in which impurity atoms are scattered by interaction with a crystal lattice and enter in a channel direction). ), It is possible to form a source / drain region having a shallow junction.

Japanese Patent Application Laid-Open No. 4-287332 discloses that an amorphous layer is formed by ion-implanting silicon or the like into a predetermined region (a region on both sides of a gate electrode and forming a source / drain) on a silicon substrate. After the formation, a method of reducing a crystal defect layer caused by the formation of the amorphous layer is described. That is, as a method of reducing the crystal defect layer, an n-type dopant (P ⁺ , As ⁺ ) or a p-type dopant (B
After ion implantation of F ₂ ⁺ ), carbon, nitrogen,
It is described that ion implantation of one or two or more kinds of impurities of oxygen or fluorine is performed, and then heat treatment (for example, at 1000 ° C. for 15 seconds) is performed.

Further, it is described that this crystal defect layer is generated on the silicon substrate side from the interface between the amorphous layer and the silicon substrate, and an n-type or p-type dopant is implanted into the amorphous layer. That is, in this method, ion implantation of carbon or the like is performed on a region below the region where the dopant is ion-implanted.

[0006]

However, in the case of MOSFETs obtained by the above-mentioned conventional technology, especially in the case of an n-channel MOSFET, a pn junction leak at a low voltage (a pn junction between a source / drain region and a silicon substrate). There is room for improvement in reducing (leakage current due to failure).

The present invention has been made in view of such problems of the prior art. The gate length is short, the thickness of the gate oxide film is small, and the pn junction depth of the source / drain region is small. It is an object to reduce pn junction leakage at a low voltage in a MOSFET.

[0008]

In order to solve the above-mentioned problems, the present invention provides a source-drain transistor of a field-effect transistor by ion-implanting an n-type dopant or a p-type dopant into a predetermined region of single crystal silicon. In a method for manufacturing a semiconductor device having a step of forming a region,
After ion implantation of the dopant, fluorine ions are ion-implanted in the same region as the region in which the dopant is ion-implanted, and then 700 to 720 ° C. in an inert gas atmosphere.
A method for manufacturing a semiconductor device, characterized by performing a heat treatment for holding the semiconductor device.

The present invention also provides a gate electrode forming step of forming a gate electrode on a single-crystal silicon doped with a first conductivity type via a gate insulating film, and a region on both sides of the gate electrode of the single-crystal silicon. A first doping step of ion-implanting a dopant of a second conductivity type, a step of forming sidewall spacers on both side surfaces of the gate electrode, and a step of forming a region doped in the first doping step outside the sidewall spacers. A second doping step of further ion-implanting a second conductivity type impurity into a region to be formed;
In the method for manufacturing a semiconductor device having the above, after the ion implantation of the dopant in the first doping step and before the side wall spacer forming step, fluorine ions are ion-implanted in the same region as the region in which the dopant has been ion-implanted. After that, a method for manufacturing a semiconductor device is provided, in which heat treatment is performed at 700 to 720 ° C. in an inert gas atmosphere.

[0010]

Embodiments of the present invention will be described below. FIG. 1 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device corresponding to one embodiment of the present invention. here,
An n-channel MOSFET (hereinafter abbreviated as “NMOS”) and a p-channel MOSFET (hereinafter “PMO”)
S ". C) (complementary) M
The OSFET will be described as an example.

First, as shown in FIG. 1A, an n-well 2 and a p-well 3 are formed on a p-type silicon substrate 1. Next, a gate electrode 5 is formed on the n well 2 and the p well 3 with a gate oxide film 4 interposed therebetween. The gate electrode 5 has a two-layer structure including a polysilicon layer 51 doped with an n-type dopant and a WSi layer 52. The thickness of the gate oxide film 4 is 8 nm (80 °), the thickness of the polysilicon layer 51 is 2000 °, the thickness of the WSi layer 52 is 1500 °, and the gate length is 0.1 mm.
5 μm.

This gate electrode forming step is performed by a conventionally known method. Reference numeral 11 denotes a LOCOS (Local Oxidation Of Silicon) film provided for element isolation. Next, as shown in FIG. 1B, BF ₂ ⁺ is ion-implanted as a p-type dopant into a region 6 on both sides of the gate electrode 5 of the n-well 2 where a source / drain is to be formed. Next, P ⁺ or As ⁺ is ion-implanted as an n-type dopant into the region 7 on both sides of the gate electrode 5 of the p well 3 where the source / drain is to be formed.

[0013] These ion implantations are the first dopant of the present invention.
This corresponds to a ping process. In this first doping step, L
Single-crystal silicon at DD (Lightly Doped Drain) level
N-type dopant or p-type
This is a step of adding a dopant. Area on n-well 2 side
6 are, for example, implantation energy
40 keV, injection amount 1 × 10¹⁴ions / cm^TwoAnd p
The ion implantation conditions for the region 7 on the well 3 side are, for example,
For example, an implantation energy of 40 keV and an implantation amount of 5 × 10 ¹⁴ions
/ Cm^TwoAnd The depth of each of the regions 6 and 7 is, for example, about 500.
Å.

Next, F ⁺ ions are implanted into the region 7 on the p-well 3 side. This ion implantation is performed, for example, under the conditions of an implantation energy of 15 keV and an implantation amount of 2 × 10 ¹⁴ ions / cm ² . Next, in this state, the wafer is placed in a normal thermal diffusion furnace, and 700 to 72% in an atmosphere of 100% nitrogen gas.
Hold at 0 ° C. for 20 minutes. Next, as shown in FIG. 1C, sidewall spacers 8 are provided on both side surfaces of the gate electrode 5.
To form This sidewall spacer forming step includes:
This is performed by a conventionally known method. For example, after forming a TEOS (tetraethylorthosilicate) film with a film thickness of 2500 °, anisotropic dry etching is performed to form the sidewall spacers 8. The width of the sidewall spacers 8 at the positions of the regions 6 and 7 is, for example, 0.2.
μm.

Next, BF ₂ ⁺ is ion-implanted as a p-type dopant into a region 61 outside the sidewall spacer 8 in the region 6 on the n-well 2 side. Next, As.sup. ⁺ Is ion-implanted as an n-type dopant into a region 71 outside the sidewall spacer 8 in the region 7 on the p-well 3 side. These ion implantations correspond to the second doping step of the present invention. This second doping step is a step of further adding an n-type dopant or a p-type dopant to increase the dopant concentration of the regions 61 and 71 to the source / drain level. Region 6 on n-well 2 side
The ion implantation conditions for 1 are, for example, an implantation energy of 35 keV and an implantation amount of 2.0 × 10 ¹⁵ ions / cm ² . The ion implantation conditions for the region 71 on the p-well 3 side are, for example, an implantation energy of 35 keV and an implantation amount of 2.0.
× 10 ¹⁵ ions / cm ² . The depth of each of the regions 61 and 71 is, for example, about 300 °.

As a result, as shown in FIG.
In the well 2, an LDD is formed inside the source / drain region 61.
A PMOS having a structure having a region 62 is formed, and an NMOS having a structure having an LDD region 72 inside a source / drain region 71 is formed in the p-well 3. Next, a BPSG film (Boro-phospho silicate gl
ass film: SiO with B ₂ O ₃ and P ₂ O ₅ added
₂ ), heat treatment is performed at 850 ° C. for 20 minutes in a nitrogen atmosphere. After that, the steps of forming the metal wiring and the like are performed by a conventionally known method, whereby the CMOSFET is formed.
Is obtained.

The above-described F ⁺ ion implantation step and the heat treatment step of maintaining the temperature at 700 to 720 ° C. for 20 minutes in an atmosphere of 100% nitrogen gas are not performed. The pn junction leak at a low voltage (drain voltage 0.1 V or less) occurred at a probability of several percent in the NMOS. On the other hand, the pn junction leak at a low voltage did not occur in the NMOS of the CMOSFET obtained by the above method. That is, according to the method of this embodiment, the pn junction leakage at a low voltage is reduced.
A MOSFET can be obtained.

The reason will be described with reference to FIG. The pn junction leak is caused by a silicon crystal defect.
That is, a dangling bond generated by dislocation of a crystal or the like, a bond that is not bonded: Si
If −) are arranged in a line, carriers are conducted along the line by the hopping mechanism, and a leakage current occurs.

For example, by ion implantation of an n-type dopant into the p well 3, a dangling bond 31 of silicon is formed at the pn junction of the p well 3. The dangling bond 31 reacts and bonds with the fluorine atom 9 by an ion implantation step of F ⁺ and a heat treatment step of maintaining the temperature at 700 to 720 ° C. in an atmosphere of 100% nitrogen gas. As a result, crystal defects are repaired, and pn junction leakage is reduced.

If the heat treatment temperature in this heat treatment step is lower than 700 ° C., the reaction between the dangling bond 31 and the fluorine atoms 9 hardly occurs. When the heat treatment temperature exceeds 720 ° C., the ion-implanted F ⁺ evaporates before bonding with the dangling bond 31 and is easily released to the outside. In addition, PMO
On the S side, BF ₂ ⁺ is added to n well 2 as a p-type dopant.
This ion doping allows
Fluorine atoms are introduced into region 6. Therefore, the effect of repairing crystal defects can be obtained without performing the F ⁺ ion implantation step and the heat treatment step later. It is presumed that this is the reason why the pn junction leakage has conventionally been a problem particularly on the NMOS side, and has not been particularly problematic on the PMOS side.

Therefore, in this embodiment, the F ⁺ ion implantation step and the heat treatment step after the dopant ion implantation are performed only on the NMOS side. However, the present invention is not limited to this. In the case of ion-implanting ions containing no fluorine atom as a p-type dopant in a PMOS, an ion implantation step of F ⁺ is performed after the ion implantation of the dopant, and then the above-described ion implantation step is performed. Preferably, a heat treatment step is performed.

[0022]

As described above, according to the method of the present invention, even if the gate length is short, the thickness of the gate oxide film is small, and the pn junction depth of the source / drain region is small, the M
The pn junction leak at a low voltage of the OSFET can be reduced. As a result, a more miniaturized MOSFET can be obtained at a high yield, and the reliability is improved.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a diagram for explaining the operation of the present invention.

[Explanation of symbols]

Reference Signs List 1 silicon substrate 2 n-well 3 p-well 4 gate oxide film 5 gate electrode 6 region for forming source / drain (predetermined region of single crystal silicon) 7 region for forming source / drain (predetermined region of single crystal silicon) 8 side Wall spacer 9 Fluorine atom 11 LOCOS film 31 Dangling bond 51 Polysilicon layer 52 WSi layer

Claims (2)

[Claims] 1. A method for manufacturing a semiconductor device, comprising: forming a source / drain region of a field-effect transistor by ion-implanting an n-type dopant or a p-type dopant into a predetermined region of single-crystal silicon. After ion implantation of fluorine, ion implantation of fluorine ions is performed in the same region as the region where the dopant is ion-implanted, and then 700 to 720 ° C. in an inert gas atmosphere.
A method for manufacturing a semiconductor device, comprising: performing a heat treatment for holding the semiconductor device. 2. A gate electrode forming step of forming a gate electrode on a single-crystal silicon doped with a first conductivity type via a gate insulating film, and a second step in a region on both sides of the single-crystal silicon gate electrode. A first doping step of ion-implanting a conductive type dopant, a step of forming sidewall spacers on both side surfaces of the gate electrode, and a step of doping the first doping step into a region outside the sidewall spacer. A second doping step of further ion-implanting impurities of the second conductivity type, wherein after the ion implantation of the dopant in the first doping step and before the sidewall spacer forming step, After the fluorine ions are ion-implanted in the same region as the region where the dopant is ion-implanted, an inert gas atmosphere is used. In 700
A method for manufacturing a semiconductor device, comprising performing heat treatment at a temperature of from about 720 ° C. to about 720 ° C.