KR100288686B1 - Semiconductor device manufacturing method - Google Patents

Abstract

In order to prevent gate penetration in the thin gate oxide layer due to the miniaturization of semiconductor devices, and to prevent the lateral diffusion of impurities in the source / drain, a gate electrode is formed on a silicon wafer having a device isolation region defined therein, Impurities are implanted to form a source / drain, and nitrogen ions are implanted before or after impurity ion implantation. Then, the silicon wafer is annealed by a rapid heat treatment process to form a source / drain junction layer. The surface of the gate oxide film is formed of a nitride film to suppress gate penetration due to diffusion of impurities, and impurities in the source / drain By suppressing the side diffusion of the not only improves the reliability of the fine semiconductor device but also improves the yield of the fine semiconductor device manufacturing process.

Description

Semiconductor device manufacturing method {SEMICONDUCTOR DEVICE MANUFACTURING METHOD}

The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a shallow junction with a gate oxide film of a semiconductor device.

In general, semiconductor devices may be structurally divided into transistors, bipolar integrated circuits (ICs), and metal-oxide-semiconductor (MOS) ICs. Such a semiconductor device basically has a structure in which an electrode region of each device, such as a base / emitter / collector or a gate / source / drain, is formed on a silicon wafer. The semiconductor device uses a metal-oxide-semiconductor condenser structure, and a channel that becomes a passage of current just under the gate oxide film on the semiconductor substrate is formed by a bias applied between the metal electrode and the semiconductor substrate, which bias Controlled by value is the basic principle. In order to obtain accurate device characteristics in such a semiconductor device, the electrical characteristics of the gate oxide film to determine the bias value should be excellent.

Next, a method of manufacturing a conventional semiconductor device will be described with reference to FIGS. 1A to 1C.

First, as shown in FIG. 1A, a gate oxide film 2 is grown by thermally oxidizing a silicon wafer 1 in which a semiconductor device isolation region is defined, and then polysilicon is formed by chemical vapor deposition (CVD) thereon. After (3) is deposited, the polysilicon 3 and the gate oxide film 2 are patterned to form a gate electrode. Then, a thick insulating film is deposited on the entire surface of the silicon wafer 1 and anisotropically etched to form the spacers 4 on the sidewalls of the gate electrodes.

Next, as shown in FIG. 1B, an ion implantation (I1) of P-type or N-type impurities such as boron (B), phosphorus (P), or arsenic (As) is ion-injected (I1) on the entire surface of the silicon wafer 1 to form a source / drain. (5) That is, a shallow junction of semiconductor elements is formed.

Then, as illustrated in FIG. 1C, the silicon wafer 1 is annealed to activate damage compensation and ion implanted impurities of the silicon wafer due to the ion implantation I1, and then wet-clean the semiconductor device. Complete

In the conventional semiconductor device manufacturing process, the size of the semiconductor device is being reduced to sub-micron, and in the corresponding field effect transistor (FET), the thickness of the gate oxide film is reduced to several tens of micrometers or less. Channel lengths have also been reduced to sub-microns.

When the thickness of the gate oxide film of the semiconductor device becomes thin in this manner, a gate penetration due to the diffusion of boron in the P-MOS, particularly the doped poly of the gate electrode, and a FN tunnel (Fowler-Nordheim tunnel) appearing in the gate oxide film of 30 kV Current leakage due to the < RTI ID = 0.0 >), < / RTI > a direct tunnel phenomenon appearing at the gate oxide film thickness below it. Gate penetration by diffusion of double boron is fundamentally inevitable in the oxide gate, and causes a fatal problem for the field effect transistor.

In order to cope with the reduction of the channel length, the junction channel of the field effect transistor is gradually shallower to form a shallow junction, but in the annealing process performed after the impurity ion implantation, the lateral diffusion of the doped impurities in the junction layer is performed. Due to the TED (transient enhanced diffusion) (6 of FIG. 1C), deterioration of the junction and a change in the channel length occur, thereby lowering the reliability of the semiconductor device.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and an object thereof is to prevent gate penetration in a thin gate oxide film due to miniaturization of a semiconductor device, and a semiconductor device manufacturing method capable of preventing TED due to side diffusion of impurities. To provide.

1A to 1C are process diagrams schematically illustrating a method of manufacturing a conventional semiconductor device.

2A through 2D are process diagrams schematically illustrating a method of manufacturing a semiconductor device according to the present invention.

In order to achieve the above object, the present invention implants nitrogen ions before or after ion implantation for source / drain formation of a semiconductor device, and at the same time to form a junction layer of the source / drain by a subsequent rapid heat treatment process The surface of the gate oxide film is formed of a nitride film.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

2A through 2D are process diagrams schematically illustrating a method of manufacturing a semiconductor device according to the present invention.

First, as shown in FIG. 2A, the gate oxide film 12 is grown by thermally oxidizing a silicon wafer 11 having a semiconductor device isolation region, and thereafter, polysilicon 13 is deposited by chemical vapor deposition. The polysilicon 13 and the gate oxide film 12 are patterned to form a gate electrode. A thick insulating film is deposited on the entire surface of the silicon wafer 11 and anisotropically etched to form the spacers 14 on the sidewalls of the gate electrodes.

Next, as shown in FIG. 2B, a shallow junction layer 15, which is a source / drain of a semiconductor device, is implanted (I11) by implanting P-type or N-type impurities such as boron, phosphorus, arsenic, and the like onto the entire surface of the silicon wafer 11. To form.

Next, as shown in FIG. 2C, nitrogen (N) ions are implanted (I12) on the entire surface of the silicon wafer 11 to form a junction layer 15 of the silicon wafer 11 doped with P-type or N-type impurities. Nitrogen ions are further doped into the polysilicon 13 of the gate electrode. At this time, the ion amount of nitrogen to be ion implanted (I12) is preferably 1.0 × 10 ⁻¹¹ cm ⁻² to 1.0 × 10 ⁻¹⁴ cm ⁻² , and the ion implantation energy is preferably 10 KeV to 30 KeV.

Then, as shown in Fig. 2d, the silicon wafer 11 is annealed, preferably subjected to rapid thermal annealing (RTA) at a temperature of 1000 ° C to 1100 ° C for 5 seconds to 15 seconds to obtain ions. The semiconductor device is completed by compensating for damage to the silicon wafer due to the implantation (I11) and at the same time as the implantation (I12), activating the impurities implanted in the ion implantation (I11), and wet cleaning. At this time, the nitrogen ions doped in the polysilicon 13 of the gate electrode are piled up to the surface of the gate oxide film 12, and the nitride film is formed by the reaction at the interface of the gate oxide film 12. Therefore, the gate penetration due to the doped impurities in the polysilicon 13, in particular, the boron diffusion in the P-MOS is suppressed. In the source / drain which is the bonding layer 15 of the silicon wafer 11, nitrogen ions are present around the P-type or N-type impurities, and P-type or N-type impurities are activated by a rapid heat treatment process. Lateral diffusion is suppressed by nitrogen ions around the impurity to suppress the TED phenomenon in which the impurity penetrates into the channel region, thereby forming a shallow junction by ion implantation of low energy. Moreover, in field effect transistors, there are no nitrogen ions in the actual channel between the source / drain regions, which does not cause the parasitic resistance problem in the channel.

In the above embodiment, the nitrogen ion implantation (I12) is performed after the impurity ion implantation (I11) for source / drain formation. Alternatively, the nitrogen ion implantation (I12) is performed after the impurity ion implantation (I11) for source / drain formation. It may be carried out before.

As described above, in the process of fabricating a semiconductor device, by injecting nitrogen ions prior to annealing to form a shallow junction of a source / drain, the surface of the gate oxide film is formed as a nitride film by annealing, thereby performing gate penetration by diffusion of impurities. In addition, since the shallow junction can be formed by suppressing the TED at the source / drain, the reliability of the fine semiconductor device can be improved and the yield of the fine semiconductor device manufacturing process can be improved.

Claims (5)

Forming a gate electrode on a silicon wafer in which device isolation regions are defined; Ion implanting impurities into the silicon wafer for source / drain formation; Annealing the silicon wafer to form a junction layer of a source / drain, And implanting impurities for source / drain formation into the silicon wafer further comprises implanting nitrogen ions. The method of claim 1, wherein the nitrogen ion implantation is performed before or after the impurity ion implantation for forming the source / drain. The method of manufacturing a semiconductor device according to claim 2, wherein the nitrogen ion is implanted with an energy of 10KeV to 30KeV in an ion amount of 1.0 × 10 ⁻¹¹ cm ⁻² to 1.0 × 10 ⁻¹⁴ cm ⁻² . . The method of manufacturing a semiconductor device according to any one of claims 1 to 3, wherein in the step of annealing the silicon wafer to form a junction layer of a source / drain, the annealing is performed by a rapid heat treatment process. The method of claim 4, wherein the rapid heat treatment is performed at a temperature of 1000 ° C. to 1100 ° C. for 5 seconds to 15 seconds.