JP2781989B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a large-scale integration (Large Scale In
The present invention relates to a method for manufacturing a semiconductor device having a shallow source / drain junction having good current-voltage characteristics required for fabricating a circuit, and particularly to a field-effect transistor such as a miniaturized metal-oxide. Metal Oxide Semiconductor Field Effe
ct Transistor, MOSFET).

[Conventional technology]

Research on further miniaturization of large-scale integrated circuits (LSIs) has been pursued for higher performance and higher integration, and field-effect transistors such as fine MOSFETs (MOS)
Field-effect transistors), MOSFETs
It is essential that a shallow junction having a depth of about 0.1 μm or less be used as a junction used as a source and a drain of the semiconductor device. Conventionally, as a method of forming a junction on a silicon (Si) substrate, B (Boron, arsenic) is formed on an N-type silicon substrate when a P ⁺ N junction is formed, and when an N ⁺ P junction is formed on the N-type silicon substrate. In this method, As (Arsenic, arsenic) or P (Phosphorus, phosphorus) ions are implanted into a P-type silicon substrate, and annealing is performed in an electric furnace.

However, it has been difficult to form a shallow junction due to diffusion of impurities during annealing. For this reason, instead of the conventional electric furnace annealing, lamp annealing, which can be activated without causing much diffusion of impurities, has been used as an effective method for forming a shallow junction.

However, when low-energy ion implantation, which is indispensable for forming a shallow junction, is performed, especially in the case of B used for forming a P ⁺ N junction, channeling occurs even when ions are implanted shifted from the low-index crystal axis direction, and impurities are generated. There is a problem that it cannot penetrate deeply and make the junction shallow.

In order to suppress the channeling, a method has been proposed in which, for example, ions that do not affect the electrical characteristics before the ion implantation of B, for example, Si ions are implanted, thereby making the vicinity of the surface of the Si substrate amorphous. I have.

According to this method, channeling can be prevented and a shallow junction can be formed due to the ion implantation into the amorphous. However, the influence of crystal defects introduced by the ion implantation of Si for amorphization. Therefore, there is a problem that the leak current of the junction diode becomes large and a shallow junction having good current-voltage characteristics cannot be formed.

As a method for solving this problem, Japanese Patent Application Laid-Open No. 63-1557 discloses that the inventor of the present application is one of the inventors of the present invention.
As described in Japanese Patent Publication No. 20 "Method of Manufacturing Semiconductor Device", a method of forming a shallow junction having good characteristics by slightly diffusing impurities during annealing has been disclosed.

However, in this method, the junction depth is about 800 to 100
Although a junction of about 0 ° can be formed, it is difficult to form a junction of about 500 °, which is shallower than the above value, because of the method of diffusing impurities.

[Problems to be solved by the invention]

An object of the present invention is to solve the above-described problems of the conventional shallow PN junction forming technology and to include a step of forming an extremely shallow junction having good current-voltage characteristics with suppressed leakage current. To provide a method of manufacturing a semiconductor device.

[Means for solving the problem]

First, a technique for forming a shallow junction by amorphization, which is the gist of the present invention, will be described. Taking the application to the formation of a shallow P ⁺ N junction as an example, here, the case of B as the impurity ion will be described, but it is clear that the gist of the present invention is not limited to this.

In order to completely prevent channeling by amorphization, it is necessary to make the depth of the amorphous layer (5) deeper than the implantation depth of B. However, after annealing after ion implantation of B into the amorphous layer (5), a crystal defect (7) occurs near the interface between the original amorphous layer (5) and the silicon single crystal, and this crystal defect is generated. It has been clarified that (7) causes degradation of diode characteristics such as an increase in leakage current of a P ⁺ N junction diode.

As a result of various experimental studies, it has been found that the diode characteristics are degraded when the crystal defect (7) is in the depletion layer, and good diode characteristics can be obtained when the crystal defects (7) are not in the depletion layer.

In Japanese Patent Application Laid-Open No. 63-155720, "Method of Manufacturing Semiconductor Device", which is a prior art, in order to solve the problem of deterioration of the diode characteristics, diffusion by heat treatment (annealing) after B ion implantation is performed. Crystal defect at joining position (7)
The junction having good diode characteristics is obtained by making the position deeper than the position.

The present invention is characterized in that it includes a step of preventing channeling by amorphization and forming an extremely shallow junction having good diode characteristics without causing diffusion during annealing after B ion implantation. A method for manufacturing a semiconductor device is provided.

The present invention is characterized in that a very shallow junction can be formed to prevent diffusion.

In the disclosure of Japanese Patent Application Laid-Open No. 63-155720 "Method of Manufacturing Semiconductor Device" as a prior art, crystal defects (7)
Was formed in the P ⁺ (6) layer, that is, at a position shallower than the junction depth, whereby good diode characteristics were obtained.

On the other hand, in the present invention, the depth (W ₂ ) of the depletion layer extending from the P ⁺ N junction surface into the N layer or from the N ⁺ P junction surface into the P layer when the voltage is applied to operate the device. By positioning the crystal defect layer (7) at a deeper position than
It is intended to realize good diode characteristics.

By the way, in a general method of manufacturing a MOSFET, ion implantation for forming a source and a drain is usually performed by a self-alignment process using the gate electrode (4) as a mask at the time of ion implantation. Therefore, Si for amorphization
The ion implantation needs to be performed after the formation of the gate electrode (4). At this time, since the amorphous layer (5) spreads laterally from the side wall of the gate electrode (4), the crystal defect layer (7) is formed. Is located in a shallow place immediately below the gate electrode (4), that is, when it is to be a channel, and may adversely affect the electrical characteristics of the MOSFET.

One of the important features of the present invention is that the laterally extending crystal defect layer (7) does not adversely affect the characteristics of the MOSFET. Therefore, in the present invention, the depth (W ₁ ) of the amorphous layer (5) is made equal to or greater than the gate length, and the gate electrode (4) is expanded by the lateral spread of the ion-implanted ions. The above problem was solved by making all the layers directly below amorphous or by forming an amorphous layer (5) having a depth sufficiently deeper than the thickness of the gate electrode (4). That is, in the latter, the above requirement is realized by completely amorphizing immediately below the gate electrode (4) through the gate electrode (4).

According to the present invention, when an amorphization technique is applied to formation of a source / drain region by a self-alignment process using a gate electrode (4) as a mask, an amorphous layer (5) is formed by first ion implantation.
After forming the gate electrode, in the step of implanting impurity ions by the second ion implantation to form a junction, the gate electrode (4) is formed.
Immediately below, the depth of the amorphous layer (5) formed by the first ion implantation to such an extent as to be amorphized from the lateral direction or to be amorphized through the gate electrode (4). (W ₁₎
So that the depth (W ₂ ) of the depletion layer of the junction formed by the second ion implantation and the subsequent annealing is shallower than the interface between the original amorphous layer (5) and the single crystal. Is the most important feature.

Accordingly, the configuration of the present invention is as described below. That is, in the manufacturing process of the field effect transistor, after forming the gate electrode (4), inactive first ions that do not affect the electrical characteristics of the semiconductor are ion-implanted to form the source region (6).
-1) a first step of forming an amorphous layer (5) in a region to be a drain region (6-2) and a region to be a channel region below the gate electrode (4); A second step of ion-implanting a highly active second ion; and a third step of performing a heat treatment for recrystallization of the amorphous layer (5) and activating impurities introduced by the second ion implantation. In the method of manufacturing a semiconductor device, the depth (W ₁ ) of a crystal defect (7) generated when the amorphous layer (5) is recrystallized in the third step is:
A source region (6-1) of the field-effect transistor,
Drain regions (6-2) cage the amorphous layer (5) of recrystallized spread in the layer depletion layer, so as to deeper than deeper depth (W _2), and the second The implantation energy and implantation energy of the ion implantation in the first step are set so that the region to be the channel region immediately below the gate electrode (4) is made amorphous by the lateral spread of the ions implanted in the first step. Amount and the gate electrode (4)
And a step of selecting and forming the gate length of the semiconductor device.

Alternatively, in the manufacturing process of the field effect transistor, after forming the gate electrode (4), inactive first ions that do not affect the electrical characteristics of the semiconductor are ion-implanted to form the source region (6-1) and the drain region. A first step of forming an amorphous layer (5) in a region to be (6-2) and a region to be a channel region below the gate electrode (4); A semiconductor comprising: a second step of implanting ions; and a third step of performing a heat treatment for recrystallization of the amorphous layer (5) and activating impurities introduced by the second ion implantation. In the device manufacturing method, in the third step, the depth (W ₂ ) of a crystal defect (7) generated when the amorphous layer (5) is recrystallized is
A source region (6-1) of the field-effect transistor,
The amorphous layer than the drain region (6-2) (5) of recrystallized spread in the layer depletion layer, so as to deeper than deeper depth (W _1), and a gate electrode (4)
The implantation energy and implantation amount of the ion implantation in the first step and the thickness of the gate electrode (4) are selected so that the region which is to be a channel region immediately below the gate electrode (4) through the gate electrode is also made amorphous. The method has a configuration as a method of manufacturing a semiconductor device, including a step of forming the semiconductor device.

〔Example〕

FIGS. 1A to 1E are schematic sectional structural views for explaining a method of manufacturing a semiconductor device as a first embodiment of the present invention, and show a MOS type large scale integrated circuit (MOS LSI). Of the present invention when applied to the manufacture of
1 shows a manufacturing process of a MOSFET. In FIG. 1, 1 is an N-type Si substrate,
2 is a field oxide film, 3 is a gate oxide film, 4 is a low-resistance polycrystalline silicon gate electrode, 5 is an amorphous layer, 6 is a P ⁺ layer (source and drain), and 7 is an amorphous layer. Reference numeral 8 denotes an interlayer insulating film, and reference numeral 9 denotes an Al electrode.

First, as shown in FIG.
5000 mm thick field oxide film 2 according to SI manufacturing process
Is formed, a gate oxide film 3 having a thickness of 100 ° is formed in a dry oxygen atmosphere. Next, the impurity concentration (P concentration) of the channel region is reduced by, for example, ion implantation of P at a low concentration.
Adjust to a concentration of 3 × 10 ¹⁷ cm ⁻³ . Then, the gate electrode 4
Low-resistance polycrystalline silicon used as
And a gate electrode 4 is formed using ordinary photolithography or electron beam lithography. Here, an extremely fine gate electrode 4 having a gate length of about 0.1 μm is formed by electron beam lithography and dry etching.

Next, as shown in FIG. 1 (b), prior to ion implantation for forming a P ⁺ N junction used as a source and a drain, Si ions are implanted at a predetermined acceleration energy and implantation amount, for example, 150 KeV, Ion implantation under conditions of × 10 ¹⁵ cm ^-2 , N-type
An amorphous layer 5 is formed in a Si substrate 1. When the ions are implanted under the conditions shown here, the depth of the amorphous layer 5 is 3000 °. Since the gate length is 0.1 μm, the N-type Si substrate 1 immediately below the gate is made amorphous as shown in FIG. 1 (b) due to the lateral spread of the ions at the time of Si ion implantation.

FIG. 2 illustrates the relationship between the depth of the amorphous layer 5 and the implantation energy of Si in the first embodiment of the present invention. As shown in FIG. 2, it can be seen that the depth of the amorphous layer 5 can be controlled by the implantation energy of Si. In some cases, ion implantation (multi-stage ion implantation) may be performed using two or more implantation energies as necessary. In this case, the amorphous layer 5 from the Si surface with the maximum implantation energy is used.
Is determined. For example, the ion implantation energy of Si
At 150 KeV and a dose of 2 × 10 ¹⁵ cm ⁻² , the thickness of the amorphous layer 5 is 30
It will be readily apparent from FIG.

Next, as shown in FIG. 1 (c), the source, for the P ⁺ N junction formed of P ⁺ layer 6 is used as a drain, a low acceleration energy of BF ₂ ions of a predetermined and prescribed injection quantity, for example, Fifteen
Ion implantation is performed under the conditions of KeV and 1 × 10 ¹⁴ cm ⁻² . Where B
The reason for using F ₂ ions is to obtain low-energy B ions, and 15 keV BF ₂ ion implantation is equivalent to 3.4 keV B ion implantation.

Thereafter, as shown in FIG. 1 (d), heat treatment, for example, lamp annealing is performed at 900 ° C. for 10 seconds to activate B introduced by ion implantation and to form an amorphous layer. 5 is formed. As a result, the amorphous layer 5 becomes a single crystal, so that the Si ion implantation does not affect the electrical characteristics such as the resistance of the P ⁺ layer 6.

FIG. 3 shows the concentration distribution of B in the P ⁺ layer 6 in the depth direction in the first embodiment of the present invention. In FIG. Represents the distribution after lamp annealing, Represents the distribution immediately after ion implantation. It has been known that when ion-implanted B is annealed, the distribution shape is expanded even by short-time annealing such as lamp annealing due to accelerated diffusion based on damage caused by ion implantation. On the other hand, since the above-mentioned accelerated diffusion is suppressed in the amorphous layer 5, B hardly diffuses in the annealing for activation, and as shown in FIG. An extremely shallow PN junction is formed. At this time, a crystal defect 7 due to ion implantation for forming the amorphous layer is formed near the interface between the original amorphous layer 5 and the single crystal. The influence of the crystal defect 7 will be described later in detail. State.

With the above manufacturing method, shallow P ⁺ for source and drain
After the N-junction is formed, according to a normal MOS LSI manufacturing process, as shown in FIG. 1E, after depositing an interlayer insulating film 8, patterning is performed to form an electrode layer for source, drain and gate. That is, for example, an Al electrode 9 is formed, and a P-channel MOSFET is manufactured.

As shown in FIGS. 1 (d) and 1 (e), when the amorphous layer 5 is formed by ion implantation, after annealing, crystal defects are found near the interface between the amorphous layer 5 and the single crystal. Occur. This crystal defect is indicated by 7. When the crystal defect 7 is in the depletion layer of the semiconductor, it acts as a center of generation and recombination, which adversely affects electrical characteristics such as an increase in leakage current in the reverse direction of the PN junction.

In the present invention, by making the crystal defects 7 accompanying the amorphization not exist in the depletion layers on the source side and the drain side, consideration is given so that deterioration of characteristics such as increase in leak current does not occur. I have.

Figure 4 is an enlarged view of a sectional structure of a MOSFET formed by using a manufacturing method of the semiconductor device described in the embodiment of the present invention, the source for the P ⁺ layer 6-1, 6-2 for a drain P
^{The +} layer, 10 is the end of the depletion layer. As shown in FIG.
In the operating state of the OSFET, a depletion layer on the drain side is extended by a voltage applied to the drain. However, Si for amorphization is formed such that the depth W ₂ of the depletion layer is smaller than the depth W ₁ of the crystal defect 7. The ion implantation energy is selected. That was set such that the distance W ₁ illustrated in Figure 4 is larger than the distance W _2. That is, in FIG. 4, W ₁ represents the distance from the crystal surface of the semiconductor substrate to the crystal defect 7 accompanying ion implantation for forming the amorphous layer 5, and W ₂ is applied from the crystal surface of the semiconductor substrate to the operating state of the MOSFET. It shows the dimension up to the distance at which the depletion layer spreads with the applied voltage. Further, since the direction of the depth W ₁ of the amorphous layer 5 as compared with the gate length is large, crystal defects 7 at a portion to be a channel region immediately under the gate due to the ion implantation for the amorphous layer 5 formed It does not exist and does not cause degradation of MOSFET characteristics such as a decrease in mobility.

As described above, according to the method of manufacturing a semiconductor device of the present invention, diffusion during channeling and annealing is prevented, and miniaturization formed by a source and a drain having a shallow PN junction having good current-voltage characteristics is achieved. MOSFETs can be manufactured.

In the above embodiment, in the Si ion implantation for amorphization, the portion immediately below the gate is made amorphous by the spread of the implanted ions in the lateral direction, which is effective when the gate length is short. is there.

Next, another embodiment which is effective even when the gate length is long will be described. 5 (a) to 5 (e) are schematic sectional structural views for explaining a method of manufacturing a semiconductor device according to a second embodiment of the present invention. 5 is an embodiment relating to a method of manufacturing a semiconductor device characterized in that it is characterized

As shown in FIG. 5A, a field oxide film 2 having a thickness of 5000 ° and a gate oxide film 3 having a thickness of 100 ° are formed.

Next, low-resistance polycrystalline silicon used as the gate electrode 4 is deposited to a thickness of 2000.degree., And the gate electrode 4 is formed using photolithography or electron beam lithography.

Next, as shown in FIG. 5 (b), the source, prior to the ion implantation for the P ⁺ N junction formed of P ⁺ layer 6 is used as a drain, the Si ions with a predetermined acceleration energy injection amount, For example, ions are implanted under the conditions of 200 keV and 2 × 10 ¹⁵ cm ⁻² to form the amorphous layer 5 in the N-type Si substrate 1. When the ions are implanted under the conditions shown here, the depth of the amorphous layer 5 is 40
5B, Si ions penetrate into the gate electrode 4 and enter the Si substrate 1, as shown in FIG.
The portion immediately below the gate electrode 4, that is, the portion to be a channel region is also amorphized.

Subsequent steps are the same as those of the first embodiment described with reference to FIG. 1, and as shown in FIGS. 5 (c), (d) and (e), the P ⁺ layer 6, the interlayer insulation The film 8 and the Al electrode 9 are formed,
A P-channel MOSFET is manufactured.

Also in the second embodiment described above, the crystal defect 7 accompanying the amorphization is formed at a deep position including a portion to be a channel region as shown in FIGS. 5 (d) and 5 (e). Runode depletion layer W ₂ of the drain-side does not reach to a depth W ₁ of the crystal defects 7 can be produced shallow source, MOSFET having a drain with good diode characteristics.

In the method of manufacturing a semiconductor device according to the present invention shown in the second embodiment, Si implantation conditions can be determined irrespective of the gate length. Therefore, there is an advantage that the degree of freedom when used in various LSIs is large.

In the above description of the first and second embodiments, the first ion species of the ion implantation for amorphization is
Although the case of Si ions has been described, it is needless to say that Ge, Ar or the like may be used, and other ions may be used as long as they do not ultimately affect the electrical characteristics.

Furthermore, in the above-described first step for forming an amorphous layer, ions of the same kind may be formed at a predetermined depth by implanting ions of the same type in multiple stages and at different implantation energies. . Needless to say, ion implantation may be performed in multiple stages using a plurality of ion species. By performing ion implantation while changing the implantation energy in multiple stages, the present invention can also be applied to applications in which the amorphous layer 5 is formed over the entire region from the semiconductor surface to a considerably deep range.

BF ₂ is used as a second ion species for forming a junction.
However, in the case of a P ⁺ N junction, other ions such as B may be used. In the case of an N ⁺ P junction, ions such as As and P may be used.

Furthermore, although the case where lamp annealing is used as the heat treatment means has been described, it goes without saying that other annealing methods, for example, electric furnace annealing, electron beam annealing, laser annealing and the like may be used.

〔The invention's effect〕

As described above, according to the method of manufacturing a semiconductor device of the present invention, since the amorphous state is deeply amorphized even immediately below the gate electrode, channeling at the time of ion implantation and diffusion at the time of annealing can be suppressed. A bond can be formed.

Further, since crystal defects formed near the interface between the original amorphous layer and the single crystal are formed deep enough to prevent the depletion layer from reaching, there is an advantage that a junction having good diode characteristics can be obtained. .

Further, since the crystal defect layer is not present in a portion to be a channel region, there is no deterioration in MOSFET characteristics, and
を 持 つ Fine, with extremely shallow source and drain junctions
MOSFET can be manufactured.

[Brief description of the drawings]

FIGS. 1A to 1E are schematic sectional structural views for explaining a method of manufacturing a semiconductor device as a first embodiment of the present invention, wherein FIG. 1A shows a field oxide film 2 and a gate. After the oxide film 3 is formed, a process chart for forming a (low-resistance polycrystalline silicon) gate electrode 4, (b) is a process chart for forming an amorphous layer 5 by Si ion implantation, and (c) is a BF ₂ ion implantation. FIG. 4D is a process diagram of forming the P ⁺ layer 6, FIG. 4D is a process diagram of recrystallizing the amorphous layer 5 by heat treatment, and FIG. 4E is a process diagram of forming the Al electrode 9 after forming the interlayer insulating film 8. is there. FIG. 2 shows the relationship between the depth of the amorphous layer 5 and the implantation energy of Si in the first embodiment of the present invention. FIG. 3 shows the P ⁺ layer 6 in the first embodiment of the present invention. B at
FIG. 4 is a diagram showing the concentration distribution in the depth direction of FIG. 4, FIG. 4 is a sectional structural view of a MOSFET formed by a method of manufacturing a semiconductor device according to a first embodiment of the present invention, and FIGS. FIG. 7E is a schematic cross-sectional structure diagram for explaining a method of manufacturing a semiconductor device according to a second embodiment of the present invention. FIG. (B) is a process chart for forming an amorphous layer 5 by Si ion implantation, and (c) is a P ⁺ layer 6 formed by BF ₂ ion implantation. FIG. 4D is a process diagram for recrystallizing the amorphous layer 5 by heat treatment, and FIG. 5E is a process diagram for forming an Al electrode 9 after forming the interlayer insulating film 8. DESCRIPTION OF SYMBOLS 1 ... N-type Si substrate 2 ... Field oxide film 3 ... Gate oxide film 4 ... (Low resistance polycrystalline silicon) Gate electrode 5 ... Amorphous layer 6 ... P ⁺ layer (for source or drain) 6-1 P ⁺ layer (for source) 6-2 P ⁺ layer 7 (for drain) Crystal defects (accompanied by ion implantation for forming an amorphous layer) 8 Interlayer insulating film 9 …… Al electrode 10 …… Depletion layer edge

Claims (2)

(57) [Claims] In a manufacturing process of a field-effect transistor, after a gate electrode is formed, inactive first ions that do not affect electric characteristics of a semiconductor are ion-implanted to form a source region.
A first step of forming an amorphous layer in a region to be a drain region and a region to be a channel region below a gate electrode; and a second step of ion-implanting second electrically active ions. And a third step of performing a heat treatment for activating the impurity introduced by the second ion implantation and recrystallizing the amorphous layer. A depletion layer in which the depth of crystal defects generated when the amorphous layer is recrystallized is expanded from the source region and the drain region of the field effect transistor into the layer where the amorphous layer is recrystallized. Out of the deeper portion, and to amorphize all the regions to be channel regions immediately below the gate electrode due to the lateral spread of the ions implanted in the first step. ,Before The method of manufacturing a semiconductor device characterized by comprising the step of forming by selecting the gate length of the implant energy and implant dose and the gate electrode of the ion implantation in the first step. 2. A method of manufacturing a field effect transistor, comprising the steps of: after forming a gate electrode, ion-implanting inactive first ions which do not affect the electrical characteristics of the semiconductor;
A first step of forming an amorphous layer in a region to be a drain region and a region to be a channel region below a gate electrode; and a second step of ion-implanting second electrically active ions. And a third step of performing a heat treatment for activating the impurity introduced by the second ion implantation and recrystallizing the amorphous layer. A depletion layer in which the depth of crystal defects generated when the amorphous layer is recrystallized is expanded from the source region and the drain region of the field effect transistor into the layer where the amorphous layer is recrystallized. Of the ion implantation in the first step, in order to form a region deeper than the deeper one and to amorphize all the regions to be channel regions directly below the gate electrode through the gate electrode. The method of manufacturing a semiconductor device characterized by comprising the step of forming by selecting the thickness of Iriryou and the gate electrode.