JPH0434942A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To accurately control an impurity concentration distribution and to suppress an increase in a leakage current by forming a gate oxide film on one conductivity type semiconductor substrate, forming an amorphous layer by ion implanting, and injecting one conductivity type impurity to a boundary between the amorphous layer and a crystalline region. CONSTITUTION:A field oxide film 2 is formed on a P-type silicon substrate 1, and a gate oxide film 3 is formed. Ge ions are implanted to form an amorphous silicon layer 4. B ions are implanted to form a P<+> type buried layer 5, and a P-type channel layer 6 is formed. A gate electrode 7 made of polysilicon is formed, and P-type ions are implanted to form an N-type low concentration layer 8 of an LDD structure. An insulating film made of PSG is deposited on the entire surface, and etched back to form a sidewall 9 made of PSG. P-type ions are implanted to form N<+> type source.drain 10. They are simultaneously heat treated. It is lamp-annealed for a short time. An interlayer insulating film is deposited, a contact hole is opened, and a metal wiring layer is formed to complete a device.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming a MOS device.

[Conventional technology]

Currently, impurity introduction in MOS device formation is mainly performed by ion implantation.

With the miniaturization of device patterns, the depth of source-drain junctions has become shallower, but with normal ion implantation, a tail occurs due to channeling, making it impossible to reduce the depth of the junctions.

As a way to deal with this, a double injection method is used, for example, C, M
, LIM et a! , by IEEE Electr
on Device Letters, vol, 9.
no, 11.1989. Published in pp. 594.

This method involves forming an amorphous layer in advance by implanting silicon ions, and then implanting ions to serve as carriers.

[Problem to be solved by the invention]

When double implantation is performed in the source-train formation process, there is a problem in that leakage current increases at the junction.

Furthermore, when ions are implanted into a single crystal layer, the ions spread laterally, and as miniaturization progresses, this effect can no longer be ignored.

Furthermore, in forming a low impurity concentration layer for the LDD ellipse of a MOSFET, it is difficult to form a shallow junction due to channeling components.

An object of the present invention is to provide a method for manufacturing a semiconductor device 1 that controls impurity concentration distribution with high precision and suppresses an increase in leakage current.

[Means to solve the problem]

The method for manufacturing a semiconductor device of the present invention includes the steps of: forming a gate oxide film on the surface of a semiconductor substrate of one conductivity type, and then forming an amorphous layer on the surface of the semiconductor substrate by ion implantation; A step of introducing an impurity of one conductivity type into the interface between the semiconductor substrate and the single crystal region of the semiconductor substrate, a step of forming a gate electrode made of polysilicon, and then a step of forming a side wall made of an insulator, and a step of forming a side wall made of an insulator, The process includes an annealing process.

[Operation] First, a group 4 element is ion-implanted into the entire surface of a P-type silicon substrate on which a field oxide film and a gate oxide film have been formed to make it amorphous.

Here, the depletion layer is prevented from reaching the boundary of the amorphous layer.

The critical implantation dose is 1.times.10.sup.14/cm.sup.2, so there is no risk of deterioration of the gate oxide film.

Next, ion implantation for the channel, LDD, and source-drain is performed, so the problem of decreased activation rate in the low dose (implantation amount) region is solved.

Furthermore, since the region into which impurities are introduced is amorphous, channeling does not occur when impurities are introduced through a mask, and tail problems and lateral spread can be reduced.

Since heat treatment is performed all at once after all ion implantations are completed, redistribution of impurities is also reduced.

〔Example〕

An embodiment of the present invention will be described with reference to FIGS. 1(a) to (C).

First, as shown in FIG. 1(a), a field oxide film 2 with a thickness of 800 nm is formed on a P-type silicon substrate 1 by the LOCO8 method, and a gate oxide film 3 with a thickness of 7 nm is formed by thermal oxidation.

Next, Ge ions are implanted at IXl014/cm2 at 150 keV and 110 keV to form an amorphous silicon layer 4.

Next, B ions are implanted at 110 keV to a depth of 1X10''7 cm2 to form a P+ type buried layer 5.

Next, B ions are applied at 30 keV to lX10"lXl013
/am2 is implanted to form a P-type channel layer 6.

Next, as shown in FIG. 1(b), a gate electrode 7 made of polysilicon is formed, and P ions are irradiated with 1X at 4°keV.
The LDD structure (7
) An N-type low concentration layer 8 is formed.

Next, as shown in FIG. 1(c), an insulating film made of PSG is deposited on the entire surface, and etched back by RIE method.
A sidewall 9 made of SG is formed.

Next, P ions are implanted at 5.times.10"/c.sub.2 at 70 keV to form an N+ type source-drain 10.

After the ion implantation is completed, a heat treatment is performed to recrystallize the amorphous layer 4 and at the same time activate the impurity layer.

Here, short-time lamp annealing was performed at 900 to 1000°C for 2 to 30 seconds.

After that, an interlayer insulating film is deposited, contact holes are opened, and metal wiring layers are formed to complete the device.

In this example, Ge ions were used to form the amorphous silicon layer 4, but group 4 ions such as Si ions and Sn ions may also be used. less and more effective.

In this embodiment, after forming the amorphous silicon layer 4,
Although the "" type buried layer 5 is formed and the P type channel layer 6 is formed, this order can also be changed.

〔Effect of the invention〕

Since the region into which impurities are introduced is amorphous, no tail due to channeling was observed in the channel layer and source-drain layer.

By lowering the acceleration energy during ion implantation,
An even shallower impurity layer can be formed.

It was found that channeling components are eliminated and the lateral inward spread of impurities is reduced, making it effective for forming fine pattern devices.

It was found that the activation rate in the low concentration layer was also improved and a value close to 100% was obtained.

[Brief explanation of drawings]

FIGS. 1(a) to 1(C) are cross-sectional views showing one embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... P-type silicon substrate, 2... Field oxide film, 3... Gate oxide film, 4... Amorphous silicon layer,
5...P+ type buried layer, 6...P type channel layer, 7.
...Gate electrode, 8...N type low concentration layer, 9... Side wall, 10... N+ type source-drain.

Claims (1)

[Claims] After forming a gate oxide film on the surface of a semiconductor substrate of one conductivity type, forming an amorphous layer on the surface of the semiconductor substrate by ion implantation, and connecting the amorphous layer and the single crystal region of the semiconductor substrate. The process includes a step of introducing impurities of one conductivity type into the interface, a step of forming a gate electrode made of polysilicon and then forming a sidewall made of an insulator, and a step of heat-treating after the completion of the three steps. A method for manufacturing a featured semiconductor device.