JP3525464B2 - Semiconductor device and method of manufacturing semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its manufacturing method.

[0002]

2. Description of the Related Art Conventionally, in a MOS transistor on a silicon substrate, for example, in the case of an n-ch transistor, a gate electrode is formed on a p-type substrate, and an n-type impurity is introduced by ion implantation using the gate electrode as a mask. By forming the source / drain regions. A method of forming an n-ch transistor will be described with reference to FIG.

In FIG. 7A, a gate electrode 2 is formed after an element isolation film 3 is formed on a p-type silicon substrate 1. Figure 7 (b)
Then, using the gate electrode 2 as a mask on the p-type substrate 1,
The source / drain forming n-type impurity is, for example, As of 30 Ke.
Introduced by ion implantation 4 under the conditions of V, 5E15 atoms / cm ² ,
The n-type impurity layer 5 is formed. In FIG. 7C, for activation of the source / drain forming impurities, for example, 900 ° C., 100 ° C.
Heat treatment 7 is performed in minutes. At this time, the source / drain forming impurities diffuse 8 during the heat treatment 7
The drain region 6 expands, and the junction depth (Xj) with the substrate becomes deep from about 0.05 μm to about 0.3 μm immediately after the implantation. Also, p-
The ch transistor is composed of p-type source / drain forming impurities on an n-type substrate. In the p-ch transistor, Xj becomes about 0.5 μm after the heat treatment.

By the way, with the progress of miniaturization of devices, a problem such as so-called short channel effect has occurred. One of the causes of the short channel effect is that the depletion layers formed near the source and the drain approach each other and are connected.

In recent years, as a method for suppressing the short channel effect and forming a fine transistor, a source / drain forming impurity is shallowly introduced into the substrate surface by low energy ion implantation, or a source / drain forming impurity is formed. By adopting a short heat treatment for activation, diffusion of the source / drain forming impurities during the heat treatment is suppressed, and the source / drain regions are formed extremely shallow on the substrate surface.

A method by low energy ion implantation will be described with reference to FIGS. 8 (a) and 8 (b), and a forming method by heat treatment at a low temperature for a short time will be described with reference to FIGS. 8 (c) and 8 (d). To do.

In FIG. 8A, a gate electrode 2 is formed after forming an element isolation film 3 on a p-type silicon substrate 1. Low energy n is applied to the p-type substrate 1 by using the gate electrode 2 as a mask.
Type impurity implantation 9 is performed under the conditions of, for example, As of 5 KeV and 5E15 atoms / cm2 to form an n-type ultra-shallow impurity layer 10,
The Xj is about 0.01 μm. In FIG. 8B, the substrate 1 is
A shallow n-type source with a Xj of 0.2um after heat treatment of
The drain region 11 is formed.

In FIG. 8C, source / drain n-type impurity implantation 4 is performed using the gate electrode 2 formed on the p-type substrate 1 as a mask to form an n-type impurity layer 5. Figure 8 (d)
Then, the substrate 1 is subjected to the heat treatment 50 for a short time such as 1000 ° C. for 10 seconds. Due to the heat treatment for a short time, the n-type impurities hardly diffuse and the shallow n-type source / drain regions 12 having Xj of 0.1 μm or less are formed.

As described above, the short channel effect is suppressed by performing the ion implantation for forming the source / drain with low acceleration energy or by performing the heat treatment in a short time, and a fine element can be formed.

[0010]

However, in these methods, since the source / drain regions are not widened,
The concentration distribution of the source / drain forming impurities becomes steep from the peak position to the junction position with the substrate.
Therefore, since the concentrations of the source / drain forming impurities and the impurities in the substrate are high in the vicinity of the junction and the gradient is steep, the leakage current generated at the junction is much higher than that of the conventional transistor. The problem arises that

In an actual device, it is necessary to reduce power consumption during standby as much as possible. When the conventional transistor was used, the current due to junction leakage was about 0.1% with respect to the total standby current, but when the transistor having the shallow source / drain region was used, It reaches about 5%. Thus, in order to suppress the short channel effect, when the source / drain regions are shallowly formed on the substrate surface by shortening the time under the heat treatment condition, the leakage current generated at the junction with the substrate is suddenly increased. There was a problem that it would increase.

Therefore, an object of the present invention is to provide a fine MOS type transistor in which a source / drain region is formed on a silicon substrate extremely shallowly with respect to the substrate surface, while suppressing the short channel effect while suppressing the short channel effect. It is an object of the present invention to provide a method for manufacturing a semiconductor device that reduces junction leakage between the bottom and the substrate.

[0013]

In view of the above problems, the method of manufacturing a semiconductor device according to the present invention suppresses the short channel effect even if the source / drain regions of a fine MOS transistor are shallowly formed on the substrate surface. The present invention provides a method for manufacturing a semiconductor device in which a leak current at a junction with a substrate is suppressed. As a configuration for this, a step (a) of forming a gate electrode on a gate insulating film formed in a portion to be a MOS type transistor region on the surface of the one conductivity type semiconductor substrate,
A step (b) of forming a first impurity layer by ion-implanting the semiconductor substrate and a first impurity of the other conductivity type with the gate electrode as a mask; and the first electrode with the gate electrode as a mask. Same conductivity type as impurities but different ionic species
Comprising second impurity by ion implantation, and (c) forming a second impurity layer of said first lower concentration than the in the bottom first impurity layer of the impurity layer, the step (b) And before
After the step (c), the substrate is heat-treated for a short time,
Seo and activating the first impurity and the second impurity
And a step (d) of forming the over scan and drain regions, by the step (d), only the bottom of the source and drain regions, forming a low concentration impurity region formed of the second impurity Characterize.

The above method for manufacturing a semiconductor device includes the steps described above.
A step of forming a sidewall insulating film on the side surface of the gate electrode after the step (a) and before the step (b);
Then, the gate electrode on which the sidewall insulating film is formed is masked.
As a mask, ion-implanting the first impurity,
In (c), the gate electrode having the sidewall insulating film is formed.
Said second impurity poles as a mask, wherein the this <br/> ion implantation.

[0015]

In view of the above problems, the first semiconductor device of the present invention suppresses the short channel effect and suppresses the short channel effect even if the source / drain regions of a fine MOS transistor are shallowly formed on the substrate surface. The present invention provides a semiconductor device in which leakage current in the device is suppressed. As a structure for this, a gate electrode formed in a portion to be a MOS type transistor region on the surface of one conductivity type semiconductor substrate, and the substrate and the first impurity of the other conductivity type formed on the semiconductor substrate are mainly used.
And the high concentration source and drain regions of which is an impurity that, the formed only on the source-drain region bottom, said source and drain regions and different from that of the first impurity in the same conductive type
And a low-concentration impurity region made of the second impurity . In this first semiconductor device,
The impurity region is the entire bottom of the source / drain region.
Is formed in.

In the first semiconductor device, the sidewall insulating film formed on the side surface of the gate electrode and the semiconductor
An element isolation film formed on the substrate,
The rain region is a gate electrode on which the sidewall insulating film is formed.
And the element isolation film is formed in a self-aligned manner . Further, the impurity region is
Gate electrode having a sidewall insulating film and the device isolation film
Is formed in a self-aligned manner. Also, the first
And the second impurity is phosphorus.
It

In view of the above problems, the second semiconductor device of the present invention suppresses the short channel effect and suppresses the junction with the substrate even if the source / drain regions of the fine MOS transistor are shallowly formed on the substrate surface. Provided is a semiconductor device in which leakage current in a part is suppressed. As a configuration for this,
A gate electrode formed in a portion to be a MOS transistor region on the surface of one conductivity type semiconductor substrate and a first impurity of the conductivity type and the other conductivity type formed on the semiconductor substrate
High concentration source / drain regions, which are the main impurities ,
With respect to the source / drain region, the first impurity having the same conductivity type as the source / drain is formed in a region other than the substrate surface.
The structure is characterized by having a low-concentration impurity region made of a second impurity different from the object . In the second semiconductor device, the impurity region is formed at a position deeper than the substrate surface by 0.05 μm or more. In addition, the first impurity
Is arsenic and the second impurity is phosphorus.

[0019]

The method of manufacturing a semiconductor device according to the present invention, shallow form source and drain regions to the substrate, strike the producing fine MOS transistor for the purpose of suppressing the short channel effect, the source .Of the drain region
By forming a low-concentration impurity region only at the bottom,
Thus, it becomes possible to suppress the leak current at the junction between the bottom of the source / drain region and the substrate.

[0020] The semiconductor device according to the present invention, the source and drain regions in order to suppress the short channel effect and shallow with respect to the substrate, low formed only on the bottom of the source and drain regions in the fine MOS transistor Dark
It is possible to suppress the leak current at the junction between the bottom of the source / drain region and the substrate by using the impurity region at various times .

[0021]

EXAMPLES As an example of a method for manufacturing a semiconductor device of the present invention, when a fine n-ch transistor is formed by forming source / drain regions shallowly on the substrate surface on a p-type substrate, A manufacturing method for suppressing junction leak between the bottom of the drain region and the substrate will be described with reference to the drawings.

FIG. 1 is a process sectional view of an embodiment of the present invention. In FIG. 1A, a device isolation film 3 is formed on a p-type silicon substrate 1.
After forming, the gate electrode 2 is formed. Using the gate electrode 2 as a mask on the p-type substrate 1, for example, As, 30 KeV, 5E15ato
The source / drain n-type impurity implantation 4 of ms / cm 2 forms the n-type impurity layer 5 with Xj of about 0.05 μm.

In FIG. 1B, the n-type impurity implantation 14 is performed under the conditions of, for example, P, 40 KeV, 2E12 atoms / cm2 using the gate electrode 2 as a mask as in the case of the source / drain n-type impurity implantation 4. The low-concentration n-type impurity layer 51 is formed only on the bottom of the type impurity layer 5. In FIG. 1 (c), for example, 1
A short-time heat treatment 50 at 000 ° C. for about 10 seconds is performed to activate the n-type impurities and form the n-type source / drain regions 6. In this n-type source / drain region 6, the n-type impurity distribution at the bottom does not become steep.

As described above, according to this embodiment, in the method of forming the source / drain regions shallowly with respect to the substrate surface in order to miniaturize the element, the source / drain formation is performed only on the bottoms of the source / drain regions. A junction leak can be suppressed by introducing an impurity having the same conductivity as the impurity.

As an example of the method for manufacturing a semiconductor device of the present invention , in the case where a fine n-ch transistor is formed by forming a source / drain region shallowly on the surface of a p-type substrate, the source / drain is formed. A manufacturing method for suppressing the junction leak between the bottom of the region and the substrate will be described with reference to the drawings.

2A to 2D are process sectional views of an embodiment of the present invention. In FIG. 2A, the device isolation film 3 is formed on the p-type silicon substrate 1.
After forming, the gate electrode 2 and the gate sidewall insulating film 53 are formed. Using the gate electrode 2 as a mask on the p-type substrate 1, an n-type impurity layer 5 with Xj of about 0.05 um is formed by n-type impurity implantation 4 for source / drain such as As, 30 KeV, 5E15 atoms / cm 2.

In FIG. 2B, the gate electrode 2 having the side wall insulating film 53 is the same as the n-type impurity implantation 4 for the source / drain.
Is used as a mask, and n-type impurity implantation 14 is performed under the conditions of P, 40 KeV, 2E12 atoms / cm2, and the n-type impurity layer 5 is formed.
A low-concentration n-type impurity layer 51 is formed only on the bottom of the. In FIG. 2C, the n-type impurities are activated by heat treatment at 1000 ° C. for a short time of about 10 seconds to form the n-type source / drain regions 6. In this n-type source / drain region 6, the n-type impurity distribution at the bottom does not become steep.

As described above, according to this embodiment, in the method of forming the source / drain regions shallowly with respect to the substrate surface in order to miniaturize the device, the source / drain formation is performed only on the bottom of the source / drain regions. Junction leakage can be suppressed by introducing an impurity having the same conductivity as the impurity by ion implantation using the gate electrode having the sidewall insulating film as a mask.

As an example of a method for manufacturing a semiconductor device of the present invention , a source / drain is formed in a p-type substrate by forming source / drain regions shallowly on the substrate surface to form a fine n-ch transistor. A manufacturing method for suppressing the junction leak between the bottom of the region and the substrate will be described with reference to the drawings.

5A to 5C are sectional views showing steps in an embodiment of the present invention. In FIG. 5A, the device isolation film 3 is formed on the p-type silicon substrate 1.
After forming, the gate electrode 2 and the gate sidewall insulating film 53 are formed. Using the gate electrode 2 as a mask on the p-type substrate 1, an n-type impurity layer 5 with Xj of about 0.05 um is formed by n-type impurity implantation 4 for source / drain such as As, 30 KeV, 5E15 atoms / cm 2.

In FIG. 5B, similarly to the n-type impurity implantation 4 for the source / drain, using the gate electrode 2 as a mask, the n-type impurity implantation 14 is performed under the conditions of P, 40 KeV, 2E12 atoms / cm 2, for example. A low-concentration n-type impurity layer 51 is formed in a region of the type impurity layer 5 excluding the substrate surface. At this time, the low-concentration impurity layer 51 has a concentration peak position of the source
Located at the bottom of the n-type impurity layer 5 for drain, from the substrate surface
The concentration up to 0.05 um is about 0 compared to the concentration of the n-type impurity layer 5 .
It will be about 01%.

In FIG. 5C, a short-time heat treatment 50 is performed at 1000 ° C. for about 10 seconds to activate the n-type impurities and form the n-type source / drain regions 6. This n-type source
In the drain region 6, the bottom n-type impurity distribution does not become steep.

As described above, according to this embodiment, in order to miniaturize the device, in the method of forming the source / drain regions shallowly with respect to the substrate surface, the surface of the source / drain region with respect to the substrate is formed. Junction leakage can be suppressed by introducing an impurity having the same conductivity as the source / drain forming impurities into the excluded region.

As an embodiment of the semiconductor device of the present invention , an n-ch transistor formed on a p-type substrate in which a junction leak between the bottom of the source / drain region and the substrate is suppressed will be described with reference to the drawings. .

FIG. 3 is a sectional view of an embodiment of the present invention. 1
Is a p-type substrate, 2 is a gate electrode, 3 is an element isolation, 6 is a shallow n-type source / drain region, and 51 is a low concentration n-type impurity region. Due to the low concentration n-type impurity region 51 , the concentration distribution of the n-type impurity does not become steep at the bottom of the source / drain region. As described above, according to the present embodiment, in the miniaturization of the device, in the device in which the source / drain region is formed shallowly with respect to the substrate surface, the source / drain forming impurities are formed only in the bottom of the source / drain region. By forming the impurity layers having the same conductivity, the junction leak can be suppressed.

As an example of a semiconductor device of the present invention , an n-ch transistor formed on a p-type substrate in which a junction leak between the bottom of the source / drain region and the substrate is suppressed will be described with reference to the drawings. .

FIG. 4 is a sectional view of an embodiment of the present invention. 1
Is a p-type substrate, 2 is a gate electrode, 3 is element isolation, 6 is a shallow n-type source / drain region, 53 is a gate sidewall insulating film,
Reference numeral 51 indicates a low concentration n-type impurity region. The low concentration n-type impurity region 51 causes n at the bottom of the source / drain region.
The concentration distribution of the type impurities does not become steep. As mentioned above,
According to this embodiment, in the miniaturization of the device, in the device in which the source / drain regions are formed shallowly with respect to the substrate surface, the impurity having the same conductivity as the source / drain forming impurities is formed only in the bottom of the source / drain regions. By forming the layer, the junction leak can be suppressed.

As an embodiment of the semiconductor device of the present invention , an n-ch transistor formed on a p-type substrate in which a junction leak between the bottom of the source / drain region and the substrate is suppressed will be described with reference to the drawings. .

FIG. 6 is a sectional view of an embodiment of the present invention. 1
Is a p-type substrate, 2 is a gate electrode, 3 is an element isolation, 6 is a shallow n-type source / drain region, and 51 is a low concentration n-type impurity region. The low-concentration n-type impurity region 51 is formed at a position deeper than 0.05 um deeper than the substrate surface, so that the concentration distribution of the n-type impurity does not become steep at the bottom of the source / drain region. As described above, according to the present embodiment, in the miniaturization of the device, in the device in which the source / drain region is formed shallowly with respect to the substrate surface, the source / drain forming impurities are formed only in the bottom of the source / drain region. By forming the impurity layers having the same conductivity, the junction leak can be suppressed.

As the n-type impurities, As, P, S
The same effect can be obtained by using b.

Further, in the above embodiment, the p-c is formed on the n-type substrate.
The same effect can be obtained when the h transistor is formed.

[0042]

As described above, according to the present invention, in the MOS type transistor in which the source / drain regions are formed extremely shallow on the substrate surface, the short channel effect is suppressed and the junction leak between the bottom of the source / drain region and the substrate is suppressed. It can be suppressed.

[Brief description of drawings]

FIG. 1 is a process sectional view of a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a process sectional view of a method for manufacturing a semiconductor device according to a second embodiment of the present invention.

FIG. 3 is a sectional view of a semiconductor device according to a third embodiment of the present invention.

FIG. 4 is a sectional view of a semiconductor device according to a fourth embodiment of the present invention.

FIG. 5 is a process sectional view of a method for manufacturing a semiconductor device according to a fifth embodiment of the present invention.

FIG. 6 is a sectional view of a semiconductor device according to a sixth embodiment of the present invention.

FIG. 7 is a process sectional view of a method for manufacturing a semiconductor device according to a first conventional example of the present invention.

FIG. 8 is a process sectional view of a method for manufacturing a semiconductor device according to a second conventional example of the present invention.

[Explanation of symbols]

1 p-type substrate 6 Source / Drain 51 Low concentration impurity layer

Claims (12)

(57) [Claims] 1. A step (a) of forming a gate electrode on a gate insulating film formed in a portion to be a MOS transistor region on the surface of a conductive type semiconductor substrate, and the semiconductor substrate and the other side using the gate electrode as a mask. A step (b) of forming a first impurity layer by introducing a first impurity of a conductive type by ion implantation; and using the gate electrode as a mask, a first conductive layer of the same conductive type as the first impurity but having a different ion species Ion-implanting the second impurity to form a second impurity layer having a lower concentration than that of the first impurity layer at the bottom of the first impurity layer (c)
And (d), after the steps (b) and (c), heat-treating the substrate for a short time to activate the first impurities and the second impurities to form source / drain regions. And a low-concentration impurity region made of the second impurity is formed only on the bottom of the source / drain region by the step (d). 2. A step of forming a sidewall insulating film on the side surface of the gate electrode after the step (a) and before the step (b), wherein in the step (b), the sidewall insulating film is formed. Ion-implanting the first impurity using the formed gate electrode as a mask, and in the step (c), ion-implanting the second impurity using the gate electrode having the sidewall insulating film formed as a mask. The method for manufacturing a semiconductor device according to claim 1, wherein 3. In the step (c), the second impurity layer is formed such that the peak position of the impurity concentration is located at the bottom of the first impurity layer. 2. The method for manufacturing a semiconductor device according to 2. 4. The first impurity is arsenic, and the second impurity is phosphorus.
The method for manufacturing a semiconductor device according to any one of the above. 5. A gate electrode formed in a portion to be a MOS transistor region on the surface of one conductivity type semiconductor substrate, and a main impurity formed mainly on the substrate and the other impurity of the other conductivity type formed on the semiconductor substrate. A low-concentration impurity region formed of only a high-concentration source / drain region and a second impurity that is formed only in the bottom of the source / drain region and has the same conductivity type as the source / drain region and different from the first impurity. A semiconductor device comprising: 6. The semiconductor device according to claim 5, wherein the impurity region is formed on the entire bottom of the source / drain region. 7. A sidewall insulating film formed on a side surface of the gate electrode, and an element isolation film formed on the semiconductor substrate, wherein the source / drain regions have a gate formed with the sidewall insulating film. 7. The semiconductor device according to claim 5, wherein the semiconductor device is formed in self-alignment with the electrodes and the element isolation film. 8. The semiconductor device according to claim 7, wherein the impurity region is formed in a self-aligned manner with respect to the gate electrode on which the sidewall insulating film is formed and the element isolation film. 9. The method according to claim 5, wherein the first impurity is arsenic and the second impurity is phosphorus.
The semiconductor device according to claim 1 . 10. A gate electrode formed on a portion to be a MOS transistor region on the surface of one conductivity type semiconductor substrate, and a main impurity formed mainly on the substrate and the other impurity of the other conductivity type formed on the semiconductor substrate. A low concentration of a certain high concentration source / drain region and a second impurity of the same conductivity type as the source / drain but different from the first impurity in a region other than the substrate surface with respect to the source / drain region. A semiconductor device having an impurity region. 11. The impurity region has a depth of 0.
The semiconductor device according to claim 10, wherein the semiconductor device is formed at a position deeper than 05 μm. 12. The first impurity is arsenic, and the second impurity is phosphorus.
Alternatively, the semiconductor device according to item 11 .