JP2827905B2 - MISFET and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure and a method of manufacturing a semiconductor device, and more particularly to a MISFET and a method of manufacturing the same.

[0002]

2. Description of the Related Art A very general method of manufacturing a MISFET will be described with reference to FIG. 8 taking a silicon (Si) n-channel device as an example. After forming an isolation insulating film for separating each element on a Si substrate by a LOCOS method or the like, the threshold voltage V _{TH of the} FET is set to a desired value, and the short channel effect and punch-through are suppressed. Working p
Boron, a type impurity, is introduced into the substrate by ion implantation.
Since this step determines the characteristics of the channel of the device, it is referred to herein as channel ion implantation. Next, after sequentially forming a gate oxide film and a gate electrode on the substrate surface,
A gate electrode having a desired shape is formed by photolithography and etching. Next, arsenic of an n-type impurity is introduced into the substrate by ion implantation using the gate electrode as a mask, thereby forming a source / drain in a self-aligned manner with the gate electrode. Thereafter, it is necessary to perform heat treatment at a high temperature (at least 800 degrees in the case of a Si substrate) at least once. As a result, the ion-implanted impurity is settled at the crystal lattice position and becomes electrically active.

In the above-mentioned manufacturing method, the source / drain implantation introduces a large amount of ions (10 ¹⁵ cm ⁻² or more), so that the crystal structure of the Si substrate is destroyed and a large number of point defects (at locations that are not originally lattice sites) In addition, “interstitial atoms” in which atoms exist and “vacancies” in which atoms in lattice positions are missing are generated. The existence of such point defects causes thermal diffusion of impurity atoms. In particular, boron (B) and phosphorus (P) are extremely easy to diffuse when paired with interstitial atoms (enhanced diffusion).
Therefore, in the above example, in the heat treatment step for activating the impurities of the source and the drain, boron previously introduced into the substrate forms a pair with the point defect generated at the time of the source and the drain implantation, and for a very short time. (Less than 1 second), it moves largely within the substrate. This enhanced diffusion is hardly controllable even if the temperature and time of the heat treatment are adjusted, and makes it difficult to design a substrate impurity distribution for obtaining desired device characteristics. For example, in a fine MISFET, there is a design requirement to reduce V _TH while suppressing the short channel effect. For this purpose, suppressing the short channel effect by disposing the peak of boron slightly deep portion of the substrate, whereas the vicinity of the substrate surface may be lowered to V _TH as low concentrations. Such a distribution can be realized by adjusting the energy and dose of boron ion implantation. However, such a distribution device designer's intention, when the subsequent heat treatment, collapses by uncontrolled enhanced diffusion described above, the completed device is unintentionally, V _TH is high, the short channel effect Will be larger. FIG. 9 shows an example of the characteristics of a device whose V _TH has been increased by such a phenomenon (dependence of the deviation of a V _{TH from} a long channel device on the channel length). Since the above-mentioned enhanced diffusion is caused by point defects generated in the source / drain regions,
Distance of the source and the drain is short, the more short-channel device mate adding the effects of both V _TH is greatly increased (this phenomenon is called reverse short channel effect). In a practically important short channel device, V _TH becomes higher than a desired value (approximately equal to V _TH at an infinite channel length).
In addition, the degree of the increase reflects the lack of controllability of the accelerated diffusion, and it is a serious problem that the degree of the increase varies due to a slight change in the process. In addition, the enhanced diffusion lowers the impurity concentration in a deep portion of the substrate, so that the short channel effect is also deteriorated. For this reason, the short channel effect of the element actually obtained is always worse than the result of the simulation performed without the accelerated diffusion.

On the other hand, a method of reducing the parasitic capacitance between the source / drain and the substrate by changing the general manufacturing method shown in FIG. 8 has been proposed in Japanese Patent Laid-Open No. 4-286364. This method will be described with reference to FIG. A feature of this method is that channel ion implantation which is usually performed before forming a gate electrode is performed after forming a gate electrode. That is, in the example of FIG. 10, after forming the gate electrode, boron ions are implanted so as to penetrate the gate electrode and reach the substrate. At this time, in the source / drain region where the gate electrode does not exist, boron is introduced deeper than the region where the channel is formed by the height of the gate electrode. Thereafter, a heat treatment for implanting and activating the source / drain impurities is performed as usual. By using this method, boron implanted with channel ions can be made deeper than the source / drain. For this reason, the concentration of the p-type portion of the substrate in contact with the n-type source / drain is lower than in the case where channel ion implantation is performed by a normal method. As a result, the depletion layer of the pn junction is widened, the parasitic capacitance generated between the source / drain and the substrate is reduced, and the circuit operation is speeded up.

[0005] In the above method, enhanced diffusion is a conventional manufacturing method and problems in the same manner, otherwise, the threshold voltage V _TH
Is difficult to control. This will be described below. The ion implantation has a mountain-shaped distribution in the depth direction. In the channel implantation, the peak of the mountain-shaped distribution is equal to the source / drain depth immediately below the gate electrode (usually 100 to 300 nm) in order to prevent punch-through.
Degree). In channel ion implantation, implantation energy is set so that the range is equal to the sum of the depth in the substrate and the height of the gate electrode. However, the height of the gate electrode (a typical value is 100 to 50)
0 nm), it is inevitable that a variation of 10 to 50 nm occurs in the process. In particular, the film thickness is likely to fluctuate in the etch-back step of diffusing phosphorus into the polysilicon gate and forming the gate side wall. For this reason, the above implantation depth is ±
An uncertainty of 10-50 nm results. As described above, the ion-implanted impurity distribution is mountain-shaped, and has a large concentration gradient in the depth direction on the substrate surface. Therefore, such a change in the depth causes a change in the impurity concentration on the substrate surface, and as a result, V _TH varies. That is, as the impurity depth becomes shallower, the concentration becomes higher and V _TH rises. As an example, boron is injected to penetrate a gate electrode having a thickness of 150 nm and has a peak at 100 nm in the substrate, and V _TH = 0.
When designed to 4V, the gate electrode height deviation is 10nm
V _TH fluctuates by about 50 mV. FIG.
In the normal manufacturing method described in (1), an oxide film (sacrificial oxide film) having a thickness of 10 to 30 nm is provided on the substrate to prevent substrate contamination and channeling. Because the oxide film is originally thin,
The absolute value of the thickness variation is one order of magnitude smaller than that of the gate electrode, which is not a problem.

[0006]

The above-mentioned ordinary MIS
In the method of manufacturing the FET, there is a problem that the channel impurity causes enhanced diffusion due to a point defect generated at the time of source / drain implantation, and it is difficult to control the distribution of the channel impurity.

Further, when channel ion implantation is performed through the gate electrode, there has been a problem that the threshold voltage V _{TH of the} device fluctuates sensitively due to a change in the height of the gate electrode.

[0008]

In order to solve the first problem of enhanced diffusion, channel ion implantation is performed after ion implantation and activation of source / drain impurities. More specifically, after the source / drain ions are implanted into the gate electrode in a self-aligned manner, a heat treatment for activation is performed, and then channel ion implantation is performed through the gate electrode.

When channel ion implantation is performed through the gate electrode as described above, there is a second problem that the threshold value V _TH varies. A similar problem also occurs when channel ion implantation is performed through the gate electrode merely for the purpose of reducing the source / drain parasitic capacitance. In order to solve this, a relatively high concentration impurity region formed by the channel ion implantation has at least two local maximum points.
An element structure having the following . For this purpose, in at least one of the channel ion implantation steps penetrating the gate electrode, the implantation is performed such that the depth peak below the gate is located on the substrate surface.

[0010]

The crystal defects caused by the source / drain ion implantation almost disappear by the subsequent heat treatment for activation. Thus, if channel impurities are subsequently introduced, their diffusion is not affected by point defects. For this reason, the channel impurity distribution can be controlled by the energy or dose of ion implantation, and the impurity distribution as intended by the device designer can be realized.

The operation relating to the variation of the threshold value V _TH due to the thickness of the gate electrode is as follows. First, from the viewpoint of the element structure, the impurity distribution is set to be substantially flat from a partly deep part of the substrate to the surface. This allows
The depth of the overall impurity region does not change the concentration of the surface also varies, variations in the V _TH is suppressed. Further, from the viewpoint of the manufacturing method, in the channel ion implantation step, the implantation is performed at least once so that the peak of the depth below the gate is located on the substrate surface. Thus, the gradient in the depth direction of the impurity concentration on the substrate surface immediately after the ion implantation becomes substantially zero. For this reason, even if the depth of the implantation peak varies somewhat, the change in the surface concentration is small, and the variation in _VTH is suppressed.

[0012]

FIG. 1 shows a case where ion implantation is performed only once.
It is an example . Here, an n-channel element is taken as an example. After forming an element isolation insulating film 6, a gate insulating film 4, and a gate electrode 5 on a silicon substrate 1 (a region of interest is p-type doped by well formation or the like), arsenic (As) is gated. 5 × 10 ¹⁵ cm ^{-2 using} electrode 5 as a mask
The source / drain regions 3A are formed by ion implantation to a certain degree. At this stage, the source / drain region 3A is electrically inactive, the crystal structure is broken around the source / drain region 3A, and a large number of point defects are present (FIG. 1A).

Next, a high-temperature heat treatment (for example,
0 seconds or 850 ° C. for 10 minutes). As a result, the implanted As falls within the lattice position, and the inactive source
The drain region 3A is converted to an electrically active source / drain region 3B. On the other hand, at this time, the point defects flow out of the substrate due to diffusion, and the interstitial atoms and vacancies recombine and almost disappear (FIG. 1B).

Next, boron (B) is ion-implanted at about 10 ¹² to 10 ¹³ cm ⁻² to form a high-concentration channel region 2A (FIG. 1C). At this time, the depth of the peak of the concentration depends on the source / drain region 3B in order to suppress the short channel effect.
Is set to the same depth as the lower end (joining depth). next,
A high-temperature heat treatment is performed again to activate boron in the electrically inactive region 2A. Thus, an electrically active p-type high concentration channel region 2B is formed. At this time, the source
Since the defects caused by the drain implantation no longer exist, the enhanced diffusion of boron is prevented.

In the above example , channel injection was performed only once. In that case, the peak position of boron implanted into the channel is usually selected so as to be substantially equal to the depth of the source and drain below the gate in order to suppress the short channel effect. However, this causes a gradient in the impurity distribution on the substrate surface, and the controllability of the threshold value VTH becomes poor. FIG. 2 shows a method according to the present invention which addresses this point.
This is a first embodiment. 1A and 1B are performed up to the implantation and activation of the source / drain. Then, the gate electrode 5
Immediately below, boron is implanted so that the concentration peak is near the surface of the substrate 1 (FIG. 2A). This injection allows V
TH variation is prevented. Next, boron is implanted again just below the gate electrode 5 so that the concentration peak is near the depth of the source / drain 3 (FIG. 2B). Finally, a high-temperature heat treatment is performed to activate the implanted boron.
As a result, a p-type high-concentration channel region 2B having a substantially uniform concentration distribution in the depth direction is formed.
c). According to the present embodiment, it is possible to prevent accelerated diffusion of impurities in the channel and suppress an increase in variation in _VTH . The order of the first and second boron implantations may be interchanged.

FIGS. 3 and 4 show that the above-described ion implantation is performed once.
FIG. 9 shows typical examples of the distribution of boron in the depth direction of the gate electrode portion in the example of the present invention and the first embodiment . The former is a simulation result immediately after boron implantation, and the latter is a simulation result after boron activation heat treatment. The vertical axis is logarithmic on the left and linear scale on the right. It is assumed that the depth of the source / drain is 100 nm. In the figure, “single-stage implantation” is a case where boron implantation is performed in one stage as in an example in which ion implantation is performed only once , and the peak position of the distribution is set to around 100 nm, which is the same as the source and drain. . This is to suppress the short channel effect. Here B is 7
1.3 × 10 ¹³ cm ^-2 is implanted at 0 keV. Then, in FIG. 3 immediately after the implantation, the concentration gradient is large on the substrate surface. Therefore, the thickness of the gate electrode (design value: 150 nm)
Slightly fluctuates the boron concentration on the substrate surface.

On the other hand, "two-stage implantation" means that boron implantation is performed in two stages as in the first embodiment, and one of them is set so as to have a peak on the substrate surface. The shallower implant sets the threshold, and the deeper implant prevents short channel effects. In this example, boron is 45 ke
4 × 10 ¹² cm ⁻² at V and 9 × 10 ¹² cm ^{−2 at} 80 keV
I'm driving. In this case, the gradient of the impurity concentration on the substrate surface is close to zero. Therefore, even if the thickness of the gate electrode is slightly fluctuated, the threshold value does not change much. When the heat treatment is performed (FIG. 4), boron diffuses out of the substrate, so that the surface concentration in the one-step implantation and the surface concentration in the two-step implantation substantially match. For this reason, both thresholds become equal. When two-stage implantation is performed, the distribution in the depth direction becomes substantially flat, and two peaks remain in the concentration distribution. FIG. 5 is a simulation result of a change in threshold value in the single-stage implantation and the two-stage implantation when the gate electrode thickness changes. For the reasons described above, the threshold value largely fluctuates in the former, but is almost suppressed in the latter.

In the above description, the source / drain depth is 10
It is assumed that the depth is about 0 nm or more. However, when a shallower source / drain is used, even if the second boron implantation is omitted in the first embodiment, the depth is larger than the source / drain depth. It is conceivable that the substrate concentration can be sufficiently increased to a slightly deep position. In this case, by performing only one implantation of boron having a peak on the substrate surface under the gate electrode, it is possible to sufficiently suppress the short channel effect and also suppress the variation of the threshold value VTH. That is, in the first embodiment, the second boron implantation can be omitted. This is shown in FIG. The steps up to the formation of the source / drain 3B are performed in the same manner as in FIGS. Next, boron is implanted through the gate electrode 5 as in FIG. However, the peak position after the implantation is located on the surface of the substrate 1 immediately below the gate electrode 5 (FIG. 6A). Next, the implanted boron is activated by a high-temperature heat treatment (FIG. 6B). In this method, the source / drain 3B is sufficiently shallow (approximately 10
If it is not suppressed, the short channel effect may be deteriorated.

In the above two examples and the first embodiment ,
The figure shows a case where the source / drain region 3 and the high-concentration channel region 2 do not overlap except for a partial region near the channel. This situation is desirable to keep the source / drain parasitic capacitance low. However, the essence of the present invention in these examples and examples is to suppress enhanced diffusion,
And realizing it without variation in threshold value. Therefore, the fact that the two regions do not overlap in these embodiments is not necessarily the essence of the present invention, and they may overlap.

On the other hand, the reduction of the threshold variation according to the present invention is effective only when the purpose is only to reduce the source / drain capacitance and the prevention of the accelerated diffusion is not considered. FIG.
Shows a second embodiment of the present invention in such a case. After forming an element isolation insulating film 6, a gate insulating film 4, and a gate electrode 5 on a silicon substrate 1, boron penetrates the gate electrode, and the peak of the range is
Implantation is performed immediately below the surface of the substrate 1 (FIG. 7).
a). At this time, the source / drain depth and the gate electrode height are set so that the high-concentration channel region 2 is deeper than the source / drain region 3. Next, boron is implanted again just below the gate electrode 5 so that the peak of the range is near the depth of the source / drain (FIG. 7B). Next, arsenic (As) is used as a mask with a gate electrode serving as a mask.
^A source / drain region 3A is formed by ion implantation of about ¹⁵ cm ^-2 (FIG. 7C). Finally, the source / drain 3 and the high-concentration channel region 2 are activated by a high-temperature heat treatment (FIG. 7D).

If the purpose is merely to reduce the parasitic capacitance without considering the enhanced diffusion, the order of the ion implantation is arbitrary. If the source and drain are sufficiently shallow, the second boron implantation can be omitted .
This is the same as the embodiment.

In the above description, an n-channel element is used as an example, but this does not limit the scope of the present invention. p
In the channel element, if the channel impurity boron is replaced by phosphorus (P) and the source / drain impurity arsenic is replaced by boron or boron fluoride (BF ₂ ), and the p-type and the n-type are replaced, the description so far is the same. Applicable. The source / drain structure has the simplest single-drain structure. However, the present invention can be easily applied to various modifications such as an LDD structure in which source / drain implantation is performed in two stages. It is clear.

[0023]

The channel impurity after the activation heat treatment of the source and drain impurity according to the present invention through the gate electrode by ion implantation, to prevent the enhanced diffusion of channel impurities, an increase in abnormal threshold V _TH, V The instability of _{TH and} the increase in the short channel effect due to the decrease in the concentration at the deep part of the base are prevented. Since the unpredictable accelerated diffusion is eliminated, the element characteristics as designed can be easily realized.

The variation in the case, by implanting channel impurity so as to have a peak at the substrate surface under the gate, the threshold V _TH of the device due to variations in the gate electrode thickness through the gate electrode for injecting channel impurity Can be suppressed. As a result, the capacity of the source / drain can be reduced without increasing the V _TH variation.

A band-shaped high-concentration channel impurity region having a substantially flat concentration distribution in the depth direction and a substantially constant width in the depth direction has an upper end in contact with the substrate surface immediately below the gate electrode, and By adopting an element structure in which the high-concentration region does not contact the surface of the substrate in the source / drain region, it is possible to prevent accelerated diffusion or reduce the source / drain capacitance without increasing _VTH variation.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing an example in which ion implantation is performed only once .

FIG. 2 is a sectional view showing a first embodiment according to the present invention.

FIG. 3 shows an example of a substrate impurity distribution immediately after ion implantation .
FIG.

FIG. 4 is a diagram showing an example of a substrate impurity distribution at the time of device completion.
There is .

FIG. 5 is a diagram illustrating the effect of the two-stage injection method.

FIG. 6 is a cross-sectional view showing an example in which ion implantation is performed only once .

FIG. 7 is a sectional view showing a second embodiment according to the present invention.

FIG. 8 is a cross-sectional view showing a general method of manufacturing a conventional MISFET.

FIG. 9 is a diagram showing an example of characteristics of an nMISFET affected by enhanced diffusion.

FIG. 10 shows a conventional MI having reduced source / drain capacitance.
It is sectional drawing which shows the manufacturing method of SFET.

Claims (5)

(57) [Claims] A gate insulating film formed on a semiconductor substrate doped with an impurity of a first conductivity type; a gate electrode formed on the gate insulating film; and both sides of the gate electrode in the semiconductor substrate. A second conductivity type source / drain region formed at
The distribution of the impurity of the first conductivity type includes a band-shaped high concentration region having a substantially constant width in the depth direction and having at least two maximum points, and an upper end of the high concentration region is located immediately below the gate electrode (channel). (Area) in contact with the surface of the substrate,
An MIS transistor, wherein the high-concentration region does not contact the surface of the substrate in the source / drain region. 2. The MIS transistor according to claim 1 , wherein the upper end of the band-shaped high-concentration region is deeper than the source / drain in the source / drain region. 3. A semiconductor substrate of a first conductivity type having a gate electrode formed on a surface thereof with a gate insulating film interposed therebetween, and an impurity of the first conductivity type penetrates the gate electrode immediately below the gate electrode. A first implantation step in which ion implantation is performed so that the surface of the semiconductor substrate coincides with a peak of the impurity distribution after the ion implantation, and a peak penetrating through the gate electrode is deeper than the first implantation step. And a second implantation step of ion-implanting a first conductivity type impurity into the MIS transistor. 4. A source / drain region is formed by ion-implanting a second conductivity type impurity into a semiconductor substrate having a gate electrode formed on a surface thereof via a gate insulating film, using the gate electrode as a mask. And a first implantation in which an impurity of a first conductivity type is ion-implanted through the gate electrode so that a surface of the semiconductor substrate and a peak of the impurity distribution after the ion implantation coincide with each other immediately below the gate electrode. And a second implantation step of ion-implanting impurities of a first conductivity type through the gate electrode so that a peak is deeper than in the first implantation step. A method for manufacturing a transistor. 5. The method according to claim 4, further comprising, after the step of forming the source / drain regions, a heating step for activating impurities in the source / drain regions.