JPH02142189A - Field effect transistor - Google Patents

Abstract

PURPOSE:To provide high breakdown strength by providing an ion implanted layer having the same conductivity type as that of a silicon substrate in a channel region so that said layer is deeper than an ion implanted layer for adjusting a threshold voltage and the depth is about the same as the depth of a source/drain region, and providing an ion implanted layer which is more deeply distributed than the source/drain region. CONSTITUTION:Before a gate oxide film 2 is formed, boron is implanted for adjusting a threshold voltage value, and an ion implanted layer 4 is formed. A part which acts as a gate electrode is made to remain by a photoengraving technology, and etching is performed. With polysilicon 3 as a mask, impurity ions having the reverse conductivity type with respect to a silicon substrate are implanted by 1X10<15>/cm<3> or more. High-energy ion particles having the same conductivity type as that of the silicon substrate are further implanted. The high energy at this time is selected as follows: the polysilicon 3, which is the gate electrode, is passed, and the peak concentration is obtained at the depth of the end of the source/drain region. Thereafter, annealing is performed in order to activate an ion implanted layer 4 in a nitrogen atmosphere at 900 deg.C for about 30 minutes. When the deep implanted layer is provided in a MOSFET in this way, high breakdown strength can be obtained without impairing the performance of the MOSFET.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention relates to an MO3 field effect transistor (hereinafter referred to as MO3 field effect transistor).
This is related to increasing the withstand voltage of SFETs.

[Conventional technology]

As the density of semiconductor integrated circuits increases, MOSFETs have been reduced in size according to the so-called scaling law.

As is well known, when MOS FETs are downsized and their channel lengths become shorter, their threshold voltages and source-drain breakdown voltages are lowered. Such threshold voltage and source/drain breakdown voltage are required for MOS F
This is an important factor that determines the lower limit of the reduction of ET. Below, the conventional technology N-channel JLzSi 1-M
I'll explain OSFE'r.

FIG. 4 is a cross-sectional view of the fabrication of an N-channel St Gut MOS FET. In the figure, ▪ is a P-type silicon substrate, 2 is a gate oxide film, 3 is polysilicon serving as a gate electrode, 4 is an ion-implanted channel doped layer), and 5 is a source/drain region. FIG. 4 (al shows gate oxide film 2 formed on P-type silicon substrate 1, polysilicon 3
This is where it was deposited. Note that before forming the gate oxide film 2, boron or the like is implanted for adjusting the threshold voltage (formation of the channel doped layer 4). Figure 4 (BL is a photolithographic technique where the part that will become the gate aggregate grains is etched. Figure 4 (C1 is the part that will become the N-type impurity ion) using polysilicon 3 as a mask. This shows the ion implanted area. Figure 4 (dl) is then annealed to activate the implanted layer and form the source/drain regions. At the same time, the polysilicon 3 is also implanted with impurities, so it becomes conductive. Show that.

[Problem to be solved by the invention]

In such conventional MOSFETs, the channel length (
If the gate length is shortened, the source/drain breakdown voltage decreases, but as a countermeasure to this, conventional technology increases the impurity concentration of the P-type substrate or thins the gate oxide film to increase the threshold voltage. The method used has been to increase the concentration of the channel doped layer by the amount of decrease in the concentration of the channel.The countermeasure to increase the substrate concentration has the drawbacks of increasing the substrate bias effect of the MOSFET and increasing the junction capacitance. The countermeasure to make the gate oxide thinner has two problems: an increase in gate capacity and a decrease in gate oxide film breakdown voltage.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to obtain a field effect transistor that can achieve high breakdown voltage while maintaining high performance.

[Means to solve the problem]

The field effect transistor according to the present invention has a channel region formed on a silicon substrate 1, which is a current path from a source to a train, which is deeper than an ion implantation layer 4 for adjusting a threshold voltage, and a source/drain region. An ion-implanted layer 6A of the same conductivity type as the silicon substrate 1 is provided at a depth of about 5, and the source/drain region 5 is deeper than this region.
The present invention is characterized in that a distributed ion implantation layer 6B is provided.

[Effect]

In this field effect transistor, the ion implantation layer 6A
acts to increase the source/drain breakdown voltage, and the ion implantation layer 6B acts harmlessly without increasing the junction capacitance of the source/drain region 5.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described as an N-channel Si gate MO.
The diagram of SFET will be explained.

In FIG. 1, ■ is a P-type silicon substrate, 2 is a gate oxide film, 3 is polysilicon that becomes a gate electrode, and 4 is an ion implantation energy for threshold voltage adjustment (in this case, 3
Ion particles of the same conductivity type as the silicon substrate 1 (in this case, boron) are implanted at a voltage of about 0.00 to 600 KeV. The high energy selection at this time passes through the polysilicon 3 which is the gate electrode, and the source/drain region edge (
FIG. 1 shows a portion where a gate oxide film 2 is formed on a P-type silicon substrate 1 and polysilicon 3 is deposited. Note that before forming the gate oxide film 2, boron is implanted for threshold voltage adjustment to form an ion implantation layer 4. Figure 1 (bl is a photolithography technique where the part that will become the gate electrode is left unetched). An impurity having a conductivity type opposite to that of the substrate 1 (arsenic in this case) was ion-implanted at 900°C for 30 minutes in a nitrogen atmosphere for commercialization, which is an important part of the present invention. By providing a deep injection layer in the MOSFET in this way, it is possible to increase the withstand voltage without impairing the performance of the MOSFET.

Next, the operation of this MOS FET will be explained using FIGS. 2 and 3. FIG. 2 shows the impurity distribution in the channel region of the cross section taken along line a-a' in FIG. 1 fdJ. There are two peaks; the deeper peak is the impurity distribution formed by high-energy implantation, and the shallower peak is the impurity distribution of channel doping. These two impurity distributions suppress the expansion of the depletion layer on the drain side, resulting in a high breakdown voltage MO3FET. On the other hand, Fig. 3 shows the impurity distribution in the source/drain region of the cross section b-b'' in Fig. 1 (fd). Unlike the case shown in Fig. 2, the injection is deeper.The peak on the shallow side is at the same position as shown in Fig. 2, and is located inside the N゜ distribution of the source/drain region 5. Therefore, like the conventional source/drain regions, the source/drain regions 5 do not come into contact with the opposite conductivity type layer (in this case, P-type boron) with a high N layer, so that the junction capacitance increases. do not have.

As described above, in the MOSFET of this embodiment, after forming the source/drain regions 5, ions are implanted through the polysilicon 3 which is the gate electrode at high energy of 300 to 600 KeV in order to increase the breakdown voltage. In this case, the source/drain region 5 is deeper than the channel region.
Impurities are distributed at a depth similar to that of the source/drain region 5, and impurities are distributed deeper than that region in the source/drain region 5. With this structure, the impurities distributed directly under the channel region act to increase the breakdown voltage of the MOSFET,
On the other hand, impurities distributed deep away from the source/drain region 5 do not increase the junction capacitance of the source/train region (become harmless).

In addition, in the above example, the most common structure as MOSFET was described, but this MO5FIET has a source
LDD type MO5FII with N-layer provided in the drain region
A similar structure can be obtained for ET. Also, N
A similar structure can be obtained not only for the St-channel St-channel MO3FET but also for the P-channel Si-channel MO3FET.

〔Effect of the invention〕

As described above, according to the present invention, an ion implantation layer of the same conductivity type as that of the silicon substrate is provided in the channel region deeper than the ion implantation layer for threshold voltage adjustment and approximately to the depth of the source/drain regions, and the source・Since the drain region is configured with a deeper (and distributed) ion implantation layer than this region, the source/drain withstand voltage increases, and the junction capacitance of the source/drain region does not increase, thus achieving high performance. The effect is that it is possible to achieve a high breakdown voltage while maintaining the same.

Fig. 1 is a sectional view for explaining the manufacturing process of the transistor, Fig. 26
The figure is a diagram for explaining the impurity distribution in the channel region in this embodiment, and FIG. 3 is a cross-sectional view for explaining the manufacturing process of the low-resilicon transistor in this embodiment 3.

DESCRIPTION OF SYMBOLS 1... Silicon substrate, 4... Ion implantation layer for threshold voltage adjustment, 5... Source/drain region, 6A.
...Deep ion implantation layer under the channel region, 6B...Deep ion implantation layer under the source/drain region.

Agent Oiwa Iwa Masu m<2 idiots) Figure 2 Figure 3 5i47 rebellion Figure 4

Claims (1)

[Claims] The channel region, which is a current path from the source to the drain, is formed on the silicon substrate, and the conductivity type is the same as that of the silicon substrate. A field effect transistor characterized in that an ion implantation layer is provided in the source/drain region, and the ion implantation layer is deeper and distributed in the source/drain region.