JPH07202010A - Dual gate type cmos semiconductor device - Google Patents

Abstract

PURPOSE:To increase the level of integration by a method wherein a PMOSFET is transformed from buried channel structure into surface channel structure, and Lp<Ln and Wp<=Wn are satisfied when the gate length of the PMOSFET is Lp, the gate length of an NMOSFET is Ln, and the gate widths are Wp and Wn. CONSTITUTION:In a P well 4, an N-type polysilicon electrode 16 is formed on a region sandwiched by the source/drain regions 10, 10 of an NMOSFET, via a gate oxide film 14. In an N well 6, the source/drain region 22 of a PMOSFET, a gate electrode 24, and a P-type polysilicon electrode 26 are formed. When the gate length of the PMOSFET is Lp and the gate length of the NMOSFET is Ln, the relation Lp<Ln can be satified. Further by suitably selecting combation of the gate lengths, a CMOS element wherein the gate widths Wn, Wp of N, PMOSFET's satisfy the relation Wp<=Wn can be designed. Thereby the level of integration can be increased as compared with the coventional device.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention uses N-type conductivity type polysilicon for the gate electrode of an NMOSFET,
The present invention relates to a dual gate CMOS semiconductor device using P-type conductivity type polysilicon for its gate electrode.

[0002]

2. Description of the Related Art NMOSFET and P constituting a CMOS
N-type conductivity type polysilicon is commonly used for the gate electrodes of the MOSFETs. In this case, the NMOSFET has a surface channel structure, while the PMOSFET has a buried channel structure. However, in order to cope with miniaturization with a gate length of 0.35 μm or less, the PMOSFET
In order to suppress the punch-through, it is effective to change the gate electrode of the PMOSFET to the P-type conductivity type and shift to the surface channel structure.

In a conventional CMOS semiconductor device using a PMOSFET having a buried channel structure, the gate length Ln of the NMOSFET and the gate length Lp of the PMOSFET are set to Ln = Lp depending on the minimum dimension value of the design rule, or punch through of the PMOSFET is performed. Considering this, it is general that Lp> Ln. Therefore, in the case of a CMOS composed of an NMOSFET and a PMOSFET having the same gate width W, the current driving capability of the PMOSFET becomes low, which causes a problem that the circuit speed becomes slow and the waveform becomes dull.

As a measure against this problem, it is generally adopted to set the gate widths Wn and Wp to Wp> Wn in order to match the current driving capability levels of the NMOSFET and PMOSFET, but the gate width Wp is also adopted.
However, there is a problem that the degree of integration decreases in inverse proportion to the increase of.

[0005]

SUMMARY OF THE INVENTION It is an object of the present invention to increase the degree of integration in a dual gate CMOS semiconductor device.

[0006]

A dual-gate CMOS semiconductor device according to the present invention has a PMOS gate length.
When the gate length of the FET is Lp and the gate length of the NMOSFET is Ln, Lp <Ln.

Regarding the gate width, PMOS FE
When the gate width of T is Wp and the gate width of the NMOSFET is Wn, it is preferable that Wp ≦ Wn. More preferably, the gate length L
Both n and Lp are smaller than 0.35 μm, the NMOSF
Refractory metal silicide is formed in the source / drain regions of ET and PMOSFET.

[0008]

By changing the PMOSFET from the buried channel structure to the surface channel structure, punchthrough can be greatly suppressed. FIG. 1 shows an example thereof. The symbol ▲ indicates the case where N-type polysilicon is used as the gate electrode in the PMOSFET and the channel length L on the horizontal axis
The threshold voltage Vth sharply decreases as the mask length (FIG. 1 shows the mask size) becomes shorter. In contrast, ●
The data indicated by the marks are for the case of using P-type polysilicon as the gate electrode in the PMOSFET, which has a surface channel structure. In the case of the surface channel structure, even if the channel length is reduced, the threshold voltage does not decrease sharply, which indicates that punchthrough can be suppressed.

In the case of the surface channel structure, the short channel effect can be suppressed even if the threshold voltage becomes low, and as a result, the off leak can be suppressed sufficiently low even if the gate length L becomes short. This effect has a gate length of 0.35.
It becomes more conspicuous when the size becomes less than μm. Therefore CM
When further reducing the size of the OS semiconductor device, the NMOS
New combinations of FET and PMOSFET gate lengths become feasible.

FIG. 2 shows an NMOSFET and a PMOSFET.
FIG. 6 is a cross-sectional view of a CMOS device in the case where both have a surface channel structure. P well 4 and N on the surface of the silicon substrate 2.
A well 6 is formed, and both wells are separated by an element isolation field oxide film 8.

An NMOSFET is formed in the P well 4. An N type conductivity type polysilicon electrode 16 is formed on the region sandwiched between the source / drain regions 10 and 10 with a gate oxide film 14 interposed therebetween. The NMOSFET needs a low-concentration N-type layer 12 for suppressing hot carrier deterioration, and the length of the N-type layer 12 in the channel length direction is 0.
The practical size is about 1 μm. Reference numeral 18 is a sidewall of an insulator used to form the N-type layer 12 and the source / drain region 10, and 20 is a refractory metal silicide layer.

On the other hand, a PMOSFET is formed in the N well 6. In the PMOSFET, 22 is a source / drain region, 24 is a gate electrode, 26 is a P-type conductivity type polysilicon electrode formed on the gate electrode, 28 is a sidewall, and 30 is a refractory metal silicide layer. PMOS
Since the FET is not deteriorated by hot carriers as much as the NMOSFET, it is possible to increase the effective channel length, which is more advantageous for reducing the gate length. Therefore, the gate length of the PMOSFET is Lp, and the NMOSFET is
When the gate length of L is set to Ln, it becomes possible to set Lp <Ln, and it is possible to improve the current drive capability balance as a CMOS element.

Further, by properly selecting the combination of the gate lengths, the gate widths Wn, Pn of the NMOSFET are
As for the gate width Wp of the MOSFET, it is possible to design a CMOS device with Wp ≦ Wn, and it is possible to increase the degree of integration as compared with the conventional case.

The parasitic resistance including the source / drain regions and the contact portion is usually higher in the PMOSFET. However, when the refractory metal silicide is formed in the source / drain regions, the parasitic resistance is significantly reduced, and there is no difference in the size of the parasitic resistance between the NMOSFET and the PMOSFET. From this point, it is not necessary to increase the gate width Wp of the PMOSFET. Therefore, it is more advantageous for designing a CMOS device in which Lp <Ln and Wp ≦ Wn.

[0015]

【Example】

(Embodiment 1) CM in which NMOSFET gate electrode is N-type polysilicon, PMOSFET gate electrode is P-type polysilicon, and both MOSFETs are surface channel type
FIG. 3 shows the results of examining the current driving capability of the OS element. FIG. 3 compares the saturation current values Idsat of both MOSFETs. Drain voltage Vd =
It was set to 3.3V. The saturation current value is represented by the current per unit gate width. The threshold voltage is NMOSFET.
It was 62V and PMOSFET 0.51.

From the results shown in FIG. 3, it can be seen that the saturation current value at the same level as that of the NMOSFET having the gate length of 0.35 μm can be obtained by the PMOSFET having the gate length of 0.25 μm. From Figure 1, PMOSFET with a gate length of 0.25 μm
There is no problem of short channel effect, and it is practical. Therefore, using such a combination of gate lengths,
It is possible to create a CMOS having a good balance of current driving capability between NMOSFET and PMOSFET. As in this example, the gate length of NMOSFET is 0.35 μm, PM
If the gate length of the OSFET is 0.25 μm, both MO
SFET has the same saturation current value and gate width Wp = Wn
As a result, it is possible to produce a CMOS device having a good current drive capability balance. At the same time, since the gate width Wp of the PMOSFET can be set to the same value as the gate width Wn of the NMOSFET, the degree of integration can be increased.

In the example of FIG. 3, the gate length L of the NMOSFET is
When n is 0.35 μm, the gate length L of the P MOSFET is
If p is smaller than 0.25 μm, the gate width is Wp <
It can be Wn. As a result, the degree of integration can be increased.

Example 2 A salicide process, that is, a process of two-step annealing and selective etching of titanium, is used to form an NMOSF as shown in FIG.
A titanium silicide layer 20 was formed in the source / drain regions of ET and PMOSFET. Then, the parasitic resistance including the source / drain region and the contact portion of this element was evaluated. As a method of metal contact to this element, a corner contact in which one contact is arranged only in the corner portion of the source / drain region was used. The contact diameter was 0.8 μm.

The parasitic resistance without a titanium silicide layer is 840Ω for PMOSFET and 270 for NMOSFET.
Ω, and the parasitic resistance of PMOSFET is NMOSFET.
The parasitic resistance is 3 to 4 times. However, when the titanium silicide layer is formed, the parasitic resistance is 100 in PMOSFET.
Ω, 60 Ω for NMOSFET, the parasitic resistance of both MOSFETs is significantly reduced, and the difference is also small. Since the channel resistance of a MOSFET having a gate width of 10 μm is about 1 kΩ, it can be almost ignored.

From the above, by forming the titanium silicide layer in the source / drain regions and by combining with the gate length shown in the first embodiment, N
It is possible to create a CMOS device in which the current drive capabilities of the MOSFET and PMOSFET are better balanced.
Further, by combining with the gate length shown in the first embodiment, the gate width of the PMOSFET can be set to the same value as the gate width of the NMOSFET, so that the degree of integration can be increased.

[0021]

In the dual gate CMOS semiconductor device of the present invention, the gate length Lp of the PMOSFET and the NMOSF
Since Lp <Ln is set for the gate length Ln of ET, the current driving capability balance is improved. Also, PMOSFET
With regard to the gate width Wp of the NMOSFET and the gate width Wn of the NMOSFET, it is possible to provide a highly integrated CMOS.

[Brief description of drawings]

FIG. 1 is a diagram showing a threshold voltage change with respect to a surface channel type and a buried channel type channel length of a PMOSFET.

FIG. 2 is a cross-sectional view showing a CMOS device of one embodiment.

FIG. 3 is a diagram showing a gate length and a saturation current value in the embodiment of FIG.

[Explanation of symbols]

 10, 22 source / drain region 12 low-concentration N-type diffusion layer 14, 24 gate oxide film 16 N-type conductivity type polysilicon electrode 20 titanium silicide layer 26 P-type conductivity type polysilicon electrode

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication 7514-4M H01L 29/78 301 C

Claims (7)

[Claims] 1. In a CMOS semiconductor device in which N-type conductivity type polysilicon is used for the gate electrode of the NMOSFET and P-type conductivity type polysilicon is used for the gate electrode of the PMOSFET, the gate length of the PMOSFET is set to Lp and NMO is set.
A CMOS semiconductor device, wherein Lp <Ln when the gate length of the SFET is Ln. 2. The gate lengths Ln and Lp are both 0.35 μm.
The CMOS semiconductor device according to claim 1, which is smaller than m. 3. The CMOS semiconductor device according to claim 1, wherein refractory metal silicide is formed in the source / drain regions of the NMOSFET and PMOSFET. 4. A CMOS semiconductor device in which N-type conductivity type polysilicon is used for the gate electrode of the NMOSFET and P-type conductivity type polysilicon is used for the gate electrode of the PMOSFET, and the gate width of the PMOSFET is Wp, and NMO is used.
A CMOS semiconductor device, wherein Wp ≦ Wn when the gate width of the SFET is Wn. 5. The gate lengths Ln and Lp are both 0.35 μm.
The CMOS semiconductor device according to claim 4, which is smaller than m. 6. The CMOS semiconductor device according to claim 5, wherein refractory metal silicide is formed in the source / drain regions of the NMOSFET and the PMOSFET. 7. A CMOS semiconductor device in which N-type conductivity type polysilicon is used for the NMOSFET gate electrode and P-type conductivity type polysilicon is used for the PMOSFET gate electrode, and the gate length of the PMOSFET is Lp, and NMO is used.
When the gate length of the SFET is Ln, Lp <Ln, both the gate lengths Ln and Lp are smaller than 0.35 μm, the gate width of the PMOSFET is Wp, and the NMO
A CMOS semiconductor device, wherein Wp ≦ Wn when the gate width of the SFET is Wn, and refractory metal silicide is formed in the source / drain regions of the NMOSFET and PMOSFET.