JPS59215766A - Metal oxide semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To obtain transistors, through which high currents can be flowed, by each forming source and drain regions in a high dielectric resistance transistor into a diffusion layer of the same conduction type as a substrate formed on the substrate and a diffusion layer of a conduction type reverse to the substrate in an IC consisting of a C-MOS logic circuit element operating at low voltage and the high dielectric resistance transistor controlled by said logic circuit element. CONSTITUTION:A P<-> type layer 7 and an N<-> layer 8 are diffused and formed to a P<--> type Si substrate 2, and N<+> type drain region 9 and source region 10 are shaped into the layer 7, thus manufacturing an N channel MOS transistor element 5. P<+> type drain region 12 and source region 13 are formed to the layer 8, thus manufacturing a P channel MOS transistor element 6. A C-MOS logic circuit section 3 operating at low voltage is constituted by these elements 5 and 6. A high dielectric resistance transistor element 4 consisting of an N<+> type drain region 22 in an N<-> type region 28 and an N<+> type source region 23 in a P<-> type region 29 is formed at a position separating from the element 6.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a MOEI integrated circuit device, and more specifically, the present invention relates to a MOEI integrated circuit device, and more specifically, a CMOS circuit with low voltage operation and a MOEI integrated circuit device with high current and high voltage resistance.
EI) A transistor.

For example, an integrated circuit device for controlling the FFI operation of a printing heating element for a thermal printer includes a large current, high voltage transistor for controlling the heating current supplied to the heating element, and whether the transistor is turned on or off. The configuration includes a CMOS logic section that operates at a low voltage and controls the operation. In this way, in an integrated circuit device in which a low voltage operation CMOS logic section and a large current, high voltage MOS transistor are formed on the same chip, in order to improve the voltage resistance performance of the MOS transistor, it is necessary to Although it is possible to use a MOS structure (for example, off-cellar), it has the disadvantage that the structure is complicated and it is difficult to extract a large current.

Therefore, the object of the present invention is to create a MOS for large current and high voltage.
An improved B fcMOS integrated circuit device equipped with an output transistor on the same substrate that does not require a complicated manufacturing process and is capable of drawing a large current kfff with a small chip size. Our goal is to provide the following.

The structure of the present invention includes a low voltage operation CMOS logic circuit element and the C! In an MO integrated circuit device in which a high breakdown voltage transistor controlled by a MOS logic circuit is formed, a source region and a drain region of the high breakdown voltage transistor are formed on the semiconductor substrate. are formed in a first diffusion layer of the same conductivity and a second diffusion layer of opposite conductivity, respectively, and the first and second diffusion layers are formed in the CMOS.
It is characterized in that it is formed at the same time as the logic circuit element is formed.

Hereinafter, the present invention will be explained in detail with reference to the illustrated embodiments.

The drawing shows a cross-sectional view of an embodiment of an MO8 integrated circuit device according to the invention. This MO8 integrated circuit device it
i is a CMO with low voltage operation on the P- semiconductor substrate 2.
E! A logic circuit section 3 and a high-voltage, large-current transistor 4 driven by the logic circuit section 3 are formed.

C! The MOS logic circuit section 3 is an N-channel full M0'S.
) consists of a transistor 5 and a P-channel MO 6), and these MOS) transistors 5 and 6 are:
They are formed in the P-diffusion layer 7 and the N-diffusion layer 8 formed on the substrate 2, respectively. ) ■Cha/J, LeMO8) The transistor 5 has an N+ diffusion layer 9 that acts as a drain region, an N+ diffusion layer 9 that acts as a source region, and a gate oxide film 1.
Consisting of 1. The P-channel MOEI) transistor is cut out from the P-mineralized layer [2] which acts as a drain region, the P-mineralized layer 13 which acts as a source region, and the gate oxide film 14.

Here, 15 and 16 are gate electrodes, 17 and 18 are drain electrodes, 19.20 are source electrodes, and 21 is s
h.

Chill with one film.

The high-voltage transistor 4 is a transistor with an N diffusion region η acting as a drain region, an N+ diffusion region acting as a source region, and a gate oxide transistor. Drain electrodes 5 are provided on L and the like, respectively.
, a source electrode 26, and a gate electrode n are provided. The N raw mineral dispersion region 22 is formed in the substrate 2 at the same time as the formation of the N− diffusion region 8. It is formed within the P- diffusion region 29 formed in the substrate 2 at the same time as the formation of the diffusion region 7.

In this way, N serves as the drain and source regions, respectively.
An N− diffusion layer 2 is formed between the raw mineral diffusion layer η, 23 and the p”-substrate 2.
8 and the P- diffusion layer 29, the breakdown voltage performance and current characteristics of the high voltage transistor can be significantly improved. That is, it is formed so as to surround the N mineral dispersion region 22 that is necessary in the drain region! The breakdown voltage of the transistor 4 can be increased due to the N-diffusion region, and a high withstand voltage can be achieved. On the other hand, punch-through occurs in the P- diffusion region 29, which is formed to surround the N+ diffusion region 93 in the source region. Since it is possible to set a large current per channel width, it is possible to configure a large output current integrated circuit.

In addition, the N- and P- diffusion layers 2 which work beneficially as described above.
8 and 29 are formed simultaneously with the logic circuit section 3ON- and the P- diffusion layers 8 and 7, so they can be realized without complicating the manufacturing process.

In the above embodiment, an embodiment in which the present invention is fully applied to an IC for driving a printing element for a thermal printer has been described, but the present invention is not limited to this embodiment, and can be used in other applications. The present invention can be applied to a conventional MO8 integrated circuit device.

According to the present invention, a CMO driven at a low voltage of about 5V
S logic section and B, pO driven at relatively high voltage
A MOS consisting of a high-voltage MO8) transistor that is controlled by a signal from the MOS logic section.
The integrated circuit device can be formed on a single substrate, and the withstand voltage characteristics of the high voltage transistor can be maintained as above without complicating the manufacturing process, and a large current can be passed through the high voltage transistor. ) has excellent effects.

[Brief explanation of drawings]

The drawing is a cross-sectional view of an embodiment of the MO8 integrated circuit device according to the X invention. 1゜0MO8 integrated circuit device 2゜. Semiconductor substrate 3°. Logic circuit section 4°. High voltage transistor 5°. N channel MOS) U/Gystaro. P channel MO8) Langistav, 29°. P-diffusion layer 8.28°, N-diffusion layer 9, 10, 22, 23,. N+ diffusion layer 12,
13°, P mineral dissemination layer 21,. 5jO2, Membrane and above Applicant Daini Seidokusha Co., Ltd. Agent Patent Attorney Mogami Affairs

Claims (1)

[Claims] In a MOS integrated circuit device comprising a CMOS logic circuit element operating at a low voltage and a high voltage transistor controlled by the CMOS logic circuit formed on a semiconductor substrate of a first conductivity type, the high voltage transistor A source region and a drain region of f′ are formed on the semiconductor substrate.
The first and second diffusion layers are formed in a first diffusion island of the same conductivity type as the semiconductor substrate or a second diffusion layer of an opposite conductivity type, respectively, and the first and second diffusion layers are formed simultaneously when forming the CMOS logic circuit element. A MOS integrated circuit device characterized by a