JPS6355975A - Semiconductor device - Google Patents

Abstract

PURPOSE:To facilitate the formation of a super LSI, by providing a part having different impurity concentration on the surface of a substrate in a channel part of one MOS transistor TR, forming regions having different threshold voltage values, forming a different gate electrode for every region, and connecting the electrodes. CONSTITUTION:Element isolating regions 48 are selectively formed on a P-type semiconductor substrate 4 with thick silicon oxide films. Boron ions 47 are implanted to form an MOS and to control a threshold voltage value. Then, as a gate oxide film, SiO2 42 is formed. Poly-Si 43 is formed thereon as a gate electrode. After a gate oxide film is formed again, ions are implanted to control the threshold voltage value and to form an MOS, and a P<+> ions implanted region 45 is formed. Finally a polycrystalline silicon film is formed. Thereafter, poly-Si 44, which is a second gate electrode, is formed by photoetching. The different electrode is formed for every region having the different threshold voltage value. The electrodes are connected, and the increase in area of the device is minimized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to an MIS field effect transistor with excellent hot carrier resistance.

[Conventional technology]

Conventionally, the structure that has been popular as a hot-resistant carrier device is the LD as described in Japanese Patent Publication No. 48-44056.
An example is the D structure. However, when the gate length reaches submicron, even the LDD structure is not reliable enough and a new structure is required, and in addition to structural measures, circuit improvements are also being attempted. An example of this is a method in which a normally-on enhancement type MOS transistor is inserted in series between the drive NMOS transistor of the inverter and the output node, as described in Nikkei Micro Devices, Summer 1985 Issue 1, Item 48. There is. As a result, the voltage between the drain and the source is divided between the two MOS transistors, and the reliability of each transistor can be improved.

[Problem that the invention seeks to solve]

Among the above-mentioned conventional techniques, the LDD structure does not have sufficient breakdown voltage when the gate length becomes submicron or even half micron, and it is difficult to obtain a fundamental solution with only slight improvements in the LDD structure.

Furthermore, when circuit technology is used, although reliability is certainly improved, the number of transistors increases, making it impossible to prevent an increase in chip area.

An object of the present invention is to realize a method using circuit technology in an element structure as a method capable of improving reliability, and to suppress an increase in area to a minimum.

[Means for solving problems]

The above purpose is to provide regions with different substrate surface impurity concentrations within the channel region of one MOS transistor to form regions with different threshold voltages, or to form different gate electrodes for each region with different threshold voltages, and to This is achieved by connecting the gate electrodes.

[Effect]

The hot carrier resistance in this structure will be explained using an equivalent circuit. Here, 7 in Figure 1 is an enhancement type MO8, 5 is a depression type MO8,
The CMO inverter drives these powered by human power.
An example of application to an OS transistor is shown in FIG. 3, and an example of a standard type inverter is shown in FIG. 2 for comparison.

First, in the standard inverter shown in Fig. 2, this drive NM
FIG. 2(b) shows the operating voltage locus of the load capacitance of an OSMOS transistor drawn on a plane with gate voltage Vas and drain voltage Vog.

A solid line 22 in the figure is a locus. In addition, the broken line 21
The isocurrent curve of the substrate current is shown in 10-8 from the top.
．． 10-7.10-aA (7) Monotial, ,: From the figure, the substrate current flowing through the NMOS transistor during the transition period of the CMOS inverter is mostly due to discharge operation, and the maximum 10
- It is expected that a substrate current of less than 1A will flow.

On the other hand, as shown in FIG. 3(a), the driving NMO
In the equivalent circuit when the structure of the present invention is applied in place of the S transistor, each transistor Qa.

The operating voltage loci of Qaa are as shown in FIGS. 3(b) and 3(c), respectively. The isobase current curve in this figure is 10-7°10 from the top.
-6,1O-9A. In this way, the drain voltage of each transistor is well divided compared to Fig. 2(b), so the voltage trajectory does not pass through the region where a large amount of substrate current occurs, and the amount of current is about 3 to 4 digits. The current has decreased. In general, device lifetime τ due to hot carrier effect
has a relationship of τ” (ISUB, piah)A with the peak value of this substrate current, and strongly depends on the peak value I5IJBePeJ1k. Here, since A is generally 2.5 to 4,
A 3- to 4-digit current reduction in substrate current is equivalent to a 7- to 10- or more-digit improvement in life, as shown in Figure 3 (
It can be seen that the structure of the present invention shown in the equivalent circuit a) can provide high reliability.

However, as shown in the equivalent circuit, the present invention doubles the number of elements (assuming the gate length of each transistor is constant).
Therefore, an increase in chip area and a slight decrease in speed are unavoidable.However, if the structure of the present invention is used, the area will be smaller than if the same circuit were formed using two completely different transistors, and the overall increase rate would be 10%. % or less.

Application of the present invention to LSIs allows for the creation of complex structures to improve voltage resistance by quantitatively understanding the stress applied to each transistor during circuit operation. It is wiser to use the structure of the present invention, which applies the above circuit technology, than to form it by a complicated process.

Furthermore, although the above explanations all give examples of the N-channel MO5 structure, it can also be applied to the P-channel MO8 structure by reversing the conductivity type and the sign of the applied voltage.

〔Example〕

Example 1 Below, as a first example of the present invention, a process for forming the structure shown in FIG. 1(a) will be outlined using FIG. 4.

First, as shown in FIG. 4(a), an element isolation region 48 is selectively formed with a thick silicon oxide film on a p-type 10Ω-1 silicon substrate by photoetching technology, and threshold voltage control for enhancement type MO8 formation is performed. Boron ions 47 are implanted. Next, as shown in (b), the gate oxide film 42 is
After forming a 5 nm thick polycrystalline silicon film and coating a 350 nm thick polycrystalline silicon film, the first gate electrode 43 is formed by photoetching again.
form. Next, as shown in (c), after forming a gate oxide film again to a thickness of 25 nm, phosphorus ions for threshold voltage control to form a depletion-type MO8 are implanted.Finally, as shown in (d), a polycrystalline silicon film is formed to a thickness of 350 nm, and then photolithography is performed. A second gate electrode 44 is formed by etching, and arsenic is implanted at a high concentration to form an n-plane wave diffusion layer 46. After coating an interlayer insulating film, a contact hole is formed and the two gates are connected using aluminum wiring. and complete it.

In this embodiment, since the two gate electrodes are formed separately, impurities can be implanted under each electrode in a self-aligned manner. However, in this embodiment, it is difficult to control the gate length of the second gate 44. When this embodiment is used in a CMOS inverter drive circuit, the second gate MO5 side, which is a depression type, is brought to the output side. . The characteristics of this inverter are the enhancement type M of the first gate.
Although it is sensitively influenced by the W/L on the O8 side, it has the characteristic that it is almost unaffected by slight fluctuations in the W/L of the depression type MO8. Therefore, the process shown in this embodiment is sufficient. This process is a normal polycrystalline silicon gate two-layer process, and there are no particularly difficult parts.

Embodiment 2 Next, a second embodiment of the present invention will be described using FIGS. 5 and 6.

In the first embodiment described above, the two gate electrodes were formed separately and later connected in an aluminum wiring process. Figures 5 and 6 show an embodiment in which connections were made in the previous process. The one shown in FIG. 5 is one that is connected to the first gate when the second gate electrode 4 is formed, and the one shown in FIG. 6 is one that is connected to the first gate when the second gate electrode 4 is formed. It is formed by coating the conductor 10. In addition.

This conductor may be of any material, and a method may also be used in which a contact hole is formed to connect the two gate electrodes at the same time in the final aluminum wiring process.In this case, rather than separately drilling contact holes for the two gates and wiring the aluminum wiring. Can be reduced.

Embodiment 3 An example in which the second embodiment (FIG. 6) is applied will be described with reference to FIG. 7.

The structure shown in this figure is obtained by forming up to the second gate using the same process as in the first embodiment, and further forming the third gate. This is effective in applications where higher reliability is required than in the first and second embodiments, for example, to transistors to which a high write voltage is applied in EPROM, which is a non-volatile memory. In this case, the threshold voltage of the first gate on the left is the highest, and conversely, the threshold voltage of the third gate on the right is the lowest (or negative voltage, if these are n-channels). can be achieved. Moreover, (b) shows the equivalent circuit. In this way, the number of regions with different threshold voltages or the number of gates may be determined depending on the amount of reliability improvement required at that time.

〔Effect of the invention〕

According to the present invention, higher reliability than the conventional structure can be achieved simply by applying the conventional process, and it will be very effective for constructing future ULSI.

[Brief explanation of the drawing]

Fig. 1 is a cross-sectional view of a structure showing a typical example of the present invention, Fig. 2 is a circuit diagram of a standard CMOS inverter and a diagram showing the operating voltage locus, and Fig. 3 is an equivalent circuit when the present invention is applied to a CMOS inverter. FIG. 4 is a diagram showing a process flow forming a first embodiment of the present invention, and FIGS. 5 and 6 are diagrams showing the operating voltage trajectory. Figure 7 shows another embodiment of the invention. Figure 61.41
... Semiconductor substrate, 2,42.48 ... Insulating film, 3.
4, 43, 44, 71, 72, 73... gate electrode,
5,7,45,47,75,76.77...Threshold pressure control impurity layer, 6.46...High concentration diffusion layer, 21,
31... Equivalent substrate current curve, 22,32゜＼~ ゛1st ffJ (long) v2 concave (good) 221 force 1 to pressure 3rd factor (0,,) (b) (C)% 5(V)
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Claims (1)

[Claims] 1. A semiconductor device characterized in that a MIS type field effect transistor formed on a semiconductor substrate has two or more regions having different impurity concentrations in a surface region of the substrate between a source and a drain. 2. In the semiconductor device according to claim 1,
A semiconductor device characterized in that a separate gate electrode is provided for each region having a different impurity concentration. 3. In the semiconductor device according to claim 2,
A semiconductor device characterized in that all of the gate electrodes are connected. 4. In the semiconductor device according to claim 1, 2, or 3, there are two types of MIS type structures, an enhancement type and a depletion type, each formed of an impurity concentration region and a gate electrode on the region. A semiconductor device comprising: