JP3088203B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which a MIS type FET has improved electrostatic breakdown resistance.

[0002]

2. Description of the Related Art In recent years, there has been proposed a MIS type FET in which the parasitic resistance of the source / drain is reduced. For example, as shown in FIG. 3, after a gate insulating film 2 and a gate 3 are formed on a semiconductor substrate 1 and a source / drain impurity diffusion layer 4 is formed, a high level is formed on the source / drain impurity diffusion layer 4. A silicide of a melting point metal, for example, titanium silicide 5 is selectively formed. By forming this titanium silicide 5, the layer resistance of the source / drain impurity diffusion layer 4 becomes 100% when there is no silicide.
It can be reduced by about one to two digits from about Ω / □ to several Ω / □ with silicide, and the parasitic resistance at the source / drain can be greatly reduced.

[0003] However, the parasitic resistance referred to here indicates not a diffusion resistance from a gate to a connection region (contact region) with a wiring but a diffusion resistance on a plane. That is, as shown in FIG. 5, if the source / drain contacts 6 of the MIS type FET are provided at one point and the wiring is passed through the vacant region, the integration degree of the entire semiconductor device is improved. When the channel width of the FET increases, the parasitic resistance of the source / drain increases if only one contact is provided. Therefore, silicide of a refractory metal is used to reduce the parasitic resistance.

[0004]

The MIS type FET provided with such a silicide has a problem that its electrostatic breakdown resistance is low. FIG. 4 shows a P-channel MOS transistor PMOS and an N-channel MOS transistor NM.
An example of a driving circuit of an output stage of a CMOS circuit configured with an OS is shown. A signal from an internal circuit is connected to a gate G, and drains D of transistors PMOS and NMOS are connected.
Are connected to an external circuit. When pulsed high-voltage noise enters the drain D from the outside, the source / drain impurity diffusion layer 4 has no MIS type F without silicide.
In ET, noise is attenuated by the layer resistance of the impurity diffusion layer 4 and the junction capacitance between the impurity diffusion layer 4 and the substrate 1, and when the noise comes to the channel region, the amplitude of the pulse is also attenuated. However, if the silicide 5 is present as shown in FIG. 3, since the resistance of the silicide 5 is low, the pulse is not so much attenuated, a high voltage is applied to the channel, and the MIS FET is destroyed. An object of the present invention is to provide a semiconductor device capable of improving the electrostatic breakdown resistance of a MIS type FET.

[0005]

SUMMARY OF THE INVENTION The present invention relates to a MIS type F having a contact having a silicide structure made of a high melting point metal.
In the source / drain impurity diffusion layer of the ET, a region where the width of the diffusion layer is smaller than the channel width is provided on the gate side of the contact. The width of the diffusion layer
The region smaller than the channel width is formed as a region in which the external shape of the source / drain impurity diffusion layer is narrowed in the gate width direction. Alternatively, a region where the width dimension of the diffusion layer is smaller than the channel width is a parallel
Consists of a number of constricted areas . A plurality of constricted regions are formed in parallel in the source / drain impurity diffusion layers.

[0006]

Next, the present invention will be described with reference to the drawings. FIG. 1 is a plan view of one embodiment of the MIS type FET of the present invention. A gate 3 is formed on a semiconductor substrate 1, and a source / drain impurity diffusion layer 4 is sandwiched between the gate 3.
Is formed. A contact 6 having a silicide structure is formed in the impurity diffusion layer 4. This contact 6
Has a cross-sectional structure similar to that shown in FIG. Further, the impurity diffusion layer 4 has a constricted region 7 between the contact 6 and the gate 3 whose width in the planar direction is smaller than the gate width.

According to this structure, the contact 6 provided in the source / drain impurity diffusion layer 4 has a silicide structure, thereby reducing the source / drain parasitic resistance. The layer resistance of the diffusion layer 4 is increased. Thus, even when pulse-like noise is introduced through the contact 6, the noise is attenuated by the increased layer resistance, a high voltage is prevented from being applied to the channel, and the MISFET is prevented from being destroyed.

FIG. 2 is a plan view of a second embodiment of the present invention. Here, the source / drain impurity diffusion layer 4
By forming a plurality of windows 8 between the contact 6 and the gate 3, a plurality of constricted regions 7 are formed therebetween. Even with such a configuration, it is possible to increase the layer resistance between the contact and the channel, attenuate noise entering from the contact, and prevent the MIS-type FET from being destroyed. In particular, in this configuration, since the high voltage is distributed to a plurality of narrowed regions, the high voltage is not concentrated in one narrowed region as in the first embodiment. According to the experiments of the present inventors, the MISFET having a silicide on the source / drain has an electrostatic breakdown resistance of 1% lower than that of the conventional MISFET.
It was improved by 00 times.

[0009]

As described above, according to the present invention, a region where the width dimension of the diffusion layer is smaller than the channel width on the gate side of the contact is provided in the impurity diffusion layer of the source / drain provided with the silicide structure contact. Because it is provided,
While reducing the parasitic resistance at the source / drain contact, the layer resistance of the source / drain impurity diffusion layer is increased to attenuate noise, and the MIS type FET having a silicide structure contact at the source / drain is provided. This has the effect of greatly improving the breakdown resistance and significantly improving the reliability of the semiconductor device.

[Brief description of the drawings]

FIG. 1 is a plan view of a first embodiment of the present invention.

FIG. 2 is a plan view of a second embodiment of the present invention.

FIG. 3 is a cross-sectional view of a conventional MISFET having a silicide structure.

FIG. 4 is a circuit diagram for explaining a problem in the MIS-type FET.

FIG. 5 is a plan view of the MIS type FET as shown in FIG.

[Description of Signs] 1 semiconductor substrate 3 gate 4 source / drain impurity diffusion layer 5 silicide 6 contact 7 constricted region

Claims (3)

(57) [Claims] An M type transistor having a high melting point metal silicide structure contact in a part of a source / drain impurity diffusion layer.
In a semiconductor device having an IS type FET, the impurity diffusion layer of the source / drain has a region in which a width dimension of the diffusion layer is smaller than a channel width on a gate side than the contact. 2. A region where the width dimension of the diffusion layer is smaller than the channel width is formed as a region where the outer shape of the source / drain impurity diffusion layer is narrowed in the direction of the gate width. The semiconductor device according to claim 1. 3. The region in which the width dimension of the diffusion layer is smaller than the channel width is formed by a plurality of parallel narrowed regions.
The semiconductor device according to claim 1 or claim 2 that.