JP4694123B2 - Electrostatic discharge protection element - Google Patents

Description

  The present invention relates to an electrostatic discharge protection element that is formed in a semiconductor integrated circuit and protects a circuit element from destruction due to electrostatic discharge, and more particularly to an electrostatic discharge protection element that utilizes a parasitic bipolar.

  Conventionally, in order to protect a circuit element in a semiconductor integrated circuit from electrostatic discharge (hereinafter also referred to as ESD (Electro Static Discharge)), an electrostatic discharge protection element (hereinafter also referred to as ESD protection element) composed of a diode or a resistance element. Was used. Recently, ESD protection elements provided in CMOS (Complementary Metal Oxide Semiconductor) integrated circuits are discharged from an ESD protection element composed of a diode or a resistance element with a lower resistance than these protection elements. It has been replaced by a MOS type protection element using a parasitic bipolar operation with high capability. This MOS type protective element is a protective element that utilizes the snapback phenomenon of a MOSFET (MOS Field Effect Transistor).

  Even in a MOS type protection element made of a parasitic bipolar transistor, there is a limit to the ability to pass the current, and the protection performance often does not satisfy the required level unless the width of the protection element is increased to about 400 to 800 μm. However, in an integrated circuit, the layout is usually restricted by the arrangement of bonding pads, etc., and it is often necessary to fit a MOS type protection element in a prescribed region. For this reason, the MOS type protection element is not a single element, but a plurality of small MOSFETs called fingers having a width of about 10 to 50 μm are arranged and connected in parallel to each other, and the MOS type protection element is arranged in a specified region. An efficient arrangement method is adopted. At this time, there is a method of connecting a plurality of fingers in parallel with each other using a common source and drain for each finger, and a method of arranging small MOSFETs individually and connecting them in parallel.

  FIG. 8 is a plan view showing an input protection element using a snapback phenomenon of an NMOSFET, which is a conventional MOS type protection element, and FIG. 9 is a diagram showing a cross section taken along the line AA 'shown in FIG. FIG. 10 is a graph showing the operating characteristics of the MOS type protection element with the voltage applied to the protection element on the horizontal axis and the current flowing through the protection element on the vertical axis. As shown in FIGS. 8 and 9, in the MOS type protection element 101, a plurality of gate electrodes 103 extending in one direction are provided on the P type substrate 102 in parallel with each other. A region immediately below the gate electrode 103 on the surface of the substrate is a channel region 104. A region between the channel regions 104 on the surface of the P-type substrate 102 is a source region 105 or a drain region 106, and the source regions 105 and the drain regions 106 are alternately arranged.

Thereby, a plurality of MOSFETs 111 are formed, and the source region or the drain region is shared between the MOSFETs 111 adjacent to each other. On the surfaces of the source region 105 and the drain region 106, a plurality of contacts 107 are arranged in a line along the direction in which the gate electrode 103 extends. A guard ring 108 made of a P ⁺ region is provided on the surface of the P-type substrate 102 so as to surround the plurality of MOSFETs 111 and is connected to the ground wiring 109. The guard ring 108 is provided for the purpose of preventing latch-up. Further, an input pad 110 is connected to the contact 107 formed on the surface of the drain region 106.

  Next, the operation of the MOS protection element 101 will be described with reference to FIGS. When a current surge is input to the input pad 110, the current surge flows into the drain region 106 via the contact 107, and the drain voltage increases. When the drain voltage becomes equal to or higher than the voltage indicated by voltage Vt0 in FIG. 10, avalanche breakdown starts at the PN junction between the drain region 106 and the channel region 104, and a substrate current flows. At this time, a parasitic bipolar is formed in which the source region 105 of each finger serves as an emitter, the P-type substrate 102 including the guard ring 108 serves as a base, and the drain region 106 serves as a collector. Due to the current flowing in the P-type substrate 102, a potential difference corresponding to the product of this current and the resistance of the P-type substrate 2 is generated in the P-type substrate 102, and the potential near the bottom surface of the source region 105 in the P-type substrate 102 is , The guard ring 108 is raised. As shown in FIG. 10, when the voltage applied to the MOS protection element 101 becomes the voltage Vt1, the potential near the bottom surface of the source region 105 with respect to the guard ring 108 causes the PN junction between the source region 105 and the channel region 104 to be The forward bias is, for example, about 0.7 V, and the PN junction is forward biased to allow further current to flow, and the parasitic bipolar is turned on to enter a low resistance state. As a result, a larger current flows. This phenomenon is called snapback, and the voltage Vt1 is called snapback start voltage or trigger voltage.

  Note that the IV measurement as shown in FIG. 10 is normally performed by a TLP (Transmission Line Pulser) because the current duration time is long in a normal current-voltage measurement device and is destroyed before entering the snapback state. ) Is used. In this method, a rectangular current waveform having a duration of about 100 nsec is added to a DUT (device under test), and the current value and voltage value of the DUT are read from the change in voltage and current. In general, the DUT breakdown current It2 [A] measured by TLP and the DUT breakdown voltage V [V] measured by the human body charging model test (HBM test) are empirically V = It2 × 1500. It is said that there is a relationship.

  In a MOS type protection element composed of a plurality of fingers (multi-finger), the operation differs for each finger. This difference in operation can be explained as being due to a difference in substrate resistance. That is, since the distance from each finger to the ground electrode (usually the guard ring) is different, the substrate resistance, that is, the base resistance of the parasitic bipolar transistor is different, and as a result, each charge accumulation after avalanche breakdown causes each A difference occurs in a local voltage formed in the junction region between the source region and the channel region of the MOSFET. Thereby, the timing at which each parasitic bipolar transistor reaches the snapback voltage is different, and the timing at which each parasitic bipolar transistor is turned on is different. Actually, as shown in FIGS. 8 and 9, the substrate potential is coupled to the substrate current between the fingers, or the substrate is driven by a three-dimensional current route in each finger and the substrate resistance in the width direction inside the finger. There are complex factors that cause differences in substrate resistance between fingers, such as different resistances.

  When a current flows through the drain side PN junction of the finger, that is, the PN junction between the drain region and the channel region, the potential difference at the PN junction portion occupies most of the potential difference in the finger. Heat is generated in the joining area. There is a positive correlation between the current and the junction temperature, and the current increases as the temperature increases. In other words, current is concentrated on some fingers due to process variations and structures, etc., or there are variations in contact resistance and drain resistance, etc. within the fingers, and current is applied to specific fingers or specific areas within the fingers. When it concentrates, it triggers, and the PN junction of the finger or the region in the finger where the current is concentrated generates heat, the temperature rises, and a positive feedback occurs that the amount of current increases. Melts. For this reason, before the other fingers are turned on, the first turned-on finger is destroyed, and the multi-finger structure cannot be used.

  As a countermeasure, basically, a technique for increasing the resistance of the drain region only for the ESD protection element has been developed. As shown in FIG. 10, by adding a ballast resistor to each finger, the drain voltage so that the breakdown voltage Vt2 of each finger alone becomes higher than the snapback start voltage Vt1, that is, Vt1 <Vt2. Adjust the resistance of the area. In FIG. 10, the difference between the slope of the line 112 and the slope of the line 113 is the ballast resistance, and most of the ballast resistance is, for example, the resistance of the drain region. In other words, in the multi-finger structure MOS type protection element, the ballast resistance of the protection element is adjusted to be high so that the minimum value of the breakdown voltage Vt2 is larger than the maximum value of the snapback voltage Vt1 for all fingers. The fingers can be snapped back. Thereby, high protection performance can be secured. That is, if the ballast resistance is increased, all fingers can be surely snapped back.

As a method for adding a ballast resistance to the drain region, a method in which a silicide layer is not formed in the drain region, that is, a method in which a silicide blocking region is provided and the resistance of the N ⁺ region in that portion is used is widely used. In addition, there is a method using an N well resistance or resistance of an impurity region formed in an LDD (Lightly Doped Drain) process (for example, refer to Patent Document 1).

  Various methods have been proposed for forming a silicide blocking region on the drain region. A representative technique is disclosed in Patent Document 2 (Japanese Patent No. 2773221). In Patent Document 2, a silicide layer is not formed over the entire length in the channel width direction in a region between the region connected to the wiring on the surface of the drain region and the region on the gate electrode side, and a part of the drain region is formed. A technique for providing a silicide block region in a slit shape is disclosed. In Patent Document 2, by providing a silicide blocking region in the drain region as described above, any portion in the channel width direction in the region between the region connected to the wiring in the drain region and the region on the gate electrode side is disclosed. It is described that resistance against electrostatic discharge can be improved because uniform resistance can be obtained.

  However, Non-Patent Document 1 (Christian Russ, et. Al. "Non-Uniform Triggering of gg-nMOSt Investigated by Combined Emission Microscopy and Transmission Line Pulsing" Electrical Overstress / Electrostatic Discharge Symposium Proceedings, 1998, (1998) pp.177- 186), when the region where the silicide layer is formed on the surface of the drain region is rectangular, the end portion is a corner portion having an extremely small radius of curvature of 90 °. It is described that it is likely to become avalanche breakdown state first. Therefore, the current tends to concentrate on the end portion of the gate electrode, and local thermal breakdown is likely to occur in the gate insulating film and the gate electrode near the end portion of the gate electrode.

  In consideration of such an electric field concentration effect at the end, current is likely to be concentrated and destroyed in a region where the edge extending in the length direction of the gate electrode in the drain region and the gate electrode intersect with each other. This technology has a low effect to prevent this. That is, if the width of the silicide blocking region is set to a resistance value that limits the current concentrated at the end of the drain region, resistance is added more than necessary to the central portion. Further, in this case, in order to increase the resistance value, it is necessary to increase the width of the silicide blocking region, and there is a disadvantage that the layout area is increased. Further, as an application of the ESD protection element, there is an application in which the voltage during the protection operation (clamp voltage) must be low. In such an application, it is not desirable to increase the width of the silicide blocking region. On the other hand, when the resistance value is optimally determined for the current in the central portion, the region in contact with the drain end of the gate electrode is likely to be destroyed.

  Therefore, Patent Document 3 (Japanese Patent Laid-Open No. 11-13573) and Non-Patent Document 2 (Ming-Dou Ker, Che-Hao Chuang, “ESD Implantations in 0.18-μm Salicided CMOS Technology for On-Chip ESD Protection with Layout Consideration” "Physical and Failure Analysis of Integrated Circuits, 2001. IPFA 2001. Proceedings of the 2001 8th International Symposium on 9-13 July 2001, pp-85-90). A technique for providing a silicide blocking region at the end of the substrate is also disclosed. FIG. 11 is a plan view showing a conventional ESD protection element described in Patent Document 3 and Non-Patent Document 2. FIG. As shown in FIG. 11, in this conventional ESD protection element, a gate electrode 123 is provided on a substrate 122, and a source region 124 and a drain are arranged in a region sandwiching the gate electrode 123 in a plan view on the surface of a P-type well. Region 125 is formed. A contact 126 is provided at the center of the surface of the drain region 125. A silicide blocking region 127 is set on the surface of the drain region 125 so as to surround the contact 126, and a silicide layer (not shown) is formed in a region other than the silicide blocking region 127 on the surface of the drain region 125. Is formed. This is because of the manufacturing process restriction that silicide must be left in the region where the contact is formed. The length L2 in the width direction of the silicide blocking region 127 is made sufficiently large. Thereby, it is possible to prevent a large current from flowing in the end portion in the width direction in the drain region, and it is possible to improve the ESD protection performance. Patent Document 4 (Japanese Patent No. 343080) discloses an invention in which this is improved.

US Pat. No. 5,498,892 Japanese Patent No. 2773221 Christian Russ, et. Al. "Non-Uniform Triggering of gg-nMOSt Investigated by Combined Emission Microscopy and Transmission Line Pulsing" Electrical Overstress / Electrostatic Discharge Symposium Proceedings, 1998, (1998) pp.177-186 Japanese Patent Laid-Open No. 11-13573 Ming-Dou Ker, Che-Hao Chuang, "ESD Implantations in 0.18-μm Salicided CMOS Technology for On-Chip ESD Protection with Layout Consideration" Physical and Failure Analysis of Integrated Circuits, 2001. IPFA 2001. Proceedings of the 2001 8th International Symposium on 9-13 July 2001, pp-85-90 Japanese Patent No. 343080

  However, the above-described conventional technology has the following problems. In the conventional technique shown in FIG. 11, the value of the length L2 needs to be determined carefully. For example, when the length L2 is small, there is a current path 131 that flows out from the side surface of the silicide layer in which the drain contact is disposed, and the corner portion of the silicide layer has a strong electric field, so the current path 132 that flows out from this corner portion is Therefore, these current paths overlap each other, and the current concentrates at the gate / drain ends.

  Actually, the optimum values of the lengths L1 and L2 are related to each other, and a clear distance cannot be defined in element design, and the value of the length L2 tends to be set larger than necessary. When the length L2 is set to be large, it is possible to suppress current concentration at the end of the drain region and to prevent the ESD protection element from being destroyed. However, since the current flowing through the drain region flows through the ballast resistor region and reaches the silicide layer in contact with the gate, the current spreads slightly in the lateral direction, so that the effective width of the transistor is strictly reduced by the length L2. However, if the length L2 is increased, the effective width of the transistor decreases at a constant rate. In terms of circuit design, the transistor may be finely divided into small transistors having a width of about 10 to 20 μm. In this case, particularly, an increase in the value of the length L2 has a great influence on the deterioration of the ESD protection performance. .

  In addition, although the region of the length L2 hardly contributes to the driving of the transistor as the ESD protection element, this region is also driven during the normal operation as the IC of the transistor. There is a drawback of generating. In addition, the area of the length L2 occupies a certain area in the semiconductor integrated circuit although it hardly contributes to the protection performance against ESD, so that the area efficiency of the entire semiconductor integrated circuit is reduced. There are also problems.

  The present invention has been made in view of such problems, and is easy to design, can suppress current concentration at the end of the drain region in the gate width direction, has high ESD protection performance, and can reduce the layout area. An object is to provide a discharge protection element.

An electrostatic discharge protection element according to the present invention includes a substrate having a first conductivity type region formed on at least a part of a surface thereof, and alternately on the surface of the first conductivity type region along a first direction. First and second second conductivity type regions formed so as to form a channel region, and the first second conductivity type region faces the second second conductivity type region. Two first regions provided at a position, and an edge between the two first regions and extending in the first direction from an edge extending in the first direction in the first region A second region in a recessed position, and an impurity concentration in the recess of the first second conductivity type region formed by the first region and the second region is the first second conductivity. A low concentration region lower than the impurity concentration of the mold region is formed .

  Furthermore, the first conductivity type region is electrically separated from the first second conductivity type region in the recess of the first second conductivity type region formed by the first region and the second region. Another first conductivity type region may be formed at the connected position, and at this time, the other first conductivity type region formed in the recess of one of the first second conductivity type regions. However, it may be connected to the other first conductivity type region formed in the recess of the other first second conductivity type region. As a result, the potential of the first conductivity type region can be made uniform, and when one finger snaps back, the other fingers can surely snap back. As a result, the protection performance against electrostatic discharge is improved.

  Furthermore, the first second conductivity type region may have an extending portion extending in a direction from each first region toward the other first region. Thereby, this extension part functions as a heat radiation fin, and the heat generated at the boundary surface between the first second conductivity type region and the channel region is diffused into the substrate via the extension part. As a result, it is possible to more reliably prevent the electrostatic discharge protection element from being destroyed by heat.

  Furthermore, a plurality of contacts provided on the first region and connected to the first region and arranged in a second direction orthogonal to the first direction, and wirings connecting the plurality of contacts to each other , May be included. Thereby, since each part of the 1st field is mutually connected by contact and wiring, the potential of the 1st field in the 2nd direction can be made uniform, and current concentrates on a specific part of the 1st field. Can be suppressed.

  According to the present invention, since the edge of the second region of the first second conductivity type region is in a position recessed from the edge of the first region, current is concentrated at the end of the first region. Can be suppressed. As a result, the silicide blocking region can be prevented from becoming unnecessarily large, so that the layout area of the electrostatic discharge protection element can be reduced. In addition, the protection performance of the electrostatic discharge protection element can be improved.

Hereinafter, embodiments of the present invention will be specifically described with reference to the accompanying drawings. First, a first embodiment of the present invention will be described. FIG. 1 is a plan view showing an electrostatic discharge protection element (ESD protection element) according to this embodiment. As shown in FIG. 1, the ESD protection element 1 according to this embodiment is formed on the surface of a P well 2 formed on the surface of a P-type silicon substrate (not shown) and on the P well 2. In the ESD protection element 1, a plurality of gate electrodes 3 are provided on the P well 2 in parallel with each other. In FIG. 1, only two gate electrodes 3 are shown for convenience, but three or more gate electrodes 3 may be provided. The same applies to other embodiments described later. A region immediately below the gate electrode 3 on the surface of the P well 2 is a channel region (not shown), and a source region 4 and a drain region 5 which are n ⁺ -type regions are formed so as to sandwich the channel region. Has been. That is, the source region 4 and the drain region 5 are arranged alternately and spaced apart from each other along the arrangement direction of the gate electrodes 3 (hereinafter referred to as direction 11). Either the region 4 or the drain region 5 is formed. For example, source regions 4 are formed at both ends of the ESD protection element 1 in the direction 11.

  In each drain region 5, two end regions 6 are provided in contact with the channel region, and a region between the end regions 6 is a central region 7. In the drain region 5, the length of the end region 6 in the longitudinal direction (hereinafter referred to as direction 12) of the gate electrode 3 is equal to the length in the direction 12 of the source region 4. The length of the central region 7 in 12 is shorter than the length of the end region 6 in the direction 12, and the end edge 7 a extending in the direction 11 in the central region 7 is the end edge 6 a extending in the direction 11 in the end region 6. It is in a more concave position. That is, the edge 6 a of the end region 6 is on the extension line of the edge 4 a extending in the direction 11 of the source region 4, but the edge 7 a of the central region 7 is further inside the ESD protection element 1. As a result, a recess 5 a is formed in the drain region 5.

  In the central region 7, the central portion in the direction 11 is a contact formation region 8 extending in the direction 12, and both sides of the contact formation region 8 in the direction 11 are ballast resistance regions 9 extending in the direction 12. . A plurality of contacts 10 are provided on the contact formation region 8 and are arranged in a line along the direction 12. Further, the end region 6 is divided into two regions extending in the direction 12. That is, the region 13 near the channel region and the region 14 far from the channel region. The shape of the region 14 is rectangular, and the length in the direction 12 is equal to the length in the direction 12 of the central region 7. The region 13 has a U shape surrounding the region 14. Note that the central region 7 composed of the contact formation region 8 and the ballast resistor region 9 and the end region 6 composed of the regions 13 and 14 are integrally formed at the same time as the drain region 5 by implantation of impurity ions. There are no substantive boundaries between each region.

  A silicide layer (not shown) is formed on the surfaces of the source region 4, the contact formation region 8 in the central region 7, and the region 13 in the end region 6. On the other hand, no silicide layer is formed on the surfaces of the ballast resistor region 9 in the central region 7 and the region 14 in the end region 6, and the silicide blocking region 15 is formed. For this reason, when viewed from the direction perpendicular to the surface of the P-type silicon substrate, that is, in plan view, the silicide blocking region 15 has a rectangular shape whose longitudinal direction is the direction 12.

  A plurality of contacts 16 are arranged in a line along the direction 12 on the source region 4. The contact 16 is connected to a ground potential wiring (not shown), and a ground potential is applied when the ESD protection element 1 operates. The contact 10 is connected to, for example, an input / output pad of a protected circuit (not shown). When a surge current is input to the input / output pad by ESD, the surge current is input to the contact 10. It has become. One MOS transistor is formed by one gate electrode 3 and a channel region immediately below the gate electrode 3, and a source region 4 and a drain region 5 sandwiching the channel region, and this constitutes one finger. In the ESD protection element 1, a plurality of fingers are connected in parallel to each other. The source region 4 and the drain region 5 are shared between adjacent fingers, and two fingers sharing one drain region 5 form a finger pair.

Further, a region surrounding the source region 4, the channel region and the drain region 5 on the surface of the P-type silicon substrate is an STI (Shallow Trench Isolation) region 17. The STI region 17 is also formed in the recess 5a of the drain region 5. Around the ESD protection element 1, for example, a guard ring (not shown) made of a p ⁺ type region connected to a ground potential wiring is formed.

  An example of the dimension of each part in this embodiment is shown. The width L 1 of the silicon blocking region 15, that is, the length L 1 in the direction 11 is, for example, 2 μm. The depth of the recess in the drain region 5, that is, the distance L 2 between the edge 6 a and the edge 7 a is, for example, 1 μm. , That is, the length L3 in the direction 11 is 0.5 μm, and the distance between the central region 7 and the channel region, that is, the length L4 is 0.8 μm.

  Next, the operation of the ESD protection element according to this embodiment configured as described above will be described. When a surge current due to electrostatic discharge is input to the input / output pad of the protected circuit, the surge current flows into the drain region 5 through the contact 10 and the drain voltage increases. When the drain voltage becomes equal to or higher than the voltage Vt0 shown in FIG. 11, avalanche breakdown starts at the PN junction between the drain region 5 and the channel region, and a substrate current flows through the P-type silicon substrate 2. At this time, a parasitic bipolar is formed in which the source region 4 of each finger serves as an emitter, the P-type silicon substrate 2 serves as a base, and the drain region 5 serves as a collector. Due to the substrate current flowing in the P well 2, a potential difference is generated in the P well 2, and the potential near the bottom surface of the source region 5 in the P well 2 rises with respect to the guard ring. When the voltage applied to the drain region 5 reaches the snapback start voltage (voltage Vt1 shown in FIG. 11), the PN junction between the channel region and the source region 4 is forward-biased, and the above-described parasitic bipolar transistor becomes conductive. Snap back and become a low resistance state. As a result, a larger current flows.

  At this time, the surge current flows through the current path of contact 10 → contact formation region 8 → ballast resistance region 9 → region 14 → region 13 → channel region → source region 4 → contact 16 → ground potential wiring. Since no silicide layer is formed on the surfaces of the ballast resistor region 9 and the region 14, a predetermined resistance is added to the above-described current path. As a result, the current flowing through the finger that snapped back first is limited, and the current is also input to the other fingers, so that the other fingers snap back one after another. As a result, all fingers snap back, and the surge current applied to the input / output pads is reliably released to the ground potential wiring.

  Next, the effect of this embodiment will be described. In the present embodiment, in the drain region 5, the edge 7 a of the central region 7 is in a position that is recessed from the edge 6 a of the end region 6 and the edge 4 a of the source region 4. Therefore, there is no current path that linearly connects from the contact region 8 to the region where the edge 6a of the end region 6 and the channel region intersect, and the current flowing through the end in the direction 12 of the central region 7 does not exist. When it flows into the end region 6, it spreads in the direction 12. As a result, current does not concentrate at the end in the direction 12 of the end region 6. As a result, the end of the drain region 5 is not thermally destroyed.

  In the present embodiment, since the drain resistance value can be controlled simply by selecting the length L1, the lengths L1 and L2 can be determined independently of each other. For this reason, it is easy to adjust the drain resistance value after layout, for example, by increasing the resistance value of fingers that tend to concentrate current, such as fingers positioned at both ends of the multi-finger structure. Further, since it is not necessary to consider the current concentration at the end of the drain region when designing the device, the value of the length L2 may be set to the optimum value for the central portion of the drain region. That is, it is not necessary to set the length L2 to be large in consideration of the current concentration at the end, and the optimum value of the length L2 can be easily determined. For this reason, element design is easy.

  Furthermore, in this embodiment, since the area of the drain region can be reduced, the ESD protection element 1 can be reduced in size and the parasitic capacitance can be reduced.

  Even if the shape of the silicon blocking region 15 is rectangular at the design stage, the corner portion of the silicon blocking region 15 is rounded to some extent when actually manufactured. For this reason, current does not normally concentrate on the corner portion. However, as a precaution, the corner may be dropped to 45 °. Further, when the width L4 of the end portion of the region 13 is made smaller than the width L3 of the central portion of the region 13, for example, about 0.2 μm, the resistance value of the end portion of the region 13 increases and the end portion of the region 13 is increased. It is possible to more reliably suppress the current from concentrating on.

  Next, a first modification of the present embodiment will be described. FIG. 2.1 is a plan view showing an ESD protection element according to this modification. As shown in FIG. 2.1, in this modification, the length of the region 14 in the direction 12 is equal to the length of the region 13, and the shape of the region 13 is rectangular. As a result, the silicon blocking region 15 reaches the edge in the direction 12 of the drain region 5. Other configurations and operations in the present modification are the same as those in the first embodiment described above.

  Next, a second modification of the present embodiment will be described. FIG. 2.2 is a plan view showing an ESD protection element according to this modification. As shown in FIG. 2.2, in this modification, the end region 6 of the drain region 5 is not divided into regions 13 and 14, and a silicide layer is formed on the entire surface of the end region 6. Further, the ballast resistor region 9 is divided into a region 9 a in contact with the end region 6 and a region 9 b in contact with the contact formation region 8. A silicide layer is formed on the surface of the region 9a, and no silicide layer is formed on the surface of the region 9b. That is, in this modification, the region 9 b is the silicide blocking region 15. The length of the region 9a in the direction 11 is 0.3 μm, for example. Other configurations and operations in the present modification are the same as those in the first embodiment described above.

Normally, the silicide layer is formed by sputtering or the like, but the silicide blocking region 15 is set by preventing the silicide layer from being formed in a predetermined region using the silicon oxide film as a mask. Therefore, usually, when patterning the silicon oxide film with a resist, misalignment, that is, misalignment of the pattern position occurs, so that the overlap between the end of the N ⁺ region serving as the base and the end of the silicide blocking region occurs. The portion or the clearance portion is inevitably generated, and the above-described first and second modifications are generated. As described above, in this specification, a region in which no silicide layer is formed is referred to as a silicide blocking region.

  Next, a third modification of the present embodiment will be described. FIG. 2.3 is a plan view showing an ESD protection element according to this modification. As shown in FIG. 2.3, in this modification, in the central region 7 of the drain region 5, both end edges in the direction 12 of the contact formation region 8 do not reach both end edges of the drain region 5. 9 is formed in a frame shape so as to surround the contact formation region 8. Further, in the ballast resistor region 9, a frame-shaped low concentration N-type region 18 is provided so as to surround the contact formation region 8. The low-concentration N-type region 18 is formed in the NLDD formation step in the semiconductor device manufacturing process, and its impurity concentration is lower than the concentration of other regions in the drain region 5. Further, the corners of the low-concentration N-type region 18 are angled so as to form an angle of 45 ° with respect to the directions 11 and 12. Furthermore, the width L5 in the direction 11 in the low concentration N-type region 18 is, for example, about 0.5 μm.

  The above-mentioned Patent Document 1 (US Pat. No. 5,498,892) discloses a technique for providing a low concentration N-type region in the drain region. In this technique, the low concentration N-type region is provided over the entire width of the drain region. ing. For this reason, the low-concentration N-type region is in contact with the element isolation region, and it becomes extremely difficult to control the resistance value at the junction surface. As a result, only the joint surface has a low resistance value or a strong electric field, and current may flow excessively in that region. On the other hand, in the present modification, the width in the direction 12 of the low-concentration N-type region 18 is made larger than the width in the direction 11, so that current can be prevented from concentrating at both ends of the drain region 5. . For this reason, an electric current does not flow excessively on the joint surface. Other configurations and operations in the present modification are the same as those in the first embodiment described above.

  Next, a second embodiment of the present invention will be described. FIG. 3 is a plan view showing the ESD protection element according to this embodiment. As shown in FIG. 3, in the ESD protection element according to the present embodiment, not the STI region but the low concentration region 21 is formed in the recess 5a. The low concentration region 21 is a region into which, for example, an N-type impurity is implanted, and the impurity concentration is lower than the impurity concentration of the drain region 5, and therefore the resistance value of the low concentration region 21 is the drain region. The resistance value is higher than 5. The configuration other than the above in the present embodiment is the same as that of the first modification (see FIG. 2.1) of the first embodiment described above.

  In the present embodiment, since the low concentration region 21 is provided in the recess 5a, the heat dissipation efficiency is higher than that in the first embodiment. For this reason, even if the amount of heat generated by the transistor increases, for example, when the current is concentrated at both ends of the transistor constituting the finger and when the width of the transistor is narrow and the area of the recess 5a is relatively large, Since the generated heat is conducted to the substrate through the low concentration region 21, an excessive temperature rise can be prevented. Other configurations, operations, and effects of the present embodiment are the same as those of the first embodiment. Note that a p-type impurity may be implanted into the low concentration region 21. Further, the shape of the silicide blocking region may be the same as that in the first embodiment or its modification.

Next, a third embodiment of the present invention will be described. FIG. 4 is a plan view showing the ESD protection element according to this embodiment. As shown in FIG. 4, in the ESD protection element according to the present embodiment, a rectangular p ⁺ region 22 is formed in the recess 5 a of the drain region 5 on the surface of the P well 2 in plan view. The p ⁺ region 22 is surrounded by the STI region 17, thereby being electrically isolated from the drain region 5, and the bottom surface is connected to the P well 2. Then, and two p ⁺ regions 22 provided on each finger pair, p ⁺ region 22 provided in each finger pair are connected to each other by an upper wiring (not shown). Other configurations in the present embodiment are the same as those in the first embodiment.

In the present embodiment, the p ⁺ region 22 functions as a tap for picking up the potential of the P well 2. Thereby, the potential of the P well 2 can be made uniform between the finger pairs. As a result, when one finger snaps back, the potential in the vicinity of this finger in the P well 2 rises. This potential rise is caused by the other finger in the P well 2 via the p ⁺ region 22 and the upper wiring. It is transmitted to the vicinity, and it becomes easy for other fingers to snap back. This is sometimes referred to as soft ground. As a result, since all the fingers snap back reliably, the protection performance against ESD can be improved.

U.S. Pat. No. 6,583,972 discloses an ESD protection element that realizes a soft ground, and discloses a technique in which a tap is provided outside the ESD protection element. However, a layout area corresponding to the provision of the tap is required. On the other hand, in this embodiment, since the tap (p ⁺ region 22) is provided in the recess 5a, the area efficiency is better than in the case where the tap is provided outside the ESD protection element.

Note that the p ⁺ region 22 may be connected to the gate electrode 3 of each finger. Further, the p ⁺ regions 22 of the plurality of fingers do not necessarily have to be connected to each other by the upper layer wiring. This is because by providing the p ⁺ region 22 in the recess 5a of the drain region 5, the substrates of the fingers that make a pair are connected to each other via the p ⁺ region 22 and a silicide layer (not shown). ^This is because the substrate potential can be made uniform between the paired fingers even if the ⁺ regions 22 are not connected to each other by the upper layer wiring. Operations and effects other than those described above in the present embodiment are the same as those in the first embodiment described above.

Next, a fourth embodiment of the present invention will be described. FIG. 5 is a plan view showing the ESD protection element according to this embodiment. As shown in FIG. 5, in the ESD protection element according to this embodiment, a low concentration region 23 is formed between the p ⁺ region 22 and the drain region 5. The shape of the low concentration region 23 is a U shape in plan view, and an N-type impurity having a concentration lower than that of the drain region 5 is implanted. The p ⁺ region 22 includes a U-shaped region 22a in contact with the low concentration region 23 and a rectangular region 22b surrounded on three sides by the region 22a, and a silicide layer is formed on the surface of the region 22a. In addition, a silicide layer is formed on the surface of the region 22b.

In the present embodiment, since the p ⁺ region 22 is thermally connected to the drain region 5 through the low concentration region 23, the heat dissipation efficiency is higher than that in the third embodiment. In addition, since the diode resistance is low between the p ⁺ region 22 and the drain region 5, the potential of the drain region 5 is easily transmitted to the p ⁺ region 22, and therefore, the potential is easily made uniform between the fingers. As a result, compared to the third embodiment described above, the soft ground effect that keeps the potential between fingers the same is high. Configurations, operations, and effects other than those described above in the present embodiment are the same as those in the third embodiment described above.

  Next, a fifth embodiment of the present invention will be described. FIG. 6 is a plan view showing the ESD protection element according to this embodiment. As shown in FIG. 6, in the ESD protection element according to the present embodiment, the extended portion 24 that extends from the region 13 into the recess 5 a with respect to the ESD protection element according to the first embodiment described above. Is different. The extension 24 is formed integrally with the region 13 and is a part of the drain region 5. That is, the drain region 5 includes an extending portion 24 that extends from each region 13 in a direction toward another region 13 belonging to the same drain region 5 as the region 13.

  In addition, an STI region 17 is formed in a region where the extended portion 24 is not formed in the recess 5a. Furthermore, in the ESD protection element in the present embodiment, the silicon blocking region 15 is formed in a frame shape, in addition to the ballast resistor region 9 and the region 13, a region facing the central region 7 in the extending portion 24, and Both end portions in the direction 12 of the contact formation region 8 are also silicon blocking regions 15. Other configurations in the present embodiment are the same as those in the first embodiment.

  In the present embodiment, the heat generated near the boundary between the drain region 5 and the channel region is transferred to the extension portion 24 and diffuses from the extension portion 24 to the P-type silicon substrate, thereby increasing the temperature near the boundary. Can be prevented. Operations and effects other than those described above in the present embodiment are the same as those in the first embodiment described above. In the second and fourth embodiments described above, the same heat dissipation effect as in this embodiment can be obtained.

  In the present embodiment, the silicon blocking region 15 may be extended along the direction 12 so that the entire extending portion 24 is included in the silicon blocking region 15. Further, a low concentration region similar to the low concentration region 21 (see FIG. 3) may be provided in place of the STI region 17 in the region where the extension 24 in the recess 5a is not formed.

Next, a sixth embodiment of the present invention will be described. FIG. 7 is a plan view showing the ESD protection element according to this embodiment. As shown in FIG. 7, in the present embodiment, the p ⁺ region 22 is formed larger than the third embodiment described above. Further, a plurality of contacts 26 are provided in one row along the direction 12 on the end region 6, and a plurality of contacts 26 provided on one end region 6 are provided on the contact 26. They are connected to each other by metal wiring 27. Other configurations in the present embodiment are the same as those in the third embodiment described above.

In the third embodiment described above, when the p ⁺ region 22 for picking up the P well potential is formed large, the depth of the recess 5a, that is, the length L2 is increased, so that the current extending in the direction 12 in the end region 6 is increased. The resistance of the path increases. For this reason, the current is less likely to flow through both end portions in the width direction 12 of the end region 6 and is concentrated in the central portion. On the other hand, in this embodiment, since the contact 26 and the metal wiring 27 are provided on the end region 6, the resistance in the direction 12 of the end region 6 decreases, and the current flows uniformly in the width direction. Can do. As a result, the protection performance against ESD is improved. Operations and effects other than those described above in the present embodiment are the same as those in the third embodiment described above.

  In each of the above-described embodiments, the N-channel MOS type ESD protection element formed on the surface of the silicon substrate has been described. However, the present invention is not limited to this, and for example, the N-channel MOS type ESD protection element formed on the surface of the SOI substrate. It may be a channel MOS type ESD protection element, or may be a P channel MOS type ESD protection element formed on the surface of a silicon substrate or SOI substrate. Further, the type of the protective element is not limited to the input / output protective element, and may be various protective elements such as a power supply protective element. Further, the MOS transistor constituting the ESD protection element may be a ggMOS (gate-grounded MOS) whose gate is connected to the ground electrode through a resistor, and is a gate-coupled structure or a dynamic-gate-floating. A transistor having a structure in which the gate potential is controlled by a surge current, such as a structure, may be used.

It is a top view which shows the ESD protection element which concerns on the 1st Embodiment of this invention. It is a top view which shows the ESD protection element which concerns on the 1st modification of this 1st Embodiment. It is a top view which shows the ESD protection element which concerns on the 2nd modification of this 1st Embodiment. It is a top view which shows the ESD protection element which concerns on the 3rd modification of this 1st Embodiment. It is a top view which shows the ESD protection element which concerns on the 2nd Embodiment of this invention. It is a top view which shows the ESD protection element which concerns on the 3rd Embodiment of this invention. It is a top view which shows the ESD protection element which concerns on the 4th Embodiment of this invention. It is a top view which shows the ESD protection element which concerns on the 5th Embodiment of this invention. It is a top view which shows the ESD protection element which concerns on the 6th Embodiment of this invention. It is a top view which shows the input protection element using the snapback phenomenon of NMOSFET which is the conventional MOS type protection element. It is a figure which shows the cross section and the equivalent circuit by the A-A 'line shown in FIG. It is a graph showing the operating characteristics of this MOS type protection element, with the voltage applied to the protection element on the horizontal axis and the current flowing through the protection element on the vertical axis. It is a top view which shows the conventional ESD protection element described in patent document 2. FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1; ESD protection element 2; P well 3; Gate electrode 4; Source region 4a; Edge 5; Drain region 5a; Concave part 6; End region 6a; Edge 7: Central region 7a; 9; Ballast resistance region 9a, 9b; Region 10; Contact 11; Arrangement direction of gate electrode 3 12; Longitudinal direction of gate electrode 3 13: Region closer to channel region 14; Region far from channel region 15; Blocking region 16; contact 17; STI region 18; low concentration N-type region 21; low concentration region 22; p ⁺ region 22a, 22b; region 23; low concentration region 24; extension 26; contact 27; MOS type protection element 102; P type substrate 103; Gate electrode 104; Channel region 105; Source region 106; Drain region 107; contact 108; guard ring 109; ground wiring 110; input pad 111; MOSFET
112, 113; line 122; substrate 123; gate electrode 124; source region 125; drain region 126; contact 127; silicide blocking region 131, 132;

Claims (7)

A substrate having a first conductivity type region formed on at least a part of the surface, and a channel region formed alternately and along the first direction on the surface of the first conductivity type region. First and second second conductivity type regions, wherein the first second conductivity type region is two first regions provided at positions facing the second second conductivity type region. And a second region which is a region between the two first regions and whose end edge extending in the first direction is recessed from the end edge extending in the first direction in the first region; In the recess of the first second conductivity type region formed by the first region and the second region, the impurity concentration is lower than the impurity concentration of the first second conductivity type region. An electrostatic discharge protection element having a region formed therein . The first conductivity type region is electrically isolated from the first second conductivity type region in the recess of the first second conductivity type region formed by the first region and the second region, and is connected to the first conductivity type region. in position, the electrostatic discharge protection device according to claim 1, wherein the other of the first conductivity type region is formed. Wherein the other of the first conductivity type region formed in the recess of the first second conductivity type region, a first conductivity of the other formed in the recess of the other of said first second-conductivity-type region The electrostatic discharge protection element according to claim 2 , wherein the electrostatic discharge protection element is connected to a mold region. An insulating film is formed between the first second conductivity type region and the other first conductivity type region formed in the recess of the first second conductivity type region. The electrostatic discharge protection element according to claim 2 or 3 . An impurity concentration between the first second conductivity type region and the other first conductivity type region formed in the recess of the first second conductivity type region is the first second conductivity type. electrostatic discharge protection device according to claim 2 or 3, characterized in that the low concentration region is formed lower than the impurity concentration in the region. 2. The electrostatic discharge protection element according to claim 1, wherein the first second conductivity type region has an extending portion extending in a direction from each first region toward the other first region. . A plurality of contacts provided on the first region and connected to the first region and arranged in a second direction orthogonal to the first direction; and a wiring for connecting the plurality of contacts to each other. The electrostatic discharge protection element according to any one of claims 1 to 6 .

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