JP5370136B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a source region and a drain region formed in a surface region of a semiconductor substrate and extending opposite to each other.

  Conventionally, step-down DC / DC converters using LDMOS (Laterally Diffused Metal Oxide Semiconductor) are known.

  FIG. 7 is a diagram showing an example of a circuit diagram of a step-down DC / DC converter using a conventional LDMOS. 7, the step-down DC / DC converter includes a low-potential side LDMOS 300, a high-potential side LDMOS 301, a control unit 330 that controls the low-potential side LDMOS 300, and a control unit 331 that controls the high-potential side LDMOS 301. . Both the low potential side LDMOS 300 and the high potential side LDMOS 301 are n-channel LDMOSs, and the drain of the low potential side LDMOS 300 and the source of the high potential side LDMOS 301 are connected to form a switch terminal SW. The low-potential side LDMOS 300 and the high-potential side LDMOS 301 each have a drain-back gate parasitic diode 310, 311 and a drain-semiconductor substrate parasitic diode 320, 321. In addition, as an external component, a coil 340 and a capacitor 350 are connected to the switch terminal SW.

  In such a step-down DC / DC converter, two LDMOSs 300 and 301 are driven by separate control circuits 330 and 331 on the low potential side and the high potential side to control the current to the coil 340, thereby realizing a step-down operation. To do. First, when the LDMOS 301 on the high potential side is ON, the current I1 flows into the coil 340. At this timing, when the power supply Vdd of the entire circuit is shut down, the path of the current I1 is cut off. Here, since the coil 340 has a property of continuing a current flow, the current I2 flows out through the parasitic diode 310 of the LDMOS 300 on the low potential side and the current I3 flows out through the parasitic diode 320.

  FIG. 8 is a diagram showing an example of the configuration of conventional LDMOSs 300 and 301 formed on the semiconductor substrate 210. 8A is an example of a plan configuration diagram of the LDMOSs 300 and 301, and FIG. 8B is an example of a cross-sectional configuration diagram of the LDMOSs 300 and 301. FIG.

  8A, conventional LDMOSs 300 and 301 have a source region 220, drain regions 230 and 231, a gate 240, a back gate 250, a LOCOS (Local Oxidation of Silicon) 260 on a semiconductor substrate 210. And a substrate electrode 280. In conventional LDMOS 300 and 301, the source region 220 and the drain region 230 extend in parallel, and a gate 240 extends between the source region 220 and the drain region 230 so as to be adjacent to the source region 220. Is provided. Further, a back gate region 250 is provided so as to surround the adjacent source regions 220 facing each other between the two gates 240. The other space is covered with the LOCOS 160 and the outer periphery is surrounded by the substrate electrode 280. One set of the above-described gate 240, source region 220 and drain region 230, or one set of the gate 240, source region 220 and drain region 231 constitutes one transistor cell. Therefore, the LDMOSs 300 and 301 in FIG. 8 include four transistor cells. In addition, in the source region 220, the drain regions 230 and 231, the back gate region 250, and the substrate electrode 280, the formation positions of contact holes 225, 235, 236, 255, and 285 for energizing are shown.

  FIG. 8B shows a cross-sectional configuration of conventional LDMOSs 300 and 301, but an n layer 215 is formed on a p-type silicon substrate 210. Drain regions 230 and 231 and a back gate region 250 are formed in the surface region of the n layer 215, and source regions 220 are formed on both ends of the surface of the back gate region 250. LOCOS 260 is formed on both sides of the drain regions 230 and 231 and is isolated. An oxide film 290 is formed on the surfaces of the source region 220, the drain region 230, and the back gate region 250, and a gate 240 is formed on the oxide film 290 adjacent to the source region 220 so as to straddle the LOCOS 260. ing. Substrate electrodes 280 are formed in the surface region of the semiconductor substrate 210 further outside the LOCOS 260 at both ends of the n layer 215.

  Here, the semiconductor substrate 210 is configured as a p-type semiconductor, and the substrate electrode 280 and the back gate region 250 are configured as a p-type diffusion layer. The n layer 215, the source region 220, and the drain regions 230 and 231 are configured as an n-type diffusion layer. Therefore, the parasitic diode 310 is formed between the back gate region 250 and the drain regions 230 and 231, and the parasitic diode 320 is formed between the semiconductor substrate 210 and the drain regions 230 and 231. Such parasitic diodes 310 and 320 are necessarily formed due to the structure in the case of general n-channel LDMOSs 300 and 310. For example, when the LDMOS 300, 301 having such a configuration is used as a power transistor for the step-down DC / DC converter shown in FIG. 7, as described in FIG. 7, the high potential side LDMOS 300 is turned on. When the power source Vdd is switched to OFF, a current in the same direction as the current I1 tends to continue to flow through the coil 340. Then, in the low potential side LDMOS 300, the currents I2 and I3 indicated by the broken lines flow toward the drain region 230 by the parasitic diodes 310 and 320.

  As an invention related to LDMOS, source cells and drain cells are alternately arranged in the cell region in order to increase the surge withstand capability without lowering the withstand voltage, and the entire periphery of the cell region is terminated at the source cell. Thus, there is known an LDMOS having a configuration in which a surge current is dispersed inside a cell region when a surge enters from a drain (see, for example, Patent Document 1).

Japanese Patent Laid-Open No. 10-313064

  When the conventional LDMOS 300 and 301 described in FIG. 8 is used in the step-down DC / DC converter of FIG. 7 and the high potential LDMOS 301 is switched from ON to OFF, the current caused by the parasitic diode 310 of the low potential LDMOS 300 A relatively small current flows through I2, but a considerably large current flows through the current I3 generated by the parasitic diode 320. At this time, as shown in FIG. 8A, the current I3 flows into the drain region 230 from the side surface and the bottom surface of the semiconductor substrate 210, and the drain region 231 existing at both ends has the entire one surface of the drain region 231; Current I3 flows into both ends in the extending direction. In the drain region 231, all the contact holes 236 formed in the entire drain region 231 are used, so that the current I3 escapes to the wiring layer. However, the current I3 flows in a concentrated manner at both ends of the drain region 230, which is sandwiched between the gates 240 on both sides. At this time, there is a problem that the current I3 concentrates on the contact holes 235 formed at both ends, and the contact hole 235 or a wiring layer (not shown) connected thereto may be burned. It was. In this case, in FIG. 7, there is a problem that the wiring is burnt at the point of the contact D <b> 1 and the LDMOS 300 is destroyed.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device having a layout pattern that increases resistance to a reverse current.

In order to achieve the above object, a semiconductor device (100, 101, 102) according to a first invention is formed in a surface region of a semiconductor substrate (10) and extends oppositely, a source region (20) and a drain region. (30, 31, 32, 33) and the source region (20) between the source region (20) and the drain region (30, 31, 32, 33) formed on the surface of the semiconductor substrate (10). ) And a substrate electrode (80) surrounding the periphery of the plurality of transistor cells and defining a reference potential of the semiconductor substrate (10). In the semiconductor device (100, 101, 102),
On the extended line of the drain region between the substrate electrode and the end of the surface region of the semiconductor substrate (10) in the extending direction of the drain region sandwiched on both sides by the gate (40), A current concentration relaxation electrode (70, 71, 72) having the same potential as the drain region (30, 31, 32, 33) is provided.

  As a result, the backflow current that flows in a concentrated manner from the semiconductor substrate to the end portion of the drain region can be dispersed and flowed to the current concentration relaxation electrode, and the breakage of the wiring at the end portion of the drain region can be prevented.

A second invention is a semiconductor device (100, 101, 102) according to the first invention.
The current concentration relaxation electrode (70, 71, 72) extends in the direction perpendicular to the direction in which the drain region (30, 31, 32, 33) extends , and extends in the drain region (30, 31, 32, 33). The length is longer than the width perpendicular to the current direction .

  Thereby, the concentrated current to the drain region can be surely guarded by the current concentration relaxation electrode, and damage to the wiring at the end of the drain region can be reliably prevented.

According to a third invention, in the semiconductor device (100, 101, 102) according to the first or second invention,
The current concentration relaxation electrodes (70, 71, 72) are electrically connected to the drain regions (30, 31, 32, 33) by wiring layers (150, 151).

  Thereby, the current concentration relaxation electrode can be surely set to the same potential as the drain region by supplying power from the same power source.

According to a fourth invention, in the semiconductor device (100, 101, 102) according to the third invention,
The current concentration relaxation electrode (70, 71, 72) is provided on the surface region of the semiconductor substrate (10) continuously with the drain region (30, 31, 32, 33).

  Thereby, the drain region and the current concentration relaxation electrode can be set to the same potential also by the diffusion layer in the surface region of the semiconductor substrate.

A fifth invention is a semiconductor device (100) according to the fourth invention, wherein:
The current concentration relaxation electrode (70) is provided on the surface region of the semiconductor substrate (10) continuously with all the drain regions (30, 31), and the drain region (30, 31) and the current concentration are provided. A relaxation electrode (70) surrounds the gate (40) and the source region (20) in a plane.

  As a result, the concentration of the backflow current at the end of the drain region can be almost completely eliminated, and damage to the wiring portion at the end of the drain region can be reliably eliminated.

A sixth invention is a semiconductor device according to any one of the first to fifth inventions,
The drain region (30, 31, 32, 33) is composed of an n-type diffusion layer,
The substrate electrode (80) is composed of a p-type diffusion layer,
The current concentration relaxation electrodes (70, 71, 72) are formed of an n-type diffusion layer.

  Accordingly, in the n-channel semiconductor device that is frequently used, the end of the drain region can be prevented from being damaged.

  Reference numerals in parentheses are given for ease of understanding, are merely examples, and are not limited to the illustrated modes.

  According to the present invention, it is possible to reduce the concentration of the backflow current at the end of the drain region and to prevent the wiring portion at the end of the drain region from being damaged by the backflow current.

1 is a diagram illustrating an example of a planar configuration of a semiconductor device 100 according to Example 1. FIG. It is the figure which showed the cross-sectional structure of the A-A 'cross section of FIG. 6 is a diagram transparently showing an example of a planar configuration of a wiring layer 150 of the semiconductor device according to Example 1. FIG. FIG. 6 is a diagram illustrating an example of a planar configuration of a semiconductor device 101 according to a second embodiment. 7 is a diagram transparently showing an example of a planar configuration of a wiring layer 151 of a semiconductor device 101 according to Example 2. FIG. FIG. 6 is a diagram illustrating an example of a planar configuration of a semiconductor device 102 according to a third embodiment. It is the figure which showed the circuit diagram of the step-down DC / DC converter using the conventional LDMOS. It is the figure which showed an example of the structure on the semiconductor substrate 210 of conventional LDMOS300,301. 8A is an example of a plan configuration diagram of the LDMOSs 300 and 301, and FIG. 8B is an example of a cross-sectional configuration diagram of the LDMOSs 300 and 301. FIG.

  DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings.

  FIG. 1 is a diagram illustrating an example of a planar configuration of a semiconductor device 100 according to the first embodiment of the present invention. 1, a semiconductor device 100 according to the first embodiment includes a semiconductor substrate 10, a source region 20, drain regions 30 and 31, a gate 40, a back gate region 50, a LOCOS 60, and a current concentration relaxation electrode 70. And a substrate electrode 80. In addition, positions where the contact holes 25, 35, 36, 55, 75, and 85 are provided in the source region 20, the drain regions 30 and 31, the back gate region 50, and the current concentration relaxation electrode 70 are shown, respectively.

  The source region 20 and the drain regions 30 and 31 have an elongated rectangular shape and extend in parallel to face each other. A gate 40 is disposed between the source region 20 and the drain regions 30 and 31. The gate 40 is provided adjacent to the source region 20 and away from the drain region 30 so as to extend along the source region 20 in parallel with the source region 20 and the drain region 30. The back gate region 50 is provided between the adjacent source regions 20 facing each other, and has a shape and a width including the source region 20 in the extending direction. A LOCOS 60 is provided in a region between the gate 40 and the drain regions 30 and 31. One drain region 30 at the center is opposed to the gate 40 via the LOCOS 60, and both sides are disposed between the gates 40. On the other hand, the two drain regions 31 at both ends are opposed to the gate 40 through the LOCOS 60 on the center side, but are arranged to face the substrate electrode through the LOCOS 60 on the end side. The current concentration relaxation electrode 70 is provided so as to extend in a direction perpendicular to the extending direction of the drain region 30. Since the drain region 30 is a portion facing the source region 20 having the same length as the source region 20, the current concentration relaxation electrode 70 is elongated and linearly connected so as to be continuously connected to the drain region 30. It has a close E shape. Therefore, the current concentration relaxation electrode 70 is connected to both ends in the extending direction of all the drain regions 30 and 31 (three in FIG. 1) in the semiconductor device 100 and is formed continuously with the drain regions 30 and 31. Has been. The drain regions 30 and 31 and the current concentration relaxation electrode 70 surround the two gates 40 and the source region 20 and the one back gate region 50. Furthermore, the substrate electrode 80 surrounds the region surrounded by the drain region 31 at both ends in the longitudinal direction of the semiconductor device 100 and the current concentration relaxation electrode 70 via the LOCOS 60, thereby forming the semiconductor device 100. Yes.

  Here, the gate 40, the source region 20 and the drain regions 30 and 31 on both sides of the gate 40, and the back gate 50 constitute one transistor cell. Therefore, the semiconductor device 100 illustrated in FIG. 1 includes four transistor cells. That is, one drain region 31 at both ends corresponds to one transistor cell, but one central drain region 30 also serves as the drain region 30 of two transistor cells.

  Next, individual components will be described.

  The semiconductor substrate 10 is a substrate on which the semiconductor device 100 according to the present embodiment is formed. As the semiconductor substrate 10, a substrate made of various semiconductor materials may be used. For example, a silicon substrate may be used. The semiconductor substrate 10 is configured as a p-type semiconductor substrate when the semiconductor device 100 is configured as an n-channel LDMOS.

  The source region 20 is a diffusion layer formed in the surface region of the semiconductor substrate 10 and functions as a source of the semiconductor device 100 configured as an LDMOS. Note that the surface region of the semiconductor substrate 10 means a region on the surface side including the surface of the semiconductor substrate 10, and an insulating film such as an oxide film is formed on the source region 20, or a metal, polysilicon, or the like is formed. A conductive film may be formed.

  An insulating layer is formed above the source region 20, and a wiring layer made of metal is formed above the insulating layer. A plurality of contact holes 25 are formed in the insulating layer for electrical connection with the wiring layer. The position of the contact hole 25 is shown in FIG.

  The source region 20 is formed of an n-type diffusion layer when the semiconductor device 100 is configured as an n-channel LDMOS.

  The drain regions 30 and 31 are diffusion layers formed in the surface region of the semiconductor substrate 10 and function as the drain of the semiconductor device 100 configured as an LDMOS. In the vertical MOS transistor, the drain is formed on the back surface of the semiconductor substrate 10. However, since the semiconductor device 100 according to this embodiment is configured as a horizontal MOS transistor, the drain regions 30 and 31 are formed on the semiconductor substrate 100. Formed in the surface region.

  The drain regions 30 and 31 are formed as a diffusion layer continuous with the current concentration relaxation electrode 70, but the portion that functions as the drain of the LDMOS is the portion facing the source region 20. Therefore, even if it is formed continuously with the current concentration relaxation electrode 70, it is functionally distinguished from the current concentration relaxation electrode 70.

  The drain region 30 is a drain region sandwiched between the gates 40 via the LOCOS 60 in a plan configuration. In FIG. 1, one drain region 30 existing in the center corresponds. However, when the number of transistor cells is larger than that in the configuration of FIG. 1, all the drain regions 30 except for the two drain regions 31 at both ends are sandwiched between the gates 40, and there are a plurality of drain regions 30. Will do. Also in the drain region 30, an insulating layer is formed as an upper layer, and a metal wiring layer is formed as an upper layer of the insulating layer, and a plurality of contact holes 35 for electrical connection are formed in the insulating layer. In FIG. 1, the position of the contact hole 35 is shown.

  The drain region 31 is a drain region 31 of a transistor cell that exists at both ends of the plurality of transistor cells arranged in the longitudinal direction of the semiconductor device 100, and one side in the extending direction faces the gate 40, and the other This side is the drain region 31 facing the substrate electrode 80. Therefore, when the transistor cells are arranged in one column, two drain regions 31 are provided for each column. Also in the drain region 31, a plurality of contact holes 36 are formed in the same manner as the contact holes 35, and electrical connection with the upper wiring layer is performed. Further, the drain region 30 and the drain region 31 are connected by the same wiring layer, and the drain regions 30 and 31 are configured to have the same potential.

  The drain regions 30 and 31 are configured as n-type diffusion layers when the semiconductor device 100 is configured as an n-channel LDMOS.

  The gate 40 is an electrode formed on the surface of the semiconductor substrate 10 and functions as an LDMOS gate.

  The back gate region 50 is a diffusion layer formed in the surface region of the semiconductor substrate 10 and is configured as a body region for the source region 20. Therefore, the back gate region 50 is configured to cover the side surface and the bottom surface of the source region 20 from the side and below.

  FIG. 2 is a diagram showing a cross-sectional configuration of the A-A ′ cross section of FIG. 1. As shown in FIG. 2, it can be seen that the back gate region 50 is configured to cover the side surface and bottom surface of the source region 20 from the side and from below. 2 also shows that the gate 40 described above is formed on the surface of the semiconductor substrate 10 so as to straddle the oxide film 90 and the LOCOS 60. FIG.

  Returning to FIG. In the back gate region 50, similarly to the source region 20, an insulating layer is formed on the upper layer, a wiring layer is further formed on the insulating layer, and a plurality of contact holes 55 are formed on the insulating layer. In FIG. 1, the position of the contact hole 55 is shown. In general, the back gate region 50 and the source region 20 are often supplied with the same potential. Therefore, the back gate region 50 and the source region 20 may be connected to the same wiring layer and supplied with the same potential. The supplied potential may be, for example, 0 V of the ground potential.

  The back gate region 50 is configured as a p-type diffusion layer when the semiconductor device 100 is configured as an n-channel LDMOS.

  The LOCOS 60 is an insulating film for insulating and separating the drain region 30 in the lateral direction, and is provided so as to sandwich the drain region 30 from both sides. Further, the LOCOS 60 surrounds the drain region 30 from both ends in the extending direction, and is insulated and isolated from other diffusion layers.

  The current concentration relaxation electrode 70 is a diffusion layer that guards both ends of the drain region 30 in the extending direction and relaxes the backflow current. Similar to the drain region 30, the current concentration relaxation electrode 70 is provided in the surface region of the semiconductor substrate 10. The current concentration relaxation electrode 70 extends in a direction perpendicular to the extending direction of the drain regions 30 and 31 in a plan configuration, is provided between the drain regions 30 and 31 and the substrate electrode 80, and It is formed by being continuously connected to both end portions of 30,31. Thus, the backflow current I3 flowing from the semiconductor substrate 10 toward the drain region 30 is sucked up by the current concentration relaxation electrode 70 before reaching the drain region 30, and the backflow current to the contact hole 35 at the end of the drain region 30 is absorbed. Concentration can be avoided. Further, in the configuration of FIG. 1, the current concentration relaxation electrode 70 also relaxes the backflow current to the end of the drain region 31.

  Similar to the drain region 30, a wiring layer is formed over the current concentration relaxation electrode 70 via an insulating layer, and a plurality of contact holes 75 are formed in the insulating layer. Since the plurality of contact holes 75 are densely formed along the extending direction of the current concentration relaxation electrode 70, the backflow current I 3 flowing into the end of the drain region 30 is caused to flow into each contact hole 75 of the current concentration relaxation electrode 70. The current can be passed through the wiring layer and the current can be dispersed by the plurality of contact holes 75.

  In FIG. 1, the reverse current I3 is indicated by a broken-line arrow, but both end portions of the drain region 30 sandwiched by the center gate 40 are guarded by the current concentration relaxation electrode 70, and the concentration of the reverse current I3 is reduced. It has been avoided. Further, since the current concentration relaxation electrode 70 and the drain region 31 are formed so as to face the substrate electrode 80, the backflow current I3 does not concentrate on any part, but the current concentration is almost uniform throughout. It flows into the relaxation electrode 70 and the drain region 31. As described above, in the semiconductor device 100 according to the first embodiment, the current concentration relaxation electrode 70 is disposed on the extension line in the extending direction of the drain region 30 between the end portion in the extending direction of the drain region 30 and the substrate electrode 80. By forming a diffusion layer that is present in the region and continuous with the drain regions 30 and 31, the concentration of the backflow current I3 at the end of the central drain region 30 can be reliably mitigated.

  The substrate electrode 80 is an electrode for determining the reference potential of the semiconductor substrate 10 and is supplied with the reference potential. Usually, the reference potential may be set to 0 V of the ground potential. The substrate electrode 80 surrounds a plurality of transistor cells and constitutes one semiconductor device 100. Then, a reference potential is supplied to the semiconductor device 100.

  An insulating layer is formed on the substrate electrode 80, and a metal wiring layer is further formed on the insulating layer. A plurality of contact holes 85 are formed in the insulating layer, and the reference potential of the semiconductor substrate 10 is supplied to the substrate electrode 80 from the wiring layer through the contact holes 85. FIG. 1 shows the position of the contact hole 85, and the contact hole 85 is formed over four sides of the substrate electrode 80.

  The substrate electrode 80 is configured as a p-type diffusion layer when the semiconductor device 100 according to the present embodiment is configured as an n-channel LDMOS.

  FIG. 2 is a diagram showing a configuration in the A-A ′ cross section of FIG. 1. In FIG. 2, the same reference numerals are assigned to the components described in FIG. Hereinafter, only the points not described in FIG. 1 will be described.

  In FIG. 2, an n layer 15 is formed in a region inside the substrate electrode 80 of the semiconductor substrate 10, and a transistor cell is formed in a surface region of the n layer 15. The n layer 15 is configured as a diffusion layer having a lower concentration than the source region 20, the drain region 30, and the current concentration relaxation electrode 70. The n layer 15 may be a well layer, an epitaxial growth layer, or a diffusion layer formed by another manufacturing method.

  The surface of the n layer 15 including the source region 20, the drain region 30, the back gate region 50 and the current concentration relaxation electrode 70, that is, the region not covered with the LOCOS 60 is covered with the oxide film 90. When forming the contact holes 25, 35, 36, 55, 75, the oxide film 90 at the position where the contact holes 25, 35, 36, 55, 75 are formed is removed, and the contact holes 25, 35, 36, It forms so that electrical connection with 55 and 75 and each diffusion region may be performed appropriately.

  A parasitic diode 110 is formed between the back gate region 50 and the drain region 30, and a parasitic diode 120 is formed between the semiconductor substrate 10 and the drain region 30. As described with reference to FIG. 8, the influence of the current I2 flowing through the parasitic diode 110 is conventionally small. On the other hand, the influence of the current I3 flowing through the parasitic diode 120 has hitherto been large in the central drain region 30 sandwiched between the gates 40 on both sides. However, in the semiconductor device 100 according to the present embodiment, the current concentration relaxation electrode 70 is It has become smaller by providing it. As shown in FIG. 2, it can be seen that the current I3 flows only from the lower side of the semiconductor substrate 10.

  As described above, in the semiconductor device 100 according to the present embodiment, the backflow current I3 can be prevented from being concentrated on the end of the drain region 30 sandwiched between the gates 40, and the semiconductor device 100 can be prevented from being damaged. Can do.

  FIG. 3 is a diagram transparently showing an example of a planar configuration of the wiring layer 150 provided in the upper layer of the semiconductor substrate 10 of the semiconductor device 100 according to the first embodiment. In FIG. 3, the wiring layer 150 includes a source wiring layer 110, a drain wiring layer 120, and a substrate electrode wiring layer 130. For the source wiring layer 110, the drain wiring layer 120, and the substrate electrode wiring layer 130, a metal used as a wiring material such as aluminum or copper is used.

  The source wiring layer 110 is a wiring for supplying power to the source region 20 and the back gate region 50. The source wiring layer 110 is provided in a rectangular shape so as to cover the contact hole 25 in the source region 20 and the contact hole 55 in the back gate region 50 from above.

  The drain wiring layer 120 is a wiring layer for supplying power to the drain regions 30 and 31 and the current concentration relaxation electrode 70. The drain regions 30 and 31 and the power concentration relaxation electrode 70 are supplied with the potential from the same drain wiring layer 120 so that they all have the same potential. The drain wiring layer 120 covers all of the contact hole 35 of the drain region 30, the contact hole 36 of the drain region, and the contact hole 70 of the current concentration relaxation electrode 70, and surrounds the source wiring layer 110 without contact. It is provided in the shape of figure 8.

  The substrate electrode wiring layer 130 is a wiring layer for supplying a reference potential to the substrate electrode 80, and is provided in a frame shape so as to cover the contact hole 85 of the substrate electrode 80 from above.

  Thus, according to the semiconductor device 100 according to the present embodiment, the drain regions 30 and 31 and the current concentration relaxation electrode 70 are supplied with power from the same drain wiring layer 120 in the wiring layer 150 on the upper layer of the semiconductor substrate 10. Thus, the drain regions 30 and 31 and the current concentration relaxation electrode 70 can be easily set to the same potential.

  In FIG. 3, the pattern of the wiring layer 150 is formed so as to conform to the planar configuration of FIG. 1. However, if the planar configuration of FIG. 1 changes, the pattern of the wiring layer 150 may change accordingly. Needless to say.

  According to the semiconductor device 100 according to the first embodiment, the end portion of the drain region 30 sandwiched between the gates 40 on both sides in the extending direction is the current concentration relaxation electrode 70 formed continuously with the drain regions 30 and 31. Since it is completely guarded, it is possible to prevent the backflow current I3 from concentrating on the end of the drain region 30, and to prevent the semiconductor device 100 from being damaged by the induced current.

  FIG. 4 is a diagram illustrating an example of a planar configuration of the semiconductor device 101 according to the second embodiment of the present invention. In the semiconductor device 101 according to the second embodiment, the same components as those of the semiconductor device 100 according to the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.

  Specifically, the semiconductor device 101 according to the second embodiment includes a semiconductor substrate 10, a source region 20, a gate 40, a back gate region 50, a LOCOS 60, a substrate electrode 80, and contact holes 25, 55, and 85. Are the same constituent elements as those of the semiconductor device 100 according to the first embodiment, and the arrangement thereof is also the same.

  The semiconductor device 101 according to the second embodiment is related to the first embodiment in that the drain regions 32 and 33 and the current concentration relaxation electrode 71 are separately formed independently and are not formed continuously. Different from the semiconductor device 100. However, the current concentration relaxation electrode 71 extends in a direction perpendicular to the extending direction of the source region 20 and the drain region 32, and exists between the end portion of the extending direction of the drain region 30 and the substrate electrode 80. In common, the semiconductor device 100 according to the first embodiment is common.

  As described above, the drain regions 32 and 33 and the current concentration relaxation electrode 71 are not necessarily formed continuously in the surface region of the semiconductor substrate 10. Even in this case, the current concentration relaxation electrode 71 guards the backflow current I3 that flows from the semiconductor substrate 10 to both ends of the drain region 32, and the backflow current I3 flows to the drain region 32 via the plurality of contact holes 76. Since the backflow current is sucked up before reaching, concentration of current in the contact holes 37 at both ends of the drain region 32 can be avoided.

  The current concentration relaxation electrode 71 has a long and narrow rectangular shape, and extends so as to guard all the drain regions 32 and 33 in the longitudinal direction of the semiconductor device 100. In addition, a plurality of contact holes 76 are densely formed on the current concentration relaxation electrode 71 along the extending direction of the current concentration relaxation electrode 71, and the backflow current I3 is distributed to flow through the wiring layer. It is configured to be possible.

  FIG. 5 is a diagram transparently showing an example of a planar configuration of the wiring layer 151 formed on the semiconductor substrate 10 of the semiconductor device 101 according to the second embodiment. In FIG. 5, the wiring layer 151 includes a source wiring layer 111, a drain wiring layer 121, and a substrate electrode wiring layer 131. The source wiring layer 111 is a wiring layer that supplies power to the source region 20 and the back gate region 50, and the drain wiring layer 121 is a wiring layer that supplies power to the drain regions 32 and 33 and the current concentration relaxation electrode 71. The point is the same as in the first embodiment. The substrate electrode wiring layer 131 is the same as the first embodiment in that the substrate electrode wiring layer 131 is a wiring layer that applies a reference potential to the substrate electrode 81.

  The drain wiring layer 121 covers all of the contact hole 37 formed on the drain region 32, the contact hole 38 formed on the drain region 33, and the contact hole 76 formed on the current concentration relaxation electrode 71. It is formed as follows. That is, the drain regions 32 and 33 and the current concentration relaxation electrode 71 are electrically connected via the drain wiring layer 121 and have the same potential. Thus, even if the drain regions 32 and 33 and the current concentration relaxation electrode 71 are not connected in the surface region of the semiconductor substrate 10, the drain regions 32 and 33 and the current concentration are separated by the upper drain wiring layer 121. The relaxing electrode 71 can be set to the same potential.

  The configurations of the drain regions 32 and 33 and the current concentration relaxation electrode 71 in the surface region of the semiconductor substrate 10 are slightly different from those in the first embodiment, but the overall arrangement is substantially the same. As a result, the arrangement of the contact holes 37, 38, and 76 is substantially the same as that of the semiconductor device 100 according to the first embodiment. Therefore, the shape of the drain wiring layer 121 is substantially the same as that of the drain wiring layer 120 according to the first embodiment. As described above, if the overall arrangement is substantially the same, the drain regions 32 and 33 and the current concentration relaxation electrode 71 may be formed in a continuous manner or in an independent manner. The wiring layers 120 and 121 can be used.

  In the semiconductor device 101 according to the second embodiment, since the arrangement configuration of the source region 20, the back gate region 50, and the substrate electrode 80 is the same as that of the semiconductor device 100 according to the first embodiment, the source wiring layer 111 and the substrate electrode are arranged. The configuration of the wiring layer 131 is the same as that of the source wiring layer 110 and the substrate electrode wiring layer 130 of the first embodiment. As a result, the wiring layer 151 of the semiconductor device 101 according to the second embodiment can use the same wiring pattern as the wiring layer 150 of the semiconductor device 100 according to the first embodiment.

  Thus, according to the semiconductor device 101 according to the second embodiment, the drain regions 32 and 33 and the current concentration relaxation region 71 are separately provided on the surface region of the semiconductor substrate 10, but the drain regions 32 and 33 and the current concentration relaxation are provided. The electrode 71 can be electrically connected to the wiring layer 151 to have the same potential. As a result, while allowing a free layout on the semiconductor substrate 10, it is possible to avoid a phenomenon in which the backflow current I3 concentrates on both ends of the drain region 32 arranged on both sides of the gate 40, and the semiconductor device 101. Can be prevented.

  FIG. 6 is a diagram illustrating an example of a planar configuration of the semiconductor device 102 according to the third embodiment of the present invention. In FIG. 6, the same components as those of the semiconductor device 101 according to the second embodiment are denoted by the same reference numerals, and the description thereof is omitted.

  Specifically, the semiconductor device 102 according to the third embodiment includes a semiconductor substrate 10, a source region 20, drain regions 32 and 33, a gate 40, a back gate region 50, a LOCOS 60, a substrate electrode 80, Since the contact holes 25, 37, 38, 55, and 85 are the same as those of the semiconductor device 101 according to the second embodiment, the same reference numerals as those in the second embodiment are given to the contact holes 25, 37, 38, 55, and 85, and the description thereof is omitted.

  In the semiconductor device 102 according to the third embodiment, the current concentration relaxation electrodes 72 do not extend to the drain regions 33 at both ends in the longitudinal direction of the semiconductor device 102 and have a length that guards only the central drain region 72. This is different from the semiconductor device 101 according to the second embodiment.

  However, in the semiconductor device 102 according to the third embodiment, the current concentration relaxation electrode 72 is provided between the end portion and the substrate electrode 80 outside the end portion in the extending direction of the drain region 72. The semiconductor devices 100 and 101 according to the first and second embodiments are common.

  As described with reference to FIG. 8, the backflow current I3 is concentrated and the problem occurs only at both ends of the drain region 32 that are sandwiched between the gates 40 and are not opposed to the substrate electrode 80. Therefore, as shown in FIG. 6, the current concentration relaxation electrode 72 may have a length that guards only both ends of the drain region 32. In this case, if the current concentration relaxation electrode 72 has a plurality of contact holes 77 between the drain region 32 and the substrate electrode 80, the current concentration relaxation electrode 72 has an effect of reducing the concentration of the backflow current I3. If the length is short, the backflow current I3 flowing from the side cannot be guarded, so that the length or width is preferably larger than the width of the drain region 32. More preferably, if the length or width of the current concentration relaxation electrode 72 is larger than the distance between the two gates 40 sandwiching the drain region 32, the concentration of the backflow current I3 can be sufficiently prevented.

  In the third embodiment, since the length or width of the current concentration relaxation electrode 72 is small, the current concentration relaxation electrode 72 may be disposed so as to be surely present on the extension line in the extending direction of the drain region 32. preferable.

  Note that the contact holes 77 are densely formed on the current concentration relaxation electrode 72 as in the semiconductor devices 100 and 101 according to the first and second embodiments.

  In addition, a wiring layer having the same pattern as the wiring layer 151 according to the second embodiment can be used as the upper wiring layer of the semiconductor substrate 10 of the semiconductor device 102 according to the third embodiment. Note that the pattern of the wiring layer is not limited to the pattern of the wiring layer 151 of the second embodiment, and the contact holes 37 and 38 of the drain regions 32 and 33 and the contact hole 77 of the current concentration relaxation electrode 72 are formed in the same drain. If it can be connected in the wiring layer, it can be configured with various wiring patterns.

  The preferred embodiments of the present invention have been described in detail above. However, the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the present invention. Can be added. In particular, in this embodiment, the example in which the semiconductor device is configured as an n-channel LDMOS has been described. However, the present invention can be similarly applied to a case where the semiconductor device is configured as a p-channel LDMOS. .

  The present invention can be used for a semiconductor device including an LDMOS.

10 Semiconductor substrate 15 n layer 20 source region 25, 35, 36, 37, 38, 55, 85 contact hole 30, 31, 32, 33 drain region 40 gate 50 back gate region 60 LOCOS
70, 71, 72 Current concentration relaxation electrode 80 Substrate electrode 90 Oxide film 100, 101, 102 Semiconductor device 110, 111 Source wiring layer 120, 121 Drain wiring layer 130, 131 Substrate electrode wiring layer 150, 151 wiring layer

Claims (6)

A source region and a drain region that are formed in a surface region of the semiconductor substrate and extend opposite to each other, and a surface that is formed on the surface of the semiconductor substrate and extends along the source region between the source region and the drain region. In a semiconductor device comprising a plurality of transistor cells including a gate, and a substrate electrode that surrounds the plurality of transistor cells and defines a reference potential of the semiconductor substrate,
The surface region of the semiconductor substrate has the same potential as the drain region on the extension line of the drain region between the end of the drain region sandwiched between the gates in the extending direction and the substrate electrode. A semiconductor device comprising a current concentration relaxation electrode. The length of the current concentration relaxation electrode in a direction perpendicular to the extending direction of the drain region is longer than a width in a direction perpendicular to the extending direction of the drain region. Semiconductor device.   The semiconductor device according to claim 1, wherein the current concentration relaxation electrode is electrically connected to the drain region by a wiring layer.   The semiconductor device according to claim 3, wherein the current concentration relaxation electrode is provided in a surface region of the semiconductor substrate continuously with the drain region.   The current concentration relaxation electrode is provided in the surface region of the semiconductor substrate continuously with all the drain regions, and the drain region and the current concentration relaxation electrode surround the gate and the source region in a plane. The semiconductor device according to claim 4. The drain region is composed of an n-type diffusion layer,
The substrate electrode is composed of a p-type diffusion layer,
The semiconductor device according to claim 1, wherein the current concentration relaxation electrode is composed of an n-type diffusion layer.

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