WO2013018589A1

WO2013018589A1 - Semiconductor integrated circuit device

Info

Publication number: WO2013018589A1
Application number: PCT/JP2012/068737
Authority: WO
Inventors: 石橋　孝一郎
Original assignee: 国立大学法人電気通信大学
Priority date: 2011-08-01
Filing date: 2012-07-24
Publication date: 2013-02-07
Also published as: TW201310620A; JPWO2013018589A1

Abstract

This semiconductor integrated circuit device has a CMOS structure that includes a first conductivity-type MOSFET and a second conductivity-type MOSFET. The semiconductor integrated circuit device has: a second conductivity-type well; the first conductivity-type MOSFET having a drain and a source formed on the second conductivity-type well; a second conductivity-type diffusion layer formed on the second conductivity-type well; a first power supply line, which is provided on an upper layer of the second conductivity-type diffusion layer, and supplies first potential to the first conductivity-type MOSFET; a first conductivity-type well; a second conductivity-type MOSFET having a drain and a source formed on the first conductivity-type well; a first conductivity-type diffusion layer formed on the first conductivity-type well; and a second power supply line, which is provided on an upper layer of the first conductivity-type diffusion layer, and supplies second potential to the first conductivity-type well. The first conductivity-type diffusion layer and the second conductivity-type diffusion layer are power supplying layers for respectively applying substrate bias to the first conductivity-type well and the second conductivity-type well, the first conductivity-type diffusion layer and the second power supply line are disposed parallel to each other by having an interlayer insulating layer therebetween, and have at least respective parts thereof overlap each other in planar view, and the second conductivity-type diffusion layer and the fist power supply line are disposed parallel to each other by having an interlayer insulating layer therebetween, and have at least respective parts thereof overlap in planar view.

Description

Semiconductor integrated circuit device

The present invention relates to a semiconductor integrated circuit device having a CMOS structure.

In recent years, CMOS (Complementary Metal Oxide Semiconductor, hereinafter the same) substrate bias technology is known as a circuit technology for realizing high speed and lower power consumption of LSI (Large Scale Integration, the same hereinafter).

As an example of the CMOS substrate bias technology, Non-Patent Document 1 describes a microprocessor manufactured in a 0.2 μm CMOS technology for a MOSFET (Metal Oxide Semiconductor Field Effect Transistor, etc.) when the microprocessor is on standby. It is described that the leakage current during standby can be reduced by about three orders of magnitude by applying a substrate bias.

Specifically, a standard cell composed of MOSFETs for applying a substrate bias, a layout of a switch cell for controlling the application of the substrate bias (see FIG. 5), and a power source by arranging a collection of cells. A layout (see FIG. 6) showing the wiring of the substrate bias is described.

In the layout described in Non-Patent Document 1, since a metal wiring layer for applying a substrate bias is arranged in each standard cell, it is possible to reduce the impedance of the substrate bias and to apply a stable substrate bias. .

As another example of the CMOS substrate bias technology, Patent Document 1 discloses that a well contact for applying a substrate bias is arranged in a place other than a standard cell, and metal wiring for applying the substrate bias to the standard cell is provided. Techniques that do not insert are described.

JP 2009-117858 A

However, the technique of Non-Patent Document 1 has a problem that the occupied area becomes large when standard cells are arranged due to the following two factors.

The first factor is that since the power supply wiring and the substrate bias wiring in the standard cell are constituted by the first metal wiring layer (M1), each wiring requires a predetermined area. The second factor is that the standard cells must be arranged between the switch cells arranged at intervals of 200 μm. Therefore, the standard cells having various widths cannot be arranged at the maximum between the switch cells. An area where the standard cell is not arranged is generated between the switch cells arranged in (1).

Further, in the technique of Patent Document 1, since the well and the contact of the MOSFET in the standard cell are separated from each other, the impedance of the substrate bias is increased, and as a result, the characteristics such as the threshold voltage of the MOSFET fluctuate, There was a problem that the delay time was not stable. That is, there is a problem that the substrate bias cannot be stably applied.

The present invention has been made in view of the above points, and an object thereof is to provide a semiconductor integrated circuit device capable of stably applying a substrate bias in a small area.

The semiconductor integrated circuit device is a semiconductor integrated circuit device having a CMOS structure including a first conductivity type MOSFET and a second conductivity type MOSFET, wherein a second conductivity type well and a drain and a source are formed in the second conductivity type well. The first conductivity type MOSFET, the second conductivity type diffusion layer formed in the second conductivity type well, and the second conductivity type diffusion layer are provided on the first conductivity type MOSFET. A first power supply line for supplying a potential; a first conductivity type well; the second conductivity type MOSFET having a drain and a source formed in the first conductivity type well; and a first conductivity type well formed in the first conductivity type well. A first conductivity type diffusion layer; and a second power supply line that is provided in an upper layer of the first conductivity type diffusion layer and supplies a second potential to the first conductivity type well. And the second conductivity type The diffusion layer is a power supply layer for applying a substrate bias to the first conductivity type well and the second conductivity type well, respectively, and the first conductivity type diffusion layer and the second power supply line are interlayer insulating layers. And the second conductive type diffusion layer and the first power supply line are arranged in parallel with each other through an interlayer insulating layer. In addition, it is a requirement that at least a portion overlaps in plan view.

According to the disclosed technique, a semiconductor integrated circuit device capable of stably applying a substrate bias in a small area can be provided.

1 is a circuit diagram illustrating a semiconductor integrated circuit device according to a first embodiment; 1 is a plan view illustrating a semiconductor integrated circuit device according to a first embodiment; It is sectional drawing which follows the AA line of FIG. 1B. It is sectional drawing which follows the BB line of FIG. 1B. It is a figure equivalent to FIG. 1C of 1st Embodiment in 2nd Embodiment. It is a figure equivalent to FIG. 1D of 1st Embodiment in 2nd Embodiment. FIG. 10 is a cross-sectional view illustrating a semiconductor integrated circuit device according to Modification 1 of the second embodiment. FIG. 10 is a cross-sectional view illustrating a semiconductor integrated circuit device according to Modification 2 of the second embodiment. 6 is a plan view illustrating a semiconductor integrated circuit device according to a third embodiment; FIG. It is sectional drawing which follows the CC line of FIG. 5A. It is sectional drawing which follows the DD line | wire of FIG. 5A. It is sectional drawing which follows the EE line of FIG. 5A. It is a figure which shows the example which has arrange | positioned many cells from which a magnitude | size differs adjacently in the semiconductor integrated circuit device which concerns on 3rd Embodiment.

Hereinafter, embodiments for carrying out the invention will be described with reference to the drawings. In the drawings, the same components are denoted by the same reference numerals, and redundant description may be omitted. In the following embodiments and modifications thereof, an inverter circuit (logic inversion circuit) will be described as an example. However, the present invention is not limited to this, and the present invention is applied to a semiconductor integrated circuit device having a CMOS structure other than the inverter circuit. Is also widely applicable.

<First Embodiment>
FIG. 1A is a circuit diagram illustrating the semiconductor integrated circuit device according to the first embodiment. Referring to FIG. 1A, a semiconductor integrated circuit device 1 is a semiconductor integrated circuit device having a CMOS structure including an N-type MOSFET 10 and a P-type MOSFET 20, and has a function as an inverter circuit. In the present application, the first conductivity type is N-type or P-type, and the second conductivity type is P-type or N-type opposite to the first conductivity type.

In FIG. 1A, the ground wiring 16 (Vss) is connected to the source S ₁ of the N-type MOSFET ₁₀ . The substrate wiring 12 (Vbn) is a wiring for applying a substrate bias to the N-type MOSFET ₁₀ and is connected to the back gate B ₁ of the N-type MOSFET ₁₀ . The power supply wiring 26 (Vdd) is connected to the source S ₂ of the P-type MOSFET ₂₀ . The substrate wiring 22 (Vbp) is a wiring for applying a substrate bias to the P-type MOSFET _20, and is connected to the back gate B ₂ of the P-type MOSFET ₂₀ .

The input terminal 31 (Vin) is an input terminal of the inverter circuit, and is connected to the gate G ₁ of the N-type MOSFET ₁₀ and the gate G _{2 of the} P-type MOSFET ₂₀ . The output terminal 32 (Vout) is an output terminal of the inverter circuit, and is connected to the drain D ₁ of the N-type MOSFET ₁₀ and the drain D _{2 of the} P-type MOSFET ₂₀ .

The voltages applied to the ground wiring 16, the power supply wiring 26, the substrate wiring 12, and the substrate wiring 22 can be determined as appropriate. For example, 0 v, 0.5 to 1.0 v, +0.5 to −3.3 v, and It can also be changed to be 0 to 3.8v.

FIG. 1B is a plan view illustrating the semiconductor integrated circuit device according to the first embodiment. 1C is a cross-sectional view taken along the line AA in FIG. 1B. 1D is a cross-sectional view taken along line BB in FIG. 1B. In FIG. 1B, for convenience, the ground wiring 16, the power supply wiring 26, the input terminal 31, and the output terminal 32 are drawn transparently, and the lower layer is seen through. For convenience, the

substrate wirings

12 and 22 are shown in a satin pattern.

1B to 1D, the N-type MOSFET 10 and the P-type MOSFET 20 are arranged so as to be adjacent to each other in the YY direction in plan view (viewed from the ZZ direction in FIG. 1C or FIG. 1D). ing.

In the N-type MOSFET 10, a source electrode 13 and a drain electrode 14 are arranged at predetermined intervals in the XX direction near the upper surface (surface on the gate electrode 15 side) of the P-type well 11 containing a low-concentration P-type impurity. It is installed. An isolation layer 33 is formed on one side of each of the source electrode 13 and the drain electrode 14. A gate electrode 15 is provided at a position overlapping a channel region sandwiched between the source electrode 13 and the drain electrode 14 via a gate insulating film (not shown).

The P-type well 11, the source electrode 13, the drain electrode 14, and the gate electrode 15 correspond to the back gate B ₁ , the source electrode S ₁ , the drain electrode D ₁ , and the gate electrode G ₁ shown in FIG. 1A, respectively.

In plan view, substrate wiring 12 is provided in the XX direction on the side near the top surface of the P-type well 11 and not adjacent to the N-type well 21. The substrate wiring 12 is formed of a P-type diffusion layer containing a P-type impurity having a concentration higher than that of the P-type well 11 in order to fix the potential of the P-type well 11. Further, a low resistance material such as metal silicide may be formed on the surface of the diffusion layer. That is, the substrate wiring 12 is a power feeding layer for applying a substrate bias to the P-type well 11.

On the upper surface of the P-type well 11, a ground wiring 16 is provided in the XX direction via an interlayer insulating layer (not shown). The ground wiring 16 extends to the source electrode 13 side (in the YY direction) and is connected to the source electrode 13 through a through wiring 16x that penetrates an interlayer insulating layer (not shown). The ground wiring 16 and the through wiring 16x can be formed of a metal such as copper (Cu) or tungsten (W), for example.

The ground wiring 16 is an upper layer of the substrate wiring 12, and the substrate wiring 12 and the ground wiring 16 are arranged in parallel to each other through an interlayer insulating layer (not shown). In order to reduce the area of the semiconductor integrated circuit device 1, it is preferable that at least a part of the substrate wiring 12 and the ground wiring 16 overlap in plan view. More preferably, the substrate wiring 12 and the ground wiring 16 all overlap in plan view.

In the example of FIG. 1B, the substrate wiring 12 and the ground wiring 16 are each formed in a substantially linear shape in the XX direction, but either one or both may include a portion that is not linear. Further, the substrate wiring 12 and the ground wiring 16 may have the same width (YY direction) or different widths. For example, in order to stabilize the power supply, the width of the ground wiring 16 can be made larger than the width of the substrate wiring 12, and the substrate wiring 12 can be arranged at a position overlapping the ground wiring 16 in plan view.

In the present application, “parallel” means approximately parallel and does not mean strictly parallel. Therefore, the semiconductor integrated circuit device according to the first embodiment may be deviated from parallelism within a range that does not substantially impair the predetermined effect.

In the P-type MOSFET 20, a source electrode 23 and a drain electrode 24 are arranged in parallel at a predetermined interval in the XX direction near the upper surface (surface on the gate electrode 25 side) of the N-type well 21 containing a low-concentration N-type impurity. It is installed. An isolation layer 33 is formed on one side of each of the source electrode 23 and the drain electrode 24. A gate electrode 25 is provided at a position overlapping the channel region sandwiched between the source electrode 23 and the drain electrode 24 via a gate insulating film (not shown).

Note that the N-type well 21, the source electrode 23, the drain electrode 24, and the gate electrode 25 correspond to the back gate B ₂ , the source electrode S ₂ , the drain electrode D ₂ , and the gate electrode G ₂ shown in FIG. 1A, respectively.

In plan view, substrate wiring 22 is provided in the XX direction near the upper surface of the N-type well 21 and on the side not adjacent to the P-type well 11. The substrate wiring 22 is formed of an N-type diffusion layer containing an N-type impurity at a concentration higher than that of the N-type well 21 in order to fix the potential of the N-type well 21. That is, the substrate wiring 22 is a power feeding layer for applying a substrate bias to the N-type well 21.

On the upper surface of the N-type well 21, a power supply wiring 26 is provided in the XX direction via an interlayer insulating layer (not shown). The power supply wiring 26 extends to the source electrode 23 side (in the YY direction) and is connected to the source electrode 23 through a through wiring 26x that penetrates an interlayer insulating layer (not shown). The power supply wiring 26 and the through wiring 26x can be formed of a metal such as copper (Cu) or tungsten (W), for example.

The power supply wiring 26 is an upper layer of the substrate wiring 22, and the substrate wiring 22 and the power supply wiring 26 are arranged in parallel to each other through an interlayer insulating layer (not shown). In order to reduce the area of the semiconductor integrated circuit device 1, it is preferable that at least a part of the substrate wiring 22 and the power supply wiring 26 overlap in plan view. It is more preferable that the substrate wiring 22 and the power supply wiring 26 are all overlapped in plan view.

In the example of FIG. 1B, the substrate wiring 22 and the power supply wiring 26 are each formed in a substantially linear shape in the XX direction, but either one or both may include a portion that is not linear. Further, the substrate wiring 22 and the power supply wiring 26 may have the same width (YY direction) or different widths. For example, in order to stabilize power supply, the width of the power supply wiring 26 can be made larger than the width of the substrate wiring 22, and the substrate wiring 22 can be arranged at a position overlapping the power supply wiring 26 in plan view.

An input terminal 31 and an output terminal 32 are provided on the upper surfaces of the P-type well 11 and the N-type well 21 via an interlayer insulating layer (not shown). The input terminal 31 is connected to the

gate electrodes

15 and 25 through a through wiring 31x that passes through an interlayer insulating layer (not shown). The output terminal 32 is connected to the

drain electrodes

14 and 24 through a through wiring 32x that passes through an interlayer insulating layer (not shown).

The ground wiring 16 is a typical example of the first power supply line according to the present invention. The substrate wiring 12 is a typical example of the second conductivity type diffusion layer according to the present invention. The power supply wiring 26 is a typical example of the second power supply line according to the present invention. The substrate wiring 22 is a typical example of the first conductivity type diffusion layer according to the present invention.

As described above, in the semiconductor integrated circuit device 1 according to the first embodiment, the substrate wiring 12 is formed by the P-type diffusion layer containing P-type impurities at a higher concentration than the P-type well 11 in the vicinity of the upper surface of the P-type well 11. The ground wiring 16 is arranged in parallel to the substrate wiring 12 via an interlayer insulating layer (not shown). Further, a substrate wiring 22 is formed by an N-type diffusion layer containing an N-type impurity at a concentration higher than that of the N-type well 21 in the vicinity of the upper surface of the N-type well 21 and an interlayer insulating layer (not shown) is formed as the power supply wiring 26. Are arranged in parallel to the substrate wiring 22. The substrate wiring 12 and the ground wiring 16 are at least partially overlapped in plan view, and the substrate wiring 22 and the power supply wiring 26 are at least partially overlapped in plan view.

Thereby, in the N-type MOSFET 10, the distance between the portion of the P-type well 11 below the gate electrode 15 and the substrate wiring 12 can be shortened. Further, in the P-type MOSFET 20, the distance between the portion of the N-type well 21 below the gate electrode 25 and the substrate wiring 22 can be shortened.

As a result, the respective impedances of the

substrate wirings

12 and 22 can be reduced, and the N-type MOSFET 10 (the portion under the gate electrode 15 of the P-type well 11) and the P-type MOSFET 20 (the gate electrode 25 of the N-type well 21). A substrate bias can be stably applied to each of the lower portions. Further, an extra wiring area for applying the substrate bias is not necessary, and the substrate bias can be applied in a small area. That is, a semiconductor integrated circuit device capable of stably applying a substrate bias in a small area can be provided.

<Second Embodiment>
In the second embodiment, an example of applying a substrate bias of a MOSFET on an SOI (Silicon On Insulator, hereinafter the same) substrate is shown. In the second embodiment, the description of the same components as those of the already described embodiments is omitted.

FIG. 2A is a diagram corresponding to FIG. 1C of the first embodiment in the second embodiment. FIG. 2B is a diagram corresponding to FIG. 1D of the first embodiment in the second embodiment. Since the circuit diagram and the plan view are the same as those in the first embodiment, the illustration is omitted.

2A and 2B, in the semiconductor integrated circuit device 1A, the semiconductor integrated circuit according to the first embodiment is that the N-type MOSFET 10A and the P-type MOSFET 20A are formed on a thin film oxide film of SOI. This is different from the apparatus 1 (see FIGS. 1B to 1D).

In FIG. 2A, the oxide film 17 is a thin insulating film constituting the SOI. The oxide film 17 is provided at least between the P-type well 11 and the source and drain

electrodes

13 and 14. The oxide film 17 is not provided between the P-type well 11 and the substrate wiring 12. In FIG. 2B, the oxide film 27 is a thin insulating film constituting the SOI. The oxide film 27 is provided at least between the N-type well 21 and the source electrode 23 and the drain electrode 24. The oxide film 27 is not provided between the N-type well 21 and the substrate wiring 22.

The

oxide films

17 and 27 can be made of SiO ₂ , for example. The thicknesses of the

oxide films

17 and 27 are determined from the

substrate wirings

12 and 22, respectively, by the N-type MOSFET 10A (the portion under the gate electrode 15 of the P-type well 11) and the P-type MOSFET 20A (the gate electrode 25 of the N-type well 21). Can be determined as appropriate within a range in which the substrate bias can be applied to the lower portion), but can be about 10 nm, for example. The oxide film 17 is a typical example of the first insulating film according to the present invention. The oxide film 27 is a typical example of the second insulating film according to the present invention.

As described above, in the semiconductor integrated circuit device 1A according to the second embodiment, the N-type MOSFET 10A and the P-type MOSFET 20A are formed on the SOI thin film substrate. Even in such a structure, the

oxide films

17 and 27 of the P-type well 11 and the N-type well 21 are respectively reduced by sufficiently reducing the thicknesses of the oxide films 17 and 27 (for example, about 10 nm). By applying a substrate bias to the upper region via the

substrate wirings

12 and 22, the characteristics of the N-type MOSFET 10A and the P-type MOSFET 20A can be controlled.

Specifically, for example, by applying a substrate bias to the regions located above the

oxide films

17 and 27 of the P-type well 11 and the N-type well 21 via the

substrate wirings

12 and 22, respectively, The threshold values of the MOSFET 10A and the P-type MOSFET 20A can be varied. At this time, since the

oxide films

17 and 27 are each an insulating film, a leak current due to application of a substrate bias does not occur. Therefore, the power consumption of the semiconductor integrated circuit device 1A can be reduced.

Further, by providing the substrate wiring 12 made of the P-type diffusion layer and the substrate wiring 22 made of the N-type diffusion layer in the region where the

oxide films

17 and 27 of the P-type well 11 and the N-type well 21 are not formed, The same effects as those of the first embodiment are obtained.

<Modification Example 1 of Second Embodiment>
Modification 1 of the second embodiment shows another example using an SOI substrate. In the first modification of the second embodiment, the description of the same components as those of the already described embodiment is omitted.

FIG. 3 is a cross-sectional view illustrating a semiconductor integrated circuit device according to Modification 1 of the second embodiment. Referring to FIG. 3, in a semiconductor integrated circuit device 1B according to Modification 1 of the second embodiment, an N-type MOSFET 10A is formed on a P-type substrate 11A, and an N-type well 21 is formed on a P-type substrate 11A. The point that the P-type MOSFET 20A is formed in the N-type well 21 is different from the semiconductor integrated circuit device 1A (see FIGS. 2A and 2B).

As described above, in the semiconductor integrated circuit device 1B according to the first modification of the second embodiment, the N-type MOSFET 10A is directly formed on the semiconductor substrate (P-type substrate 11A), and the same semiconductor substrate (P-type substrate 11A) is formed. Although the P-type MOSFET 20A is formed via the N-type well 21, the same effects as those of the second embodiment can be obtained even in such a structure.

<Modification 2 of the second embodiment>
The second modification of the second embodiment shows an example in which a plurality of N-type MOSFETs and P-type MOSFETs are formed on an SOI substrate, and a substrate bias is individually applied to the MOSFETs. In the second modification of the second embodiment, the description of the same components as those of the already described embodiment is omitted.

FIG. 4 is a cross-sectional view illustrating a semiconductor integrated circuit device according to Modification 2 of the second embodiment. Referring to FIG. 4, in the semiconductor integrated circuit device 1C according to the second modification of the second embodiment, an N-type MOSFET 10A is formed in the P-type well 11, and a P-type MOSFET 20A is formed in the N-type well 21. This is similar to the semiconductor integrated circuit device 1A (see FIGS. 2A and 2B). However, an N-type well 41 is provided below the P-type well 11 and the N-type well 21 (at a position deeper than the P-type well 11 and the N-type well 21). 49 is different from the semiconductor integrated circuit device 1A (see FIGS. 2A and 2B).

In the semiconductor integrated circuit device 1C, P-type well 11 ₁ (being insulated) independently has a P-type well 11 _2, N-type well 21 ₁ is independent from the N-type well 21 ₃ (being insulated ) The N-

type wells

21 ₁ and 21 ₂ are connected by an N-type well 41 ₁ .

Independently to have P-

type well

11 ₁ and 11 ₂ each are capable individual substrate bias is applied, the N-

type well

21 ₁ and 21 ₃ which are independent, each individual substrate bias is applied It is possible. In the case of Figure 4, the substrate wiring 12 ₁ and the substrate wiring 12 _2, respectively separate substrate bias can be applied. Further, the substrate wiring 22 ₁ and the substrate wiring 22 _2, respectively separate substrate bias can be applied.

As described above, in the semiconductor integrated circuit device 1C according to the second modification of the second embodiment, the P-type well 11 ₁ in which the N-type MOSFET 10A is formed is formed at a deeper position than the P-type well 11 ₁ . the N-type well 41 _1, is electrically isolated from the P-type well 11 ₂ other N-type MOSFET10B is formed. Further, N-type well 21 ₁ P-type MOSFET20A is formed, N-type well 21 by N-type well 41 ₁ formed at a position deeper than _1, other N-type well P-type MOSFET20B are formed 21 ₂ And are electrically connected.

Thereby, individual substrate biases can be applied to the independent P-type well 11 (P-type wells 11 ₁ and 11 ₂ ) and N-type well 21 (N-type wells 21 ₁ and 21 ₃ ), respectively.

Note that the semiconductor integrated circuit device 1C according to the second modification of the second embodiment also has the same effect as the semiconductor integrated circuit device 1A according to the second embodiment.

<Third Embodiment>
The third embodiment shows an example in which a plurality of standard cells are arranged adjacent to each other. In the third embodiment, the description of the same components as those of the already described embodiments is omitted.

FIG. 5A is a plan view illustrating a semiconductor integrated circuit device according to the third embodiment. FIG. 5B is a cross-sectional view taken along the line CC of FIG. 5A. FIG. 5C is a cross-sectional view taken along the line DD of FIG. 5A. FIG. 5D is a cross-sectional view taken along line EE of FIG. 5A. 5A to 5D, the P-type well 11 and the N-type well 21 are the S0 layer, the metal wiring layer disposed on the S0 layer via the interlayer insulating layer (not shown) is the M1 layer, and the interlayer insulating layer. The metal wiring layer disposed on the M1 layer via the (not shown) is the M2 layer, and the metal wiring layer disposed on the M2 layer via the interlayer insulating layer (not shown) is the M3 layer. ... (M1) ”or the like, and the layers in which (...) are formed are indicated. In FIG. 5A, for convenience, the ground wiring 16, the power supply wiring 26, the input terminal 31, and the output terminal 32 are drawn transparently and the lower layer is seen through. For convenience, the substrate wirings 12 (S0) and 22 (S0) are shown in a satin pattern.

5A to 5D, in the semiconductor integrated circuit device 1D, a plurality of standard cells are arranged adjacent to each other. Specifically, three inverter cells 51 are arranged adjacent to each other, and a high booster cell 52 is arranged adjacent to the inverter cells 51. A tap cell 53 is disposed adjacent to the high booster cell 52.

However, in the present embodiment, the inverter cell 51 and the high booster cell 52 having a width (XX direction) wider than the inverter cell 51 are arranged as the standard cells, but the present invention is not limited to this. . In FIG. 5A, the N-type MOSFET 10 and the P-type MOSFET 20 are shown only in one inverter cell 51 as a representative, and the illustration of the other inverter cells 51 is omitted.

In this manner, by arranging a plurality of standard cells (inverter cell 51 and high booster cell 52) adjacent to each other, a set of N-type MOSFET and P-type MOSFET adjacent to each other in YY direction is changed to YY direction. By arranging a plurality of sets in parallel in the XX direction orthogonal to each other, the substrate wirings 12 (S0) of the standard cells are arranged adjacent to each other, so that the substrate wirings 12 (S0) of the standard cells can be easily connected to each other. can do. Further, since the substrate wirings 22 (S0) of the standard cells are arranged adjacent to each other, the substrate wirings 22 (S0) of the standard cells can be easily connected to each other. For example, a flip-flop cell, a NAND cell, an inverter cell with a wide gate width, or the like can be arranged in the high booster cell 52.

In the semiconductor integrated circuit device 1D, the substrate wiring 12 (M2), the ground wiring 16 (M2), the substrate wiring 22 (M2), and the power wiring 26 (M2), which are power supply trunk lines, are metal wiring layers M2, respectively. It is formed in the Y direction in the layer. These four power trunks can be formed on top of any standard cell. In the present embodiment, an example is shown in which four power supply trunks are formed above the high booster cell 52.

The ground wiring 16 (M2), which is one of the power supply trunk lines, is connected to the ground wiring 16 (M1) of the high booster cell 52 on the high booster cell 52 by the through wiring 54. Similarly, the power supply wiring 26 (M2) which is one of the power supply trunk lines is connected to the power supply wiring 26 (M1) of the high booster cell 52 on the high booster cell 52 by the through wiring 55.

On the other hand, the substrate wiring 12 (M2), which is one of the power supply trunk lines, includes the through wiring 56, the metal wiring 57 (M3), the through wiring 58 ₁ , the metal wiring 57 (M2), the through wiring 58 ₂ , and the metal wiring 57 (M1). ), and via the through wiring 58 _3, and is connected to the P-type diffusion layer 59 containing a P-type impurity of high concentration of tap cell 53 (S0). Further, the P-type diffusion layer 59 (S0) is connected to the substrate wiring 12 (S0) in the tap cell 53.

Similarly, the substrate wiring 22 (M2) which is one of the power supply trunk lines includes a through wiring 66, a metal wiring 67 (M3), a through wiring 68 ₁ , a metal wiring 67 (M2), a through wiring 68 ₂ , a metal wiring 67 ( M1), and via the through wiring ₆₈₃ is connected to the N-type diffusion layer 69 containing N-type impurity of high concentration of tap cell 53 (S0). Further, the N-type diffusion layer 69 (S0) of the tap cell 53 is connected to the substrate wiring 22 (S0) in the tap cell 53. The tap cell 53 can be inserted at any position between adjacent standard cells (any position between a plurality of sets of N-type MOSFET 10 and P-type MOSFET 20).

However, an M4 layer (metal wiring layer) is disposed on the M3 layer via an interlayer insulating layer (not shown), and the substrate wiring 12 (M2), the ground wiring 16 (M2), and the substrate wiring 22 ( M2) and all or part of the power supply wiring 26 (M2) may be formed in the Y direction in the M4 layer.

The ground wiring 16 (M2) is a typical example of the first power supply trunk line according to the present invention. The substrate wiring 12 (M2) is a typical example of the first substrate bias trunk line according to the present invention. The power supply wiring 26 (M2) is a typical example of the second power supply trunk line according to the present invention. The substrate wiring 22 (M2) is a typical example of the second substrate bias trunk line according to the present invention.

FIG. 6 is a diagram showing an example in which a large number of cells having different sizes are arranged adjacent to each other in the semiconductor integrated circuit device according to the third embodiment. As shown in FIG. 6, by arranging the power supply trunk lines at a predetermined interval, a large number of cells having different sizes can be arranged adjacent to each other in the XX direction and the YY direction.

As described above, in the semiconductor integrated circuit device 1D according to the third embodiment, the connection from the substrate wiring 12 (M2) that is the power supply trunk line to the substrate wiring 12 (S0) and the substrate wiring 22 (M2 that is the power supply trunk line). ) To the substrate wiring 22 (S 0) through the tap cell 53. Further, the connection from the substrate wirings 12 (M2) and 22 (M2), which are power supply trunk lines, to the tap cell 53 is performed through metal wirings 57 (M3) and 67 (M3) which are substantially orthogonal to the power supply trunk lines, respectively. Thereby, even if the distance from the substrate wirings 12 (M2) and 22 (M2), which are power supply trunk lines, to the tap cell 53 is long, both can be easily connected.

Further, in the conventional semiconductor integrated circuit device, since the tap cell is disposed below the power supply trunk line, the standard cell cannot be disposed below the power supply trunk line, which hinders the reduction of the area of the semiconductor integrated circuit device. In the present embodiment, the tap cell 53 can be arranged at an arbitrary position rather than below the power supply trunk line. For this reason, standard cells (a combination of an N-type MOSFET and a P-type MOSFET) can be arranged in a region overlapping the region where the power supply trunk line is provided in plan view, and the tap cell 53 can be arranged adjacent to the standard cell. Thereby, the area of the semiconductor integrated circuit device 1D can be reduced.

Note that the semiconductor integrated circuit device 1D according to the third embodiment also has the same effects as the semiconductor integrated circuit device 1 according to the first embodiment.

Here, the effect of the present application will be described in more detail. As described above, in the present application, the area of the semiconductor integrated circuit device can be reduced. In this regard, the first effect of reducing the size of the standard cell itself (for example, the first embodiment and the second embodiment) and the case where cells of different sizes are arranged adjacent to each other There is a second effect (for example, the third embodiment) of reducing a useless area. Hereinafter, a case where the present application is applied to a technology having a minimum dimension of 65 nm will be described as an example with specific numerical examples.

In the 65 nm technology, the minimum dimension is applied to the gate length, but the metal wiring interval is usually about 0.2 μm minimum. That is, the design grid length is about 0.2 μm. The standard cell height is typically 9 grids. Therefore, the height of the standard cell is 1.8 μm.

At this time, in the prior art (for example, Non-Patent Document 1, etc.), if a wiring (substrate wiring) for applying a substrate bias is to be drawn, the substrate wiring (substrate bias Vbp) of the P-type MOSFET and the N-type MOSFET For each substrate wiring (substrate bias Vbn), one extra wiring is required for each. Therefore, the height of the standard cell is 1.8 μm to 2.2 μm.

On the other hand, as described above, an extra wiring area for applying the substrate bias is not necessary in the present application, and therefore the height of the standard cell is 1.8 μm. That is, the area reduction effect of the standard cell size in the present application is about 18% (first effect).

Further, in the prior art (for example, Non-Patent Document 1 etc.), tap cells for applying a substrate bias are installed every 200 μm in the 0.2 μm technology. If this is replaced with 65 nm technology, it is necessary to place tap cells about every 65 μm. In the 65 nm technology, a standard cell having a large circuit scale such as a flip-flop with a scanning function may have a cell width of about 10 μm. For example, if cells having a cell width of 10 μm are arranged in a 65 μm area between adjacent tap cells, six cells are arranged to have a remainder of 5 μm, so this 5 μm area becomes a waste area where no cells are placed. Therefore, about 8% of the area is wasted in this example.

On the other hand, as described above, since the tap cell can be arranged at an arbitrary position instead of below the power supply trunk line in the present application, the standard cell is also arranged in an area overlapping with the area where the power supply trunk line is provided in plan view. Tap cells can be placed adjacent to standard cells. For this reason, in the present application, the above-described waste area does not occur, so that there is an area reduction effect of about 8% (second effect).

Thus, when the first effect and the second effect are combined, according to the present application, there is a total area reduction effect of about 26% in the case of 65 nm technology. Even if the technology advances further, it is thought that the same effect can be maintained with a slight change.

In a CMOS circuit, generally, as the chip area increases, the wiring becomes longer, and as a result, the wiring capacity increases. When the wiring capacity increases, the charging / discharging current of the wiring increases or the operation speed of the circuit becomes slow. In the present application, there is an area reduction effect of about 26%, so that low power and high speed equivalent to that are expected. In addition, the reduction of the area increases the number of non-defective chips acquired per wafer and reduces the manufacturing cost per chip, which is very significant industrially.

In addition, as described above, the substrate bias can be stably applied in the present application. This effect will also be described with specific numerical examples.

In a normal CMOS circuit in which no substrate bias is applied, the substrate of the P-type MOSFET is fixed to the power supply potential, and the substrate of the N-type MOSFET is fixed to the ground potential. In this case, a tap cell method is used in which the substrate potential is not fixed for each standard cell, and the substrate potential is fixed at a certain interval. In the tap cell method, since it is not necessary to fix the substrate potential for each standard cell, the area of the diffusion layer for fixing the substrate potential can be saved.

However, in the tap cell method, the substrate potential is fixed through a well resistance having a sheet resistance of about 1 K ohm / □, and thus the variation in the substrate potential increases accordingly. According to studies by the inventors, the substrate potential fluctuates by about 30% of the power supply voltage due to a change in the drain current of the CMOS. The fluctuation in the substrate potential is expected to reduce the operating speed by about 8% to 9%.

As described above, in the present application, each substrate wiring is formed of a P-type diffusion layer and an N-type diffusion layer. Since the sheet resistance of each of the P-type diffusion layer and the N-type diffusion layer is about 10 ohms / square or less, it is possible to reduce the fluctuation of the substrate potential by two orders of magnitude compared to the conventional one, and as a result, the operation speed is lowered. It can be almost eliminated. That is, according to the present application, the substrate bias can be applied more stably than in the prior art, and the operation speed can be increased by about 8% to 9% compared to the prior art.

The preferred embodiment and its modification have been described in detail above, but the present invention is not limited to the above-described embodiment and its modification, and the above-described implementation is performed without departing from the scope described in the claims. Various modifications and substitutions can be added to the embodiment and its modifications.

This international application claims priority based on Japanese Patent Application No. 2011-168531 filed on Aug. 1, 2011, and the entire contents of Japanese Patent Application No. 2011-168531 are incorporated herein by reference. .

1, 1A, 1B, 1C, 1D Semiconductor integrated

circuit device

10, 10A, 10B N-type MOSFET
11 P-type well 11A, 49 P-

type substrate

12, 12 ₁ , 12 ₂ (P-type diffusion layer), 12 (M2), 12 (S0), 22, 22 ₁ , 22 ₂ (N-type diffusion layer), 22 ( M2), 22 (S0)

Substrate wiring

13, 23

Source electrode

14, 24

Drain electrode

15, 25 Gate electrode 16, 16 (M1), 16 (M2)

Ground wiring

16x, 26x, 31x, 32x, 54, 55, 56 , ₅₈ _1, 58 _2, ₅₈ 3, 66, 68 _1, 68 2, 68 ₃ through

wiring

17, 27

oxide film

20, 20A, 20B P-type MOSFET
21, 41 N-type well 26, 26 (M1), 26 (M2) Power supply wiring 31 Input terminal 32 Output terminal 33 Isolation layer 51 Inverter cell 52 High boost cell 53 Tap cell 57 (M1), 57 (M2), 57 ( M3), 67 (M1), 67 (M2), 67 (M3) Metal wiring 59 (S0) P-type diffusion layer 69 (S0) N-type diffusion layer B ₁ , B ₂ Back gate D ₁ , D ₂ drain G ₁ , G ₂ gate S ₁ , S ₂ source

Claims

A semiconductor integrated circuit device having a CMOS structure including a first conductivity type MOSFET and a second conductivity type MOSFET,
A second conductivity type well;
The first conductivity type MOSFET having a drain and a source formed in the second conductivity type well;
A second conductivity type diffusion layer formed in the second conductivity type well;
A first power supply line provided on an upper layer of the second conductivity type diffusion layer and supplying a first potential to the first conductivity type MOSFET;
A first conductivity type well;
The second conductivity type MOSFET in which a drain and a source are formed in the first conductivity type well;
A first conductivity type diffusion layer formed in the first conductivity type well;
A second power supply line provided on an upper layer of the first conductivity type diffusion layer and supplying a second potential to the first conductivity type well;
The first conductivity type diffusion layer and the second conductivity type diffusion layer are power supply layers for applying a substrate bias to the first conductivity type well and the second conductivity type well, respectively.
The first conductivity type diffusion layer and the second power supply line are arranged in parallel with each other through an interlayer insulating layer, and at least a part thereof overlaps in plan view,
The semiconductor integrated circuit device, wherein the second conductivity type diffusion layer and the first power supply line are arranged in parallel with each other through an interlayer insulating layer, and at least a part thereof overlaps in plan view .
In the first conductivity type MOSFET, a first insulating film is provided between the second conductivity type well and the drain and source.
2. The semiconductor integrated circuit device according to claim 1, wherein a second insulating film is provided between the first conductivity type well and the drain and source in the second conductivity type MOSFET.
A plurality of sets of the first conductivity type MOSFET and the second conductivity type MOSFET adjacent in a predetermined direction are arranged in parallel in a direction orthogonal to the predetermined direction,
Connecting the second conductivity type diffusion layers of the second conductivity type well in which the first conductivity type MOSFETs arranged in parallel are formed;
2. The semiconductor integrated circuit device according to claim 1, wherein the first conductivity type diffusion layers of the first conductivity type well in which the second conductivity type MOSFETs arranged in parallel are formed are connected to each other.
A first power supply trunk line and a second power supply trunk line connected to the first power supply line and the second power supply line, respectively, are provided in an upper layer than the first power supply line and the second power supply line,
A set of the first conductivity type MOSFET and the second conductivity type MOSFET is also arranged in a region overlapping in a plan view with a region where the first power source trunk line and the second power source trunk line are provided. The semiconductor integrated circuit device according to claim 3.
The first power supply line, the second power supply line, the first power supply trunk line, and the second power supply trunk line are connected to each other through a through wiring that penetrates an interlayer insulating layer. 5. The semiconductor integrated circuit device according to 4.
A tap cell is inserted between any set of the first conductivity type MOSFET and the second conductivity type MOSFET arranged in parallel.
A first substrate bias trunk line and a second substrate bias trunk line connected to the second conductivity type diffusion layer and the first conductivity type diffusion layer are provided above the first power supply line and the second power supply line, respectively. ,
4. The first substrate bias trunk line and the second substrate bias trunk line are respectively connected to the second conductivity type diffusion layer and the first conductivity type diffusion layer via the tap cell. The semiconductor integrated circuit device described.
A plurality of sets of the first conductive type MOSFET and the second conductive type MOSFET are formed on a second conductive type semiconductor substrate,
The second conductivity type well in which the first conductivity type MOSFET is formed is electrically separated from the second conductivity type semiconductor substrate by the first conductivity type well formed at a position deeper than the second conductivity type well. 4. The semiconductor integrated circuit device according to claim 3, wherein the semiconductor integrated circuit device is formed.