JP2001237328A - Layout structure of semiconductor device and layout designing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress a potential drop of a substrate or a well potential or a power supply potential while preventing an increase of a layout area in a layout structure in which the substrate or well potential can be supplied independently from the power supply potential. SOLUTION: A second diffusion region 104 for supplying a substrate or well potential is provided separately from a first diffusion region 102 for forming a source of a transistor. In the first diffusion region 102, a power supply potential VSS is supplied via wiring 112 of a first wiring layer and wiring 108 provided in a second wiring layer so as to have some overlaps with the second diffusion region 104. In the first wiring layer, reinforcing wiring 106 for preventing a potential drop in the second diffusion region 104 is provided in the overlaps of the second diffusion region 104 and the VSS wiring 108.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a layout structure of a semiconductor integrated circuit, and more particularly to a layout structure capable of supplying a substrate or well potential independently of a power supply potential, and a layout design method for such a structure. Belongs to technology.

[0002]

2. Description of the Related Art In recent years, MOS (Metal Oxide Semiconduc
tor) In an LSI using a transistor, it is important to reduce a standby current. However, the leak current in the off state of the transistor has increased to a non-negligible level due to a decrease in the threshold voltage due to miniaturization of the process and a reduction in the voltage of the LSI.

In order to solve such a problem, there is known a method of reducing the leak current of a transistor by setting the substrate or well potential to a value different from the source potential and setting the threshold voltage to be apparently higher. in this way,
The substrate potential is set lower than the source potential for the N-type transistor, and the substrate potential is set higher than the source potential for the P-type transistor. In order to use this method, it is necessary to set the substrate or well potential to a value different from the source potential for the cell data included in the standard cell library in the LSI design using the automatic placement and routing.

FIG. 10 shows an example of a conventional cell layout structure. In the layout structure shown in FIG.
MOS transistor (hereinafter referred to as “PMOS”) TP
The substrate or well 7 is connected to a VDD wiring 705 to which a positive power supply potential VDD is supplied from a high-concentration N-type impurity diffusion region 703 on the N well via a contact hole. The source 701 of the PMOS TP7 is connected to the VDD wiring 705 via a contact hole. On the other hand, NMOS transistors (hereinafter referred to as "NMOS")
The substrate or the well of the TN 7 is connected to the VSS wiring 706 to which the negative power supply potential VSS is supplied from the high-concentration P-type impurity diffusion region 704 on the P well via the contact hole. The source 702 of the NMOS TN7 is connected to the VSS wiring 706 via a contact hole. Therefore, in the structure shown in FIG. 10, the substrate or well potential and the source potential are shared, and the substrate or well potential cannot be set to a potential different from the source potential, that is, the power supply potential.

FIG. 11 is a diagram showing an example of a conventional cell layout structure, in which a substrate or well potential and a power supply potential are separated so that power can be supplied. That is, in the structure of FIG. 11, the substrate or well potential of the PMOS TP8 is set to the wiring 8 separated from the VDD wiring 805.
07, and the substrate or well potential of the NMOS TN8 can be supplied from a wiring 808 separated from the VSS wiring 806. Therefore, in the structure shown in FIG. 11, a potential different from the source potential can be supplied as the substrate or well potential.

FIG. 12 is a view showing an example of a conventional cell layout structure, and is a view showing a structure in which a substrate or well potential and a power supply potential are separated so that power can be supplied (Japanese Patent Laid-Open No. 10-154756). Gazette). In FIG. 12, a VDD wiring 901 and a VSS wiring 902 are provided in a second wiring layer formed above a first wiring layer for in-cell wiring. The substrate or well potential of the PMOS TP9 is a high concentration N on the PMOS substrate or N well.
Is supplied from the impurity diffusion region 904 to the VDD wiring 90.
1 does not supply power. The substrate or well potential of the NMOS TN 9 is supplied from the high-concentration P-type impurity diffusion region 903 on the NMOS substrate or the P well, and is not supplied from the VSS wiring 902. A wiring for supplying a substrate or well potential is provided in a wiring layer which is not used for a power supply wiring or a signal line.

[0007]

However, the conventional layout structure has the following problems.

First, in the layout structure shown in FIG.
The wiring width of each of the power supply wirings 805 to 808 is smaller than that of the structure of FIG. For this reason, the sheet resistance of the power supply wiring increases, and the potential drop easily occurs in the power supply path. For example, when the source potential decreases, the performance of the transistor decreases, and the performance of the LSI deteriorates. On the other hand, if the wiring width of the power supply wiring is to be kept wide, it is necessary to make the cell higher accordingly, and the cell area increases. Further, when the wiring width of the power supply wiring is reduced, a phenomenon such as EM (Electro-Migration) tends to occur when a transistor having a high driving capability is connected, and the reliability of the wiring is reduced. Therefore, it is necessary to take measures such as limiting the transistor size.

In the cell layout structure shown in FIG.
The power supply wiring is formed only in the second wiring layer. Therefore, in LSI design using automatic placement and routing, the second
If it is desired to increase the degree of freedom in the wiring layout in the wiring layer, the wiring width of the power supply wiring must be reduced, thereby lowering the power supply potential due to the wiring resistance. For this reason,
The source potential decreases, the performance of the transistor decreases, and the performance of the LSI deteriorates.

In the cell layout structure shown in FIG.
The supply of the substrate or well potential is performed by the impurity diffusion region. Since the impurity diffusion region has a sheet resistance higher by one digit or more than the wiring layer, a potential drop is likely to occur. For this reason, the substrate or well potential is not stabilized, the threshold voltage of the transistor fluctuates, and the like, which causes a problem that the reliability of the LSI operation is reduced and the standby leak current cannot be sufficiently suppressed. In order to prevent a potential drop, a method of inserting reinforcing wires at predetermined intervals is also conceivable.However, even in this case, the number of reinforcing wires needs to be greatly increased as compared with the case where a wiring layer is used, so that a chip is required. There is a concern that the area will increase.

In view of the above problems, the present invention suppresses a potential drop of a substrate or well potential or a power supply potential while suppressing an increase in layout area in a layout structure capable of supplying a substrate or well potential independently of a power supply potential. That is the task.

[0012]

Means for Solving the Problems In order to solve the above-mentioned problems, a solution taken by the invention of claim 1 is to provide a semiconductor device having a first impurity diffusion region formed on a substrate surface as a layout structure. A second impurity diffusion region formed on the surface of the substrate separately from the first impurity diffusion region for supplying a substrate or well potential; and a first wiring layer formed on the substrate. A first wiring electrically connected to the first impurity diffusion region;
A second wiring layer formed above the first wiring layer so as to overlap with the second impurity diffusion region when viewed from a direction perpendicular to the substrate surface, and is electrically connected to the first wiring. A second wiring for supplying a power supply potential to the first impurity diffusion region, and a portion overlapping the second impurity diffusion region and the second wiring when viewed from a direction perpendicular to the substrate surface of the first wiring layer. And a reinforcing wiring which is provided separately from the first wiring and is electrically connected to the second impurity diffusion region.

According to the first aspect of the present invention, in a structure in which the substrate or well potential can be supplied as an independent potential separated from the power supply potential, the substrate or well is connected to the second impurity diffusion region for supplying the substrate or well potential. The reinforcing wiring is provided in the first wiring layer. Thereby, the potential drop of the substrate or well potential is suppressed, and the substrate or well potential becomes more stable. In addition, since the reinforcing wiring is provided in a portion overlapping with the second impurity diffusion region and the second wiring, the layout area does not increase.

According to a second aspect of the present invention, there is provided a semiconductor device layout structure comprising: a first impurity diffusion region formed on a substrate surface; and a first impurity diffusion region formed on the substrate surface. A second impurity diffusion region formed separately and for supplying a substrate or well potential;
A first wiring provided on a first wiring layer formed on the substrate and electrically connected to the first impurity diffusion region; and a second wiring formed on the first wiring layer. Is provided so as to overlap with the second impurity diffusion region when viewed from the direction perpendicular to the substrate surface, and is electrically connected to the first wiring, and a power supply potential is applied to the first impurity diffusion region. And a second wiring for supplying power to the second impurity diffusion region and the second wiring when viewed from a direction perpendicular to the substrate surface of the first wiring layer. It extends to the overlapping part.

According to the second aspect of the present invention, in the structure in which the substrate or well potential can be supplied as an independent potential separated from the power supply potential, the first impurity diffusion region and the second wiring for supplying the power supply potential are provided. Are connected to each other,
A second impurity diffusion region and a second impurity diffusion region in the first wiring layer;
Extending to a portion overlapping with the wiring of FIG. Thereby, the potential drop of the power supply potential is suppressed without increasing the layout area, and the power supply potential is more stabilized. Thereby, the degree of freedom of the wiring layout in the second wiring layer is improved.

According to a third aspect of the present invention, in the layout structure of the semiconductor device according to the first or second aspect, the first
It is assumed that a salicide layer is formed on the surface of the second impurity diffusion region.

According to the fourth aspect of the present invention, in the first aspect,
Alternatively, it is assumed that the first wiring layer in the layout structure of the second semiconductor device is formed of a conductive high melting point material such as tungsten.

According to a fifth aspect of the present invention, there is provided a layout design method using a cell library, wherein at least one of the cell data included in the cell library is formed on a first surface formed on a substrate surface. An impurity diffusion region, a second impurity diffusion region formed on the surface of the substrate separately from the first impurity diffusion region to supply a substrate or well potential, and a first impurity diffusion region formed in the upper layer of the substrate. A first wiring provided in the first wiring layer and connected to the first impurity diffusion region; and a second wiring layer formed in an upper layer of the first wiring layer in the second wiring layer. A second wiring, which is provided so as to have an overlap when viewed from a direction perpendicular to the substrate surface, is electrically connected to the first wiring, and supplies a power supply potential to the first impurity diffusion region; Of the first wiring layer A portion overlapping the second impurity diffusion region and the second wiring when viewed from the direction perpendicular to the plate surface is provided separately from the first wiring, and is electrically connected to the second impurity diffusion region. When the cell is provided with a substrate or well potential and a power supply potential, a contact hole is provided to electrically connect the second wiring and the reinforcement wiring to each other. The method further comprises a step of electrically disconnecting the second wiring and the reinforcing wiring when separating the substrate or well potential from the power supply potential while electrically connecting.

A fifth aspect of the present invention uses the cell data having the layout structure according to the first aspect of the present invention. That is, according to the invention of claim 5, depending on the presence or absence of a contact hole between the second wiring and the reinforcing wiring,
Both a structure for sharing the substrate or well potential and the power supply potential and a structure for separating the same can be easily generated, and the design efficiency is significantly improved.

According to a sixth aspect of the present invention, there is provided a layout design method using a cell library, wherein at least one of the cell data included in the cell library is formed on a first surface formed on a substrate surface. An impurity diffusion region, a second impurity diffusion region formed on the surface of the substrate separately from the first impurity diffusion region to supply a substrate or well potential, and a first impurity diffusion region formed in the upper layer of the substrate. A first wiring provided in the first wiring layer and electrically connected to the first impurity diffusion region; and a second wiring formed in a layer above the first wiring layer. A second region electrically connected to the first wiring and configured to supply a power supply potential to the first impurity diffusion region;
Wherein the first wiring extends to a portion overlapping with the second impurity diffusion region and the second wiring when viewed from a direction perpendicular to the substrate surface of the first wiring layer. When the cell or the well potential and the power supply potential are shared by the cell, a contact hole is provided to electrically connect the first wiring and the second impurity diffusion region, Alternatively, when the well potential is separated from the power supply potential, the method further includes a step of electrically disconnecting the first wiring and the second impurity diffusion region.

A sixth aspect of the present invention uses cell data having a layout structure according to the second aspect of the present invention. That is, according to the invention of claim 6, the structure for sharing the substrate or well potential and the power supply potential and the structure for separating the same depending on the presence or absence of the contact hole between the first wiring and the second impurity diffusion region. , Can be easily generated, and the design efficiency is greatly improved.

According to a seventh aspect of the present invention, there is provided a semiconductor device layout structure comprising: a cell row in which a plurality of cells are arranged in series; and one between the cells in the cell row. And a reinforcing power supply cell disposed therein, wherein each of the cells has an impurity diffusion region for supplying a substrate or well potential different from a power supply potential, and the impurity diffusion region is electrically connected between adjacent cells. Wherein the reinforcing power supply cell includes a power supply impurity diffusion region that electrically connects the impurity diffusion regions of adjacent cells, and a wiring layer formed above the power supply impurity diffusion region. And a power supply wiring electrically connected to the power supply impurity diffusion region.

According to the seventh aspect of the present invention, the substrate or well potential can be reinforced and supplied from the power supply wiring of the reinforcing power supply cell, so that a potential drop in the substrate or well potential power supply path can be prevented, and Alternatively, the well potential can be further stabilized.

According to the invention of claim 8, the reinforcing power supply cells in the layout structure of the semiconductor device of claim 7 are arranged at substantially constant intervals in the cell row.

According to the ninth aspect of the present invention, the seventh aspect of the present invention is provided.
Wherein the plurality of cell rows are provided, and the reinforcing power supply cells are arranged in each of the cell rows so as to be substantially linear in a direction orthogonal to the cell rows. And

According to a tenth aspect of the present invention, there is provided a layout design method comprising: a first step of arranging a plurality of cells in series to form a cell row; A second step of arranging a reinforcing power supply cell in any one of the above, wherein each of the cells has an impurity diffusion region for supplying a substrate or well potential different from a power supply potential, and this impurity diffusion region is adjacent to the power supply potential. The reinforcing power supply cells are electrically connected to each other, and the reinforcing power supply cells are electrically connected to the impurity diffusion regions of adjacent cells. And a power supply wiring provided in a wiring layer formed above the region and electrically connected to the power supply impurity diffusion region.

According to the tenth aspect of the present invention, it is possible to design a layout structure in which a reinforcing power supply cell capable of reinforcing and supplying a substrate or well potential from a power supply wiring is inserted.

In the eleventh aspect of the present invention, the second step in the layout design method of the tenth aspect is to arrange the reinforcing power supply cells at substantially constant intervals in the cell row.

According to a twelfth aspect of the present invention, in the layout designing method of the tenth aspect, the first step includes providing a plurality of the cell rows, and the second step includes: The cells are arranged in each of the cell rows so as to be substantially linear in a direction orthogonal to the cell rows.

[0030]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 is a diagram showing a layout structure of a semiconductor device according to a first embodiment of the present invention. In the figure, (a) is a plan view showing a layout structure of a cell in which a substrate or well potential and a power supply potential are separated from each other,
1B is a sectional view taken along line AA of FIG. 1A, and FIG.
It is a BB sectional view of (a).

In FIG. 1A, TP1 is a P-type MOS transistor (hereinafter, referred to as "PMOS") comprising a source / drain and a gate electrode formed by a high-concentration P-type impurity diffusion region 101 on an N well. Yes, TN1
Is an N-type MOS transistor (hereinafter referred to as NMOS) comprising a source / drain formed by the high-concentration N-type impurity diffusion region 102 on the P-well and a gate electrode.

Reference numeral 103 denotes a high-concentration N-type impurity diffusion region formed on the N-well separately from the high-concentration P-type impurity diffusion region 101 to supply the substrate or well potential of the PMOS TP1; The NMOS T is formed separately from the high-concentration N-type impurity diffusion region 102.
High concentration P for feeding the substrate or well potential of N1
Type impurity diffusion region.

The first and second wiring layers are formed on the upper layer of the substrate. In the first wiring layer, the high concentration N
Potential NWVDD above the impurity diffusion region 103
(Hereinafter referred to as “NWVDD wiring”) 1
A wiring (hereinafter referred to as “P”) supplied with a negative potential PWVSS is provided above the high-concentration P-type impurity diffusion region 104.
WVSS wiring ”) 106 is provided. In the second wiring layer, a wiring to which a positive power supply potential VDD is supplied (hereinafter referred to as “VDD”) is provided above the NWVDD wiring 105.
The wiring 107) is provided, and the PWVSS wiring 10 is provided.
A wiring 108 (hereinafter referred to as “VSS wiring”) to which the negative power supply potential VSS is supplied is provided above the wiring 6. 1A, the high-concentration N-type impurity diffusion region 103 and the NWVDD wiring 105 are
The high-concentration P-type impurity diffusion region 104 and the PWVSS wiring 106 are shown prior to the VSS wiring 108 over the D wiring 107.

The NWVDD wiring 105 and the N-type impurity diffusion region 103 are connected by a contact hole, whereby a positive potential NWVDD is supplied to the PMOS TP1 as a substrate or well potential. Also,
The VDD wiring 107 and the P-type impurity diffusion region 101 are connected to the wiring 11 provided in the contact hole and the first wiring layer.
1 through which the PMOS T
The power supply potential VDD is supplied as the source potential of P1.

On the other hand, the PWVSS wiring 106 and the P-type impurity diffusion region 104 are connected by a contact hole, so that a negative potential PWVSS is supplied to the NMOS TN1 as a substrate or well potential. In addition, the VSS wiring 108 and the N-type impurity diffusion region 102 are connected via a contact hole and a wiring 112 provided in the first wiring layer.
The power supply potential VSS is supplied as the source potential of TN1.

In FIG. 1B, the high concentration P
Type impurity diffusion region 104 has salicide layer 109. Here, “salicide” refers to a high melting point metal silicide formed in a self-aligned manner, and by forming an alloy of an impurity diffusion region and a high melting point metal layer such as tungsten, titanium, and cobalt by heat treatment or the like, The resistance has been reduced. Note that the salicide layer 109 is not necessarily required if it is electrically connected to the PWVSS wiring 106.

In FIG. 1C, an impurity diffusion region 102 serving as a first impurity diffusion region forming the source of the NMOS TN1 and a second substrate or a well for supplying power are supplied.
Is electrically insulated from the impurity diffusion region 104 as the impurity diffusion region by the element isolation region 110. The element isolation region 110 is an STI (Shallow-Trench-Isolatio).
n) It has a structure or the like and is formed of an insulating film such as SiO ₂ .

Impurity diffusion region 102 forming source
Are electrically connected to a VSS wiring 108 serving as a second wiring provided in the second wiring layer via a wiring 112 serving as a first wiring provided in the first wiring layer.
Impurity diffusion region 104 for supplying a substrate or well potential
Is a PWV as a reinforcement wiring through a contact hole
It is electrically connected to the SS wiring 106. The VSS wiring 108 is provided so as to overlap with the impurity diffusion region 104 when viewed from the direction perpendicular to the substrate surface.
The wiring 106 is provided separately from the wiring 112 in a portion of the first wiring layer that overlaps with the impurity diffusion region 104 and the VSS wiring 108 when viewed from the direction perpendicular to the substrate surface.

As described above, in the layout structure shown in FIG. 1, the substrate or well potential can be supplied as a potential independent of the power supply potential. Further, since the wiring 106 of the wiring layer having a sheet resistance lower by one digit or more than the impurity diffusion region is connected to the impurity diffusion region 104 for supplying the substrate or well potential, the potential drop in the substrate or well potential supply path is reduced. Can be prevented, and the substrate or well potential can be further stabilized. Moreover,
The wiring 106 includes the impurity region 104 and the VSS wiring 108
The cell area is not increased by providing the wiring 106 because the wiring 106 is provided in a portion overlapping with. That is,
The substrate or well potential can be stabilized without increasing the cell area, thereby improving the reliability of the LSI operation.

In FIGS. 1B and 1C, the NMOS is used.
Although only the cross-sectional structure of TN1 is shown, the PMOS TP
The cross-sectional structure of No. 1 is similar to the above, except that the potential to be supplied is different.

It is preferable that the first wiring layer is formed of a conductive high melting point material such as tungsten. In this case, if the wiring width and the wiring film thickness are the same, the resistance to EM or the like is increased by about three digits as compared with aluminum wiring or copper wiring. For this reason,
Since the wiring capacitance can be reduced by reducing the wiring film thickness,
The performance of the LSI can be greatly improved. However, when the thickness of the wiring is reduced, the sheet resistance becomes higher by about two digits than that of the aluminum wiring or the like, so that it is not suitable as a global wiring for connecting cells or blocks.
For this reason, it is preferable that the first wiring layer is used for wiring in the cell.

As described above, according to the first embodiment, in a layout structure capable of supplying the substrate or well potential independently of the power supply potential, the impurity diffusion region for supplying the substrate or well potential and the wiring for supplying the power supply potential are provided. Since the reinforcing wiring for preventing the potential drop of the substrate or well potential is provided in the overlapped portion, the potential drop of the substrate or well potential can be suppressed while suppressing an increase in the layout area. As a result, the substrate or well potential is stabilized, the threshold voltage of the transistor does not fluctuate, the reliability of the LSI operation is increased, and the standby leak current can be effectively suppressed.

(Second Embodiment) FIG. 2 is a diagram showing a layout structure of a semiconductor device according to a second embodiment of the present invention. In the figure, (a) is a plan view showing a layout structure of a cell in which a substrate or well potential and a power supply potential are separated from each other,
1B is a cross-sectional view taken along the line CC of FIG. 1A, and FIG.
It is DD sectional drawing of (a).

In FIG. 2A, TP2 is a PMOS comprising a source / drain and a gate electrode formed by a high-concentration P-type impurity diffusion region 201 on an N-well, and TN2 is a high-concentration N on a P-well. Type impurity diffusion region 2
This is an NMOS comprising a source / drain and a gate electrode formed by O.2.

Reference numeral 203 denotes a high-concentration N-type impurity diffusion region formed separately from the high-concentration P-type impurity diffusion region 201 on the N-well to supply a substrate or well potential of the PMOS TP2; The NMOS T is formed separately from the high-concentration N-type impurity diffusion region 202.
High concentration P for feeding substrate or well potential of N2
Type impurity diffusion region.

The first and second wiring layers are formed on the upper layer of the substrate. In the second wiring layer, the high concentration N
A VDD wiring 207 is provided above the p-type impurity diffusion region 203, and a VSS wiring 208 is provided above the high-concentration P-type impurity diffusion region 204. In the first wiring layer, the wiring 205 electrically connected to the VDD wiring 207 by the contact hole and the VSS wiring 2
A wiring 206 is provided, which is electrically connected to the contact hole 08 by a contact hole. For convenience of illustration, FIG.
3A, the high-concentration N-type impurity diffusion region 203 and the wiring 205 are shown prior to the VDD wiring 207.
The high-concentration P-type impurity diffusion region 204 and the wiring 206
It is shown prior to the SS wiring 208.

The PMOS TP2 has a positive potential NW from the N-type impurity diffusion region 203 as a substrate or well potential.
VDD is supplied. Further, the VDD wiring 207 and the P-type impurity diffusion region 201 are connected via a contact hole and a wiring 205 provided in the first wiring layer, whereby the power supply potential VDD is supplied as the source potential of the PMOS TP2. Is done.

On the other hand, a negative potential PWVSS is supplied to the NMOS TN2 from the P-type impurity diffusion region 204 as a substrate or well potential. In addition, the VSS wiring 20
8 and the N-type impurity diffusion region 202 are connected via a contact hole and a wiring 206 provided in the first wiring layer, whereby the power supply potential VSS is supplied as the source potential of the NMOS TN2.

In FIG. 2B, the high concentration P
Type impurity diffusion region 204 has salicide layer 209.

In FIG. 3C, an impurity diffusion region 202 serving as a first impurity diffusion region for forming a source of the NMOS TN2 and a second substrate or a well for supplying electric potential.
Is electrically insulated from the impurity diffusion region 204 as the impurity diffusion region by the element isolation region 210. The element isolation region 210 has an STI structure or the like, and is formed of an insulating film such as SiO ₂ .

Impurity diffusion region 202 forming source
Are electrically connected to a VSS wiring 208 as a second wiring provided in the second wiring layer via a wiring 206 as a first wiring provided in the first wiring layer.
Impurity diffusion region 204 for supplying a substrate or well potential
Is supplied with a negative potential PWVSS. VSS wiring 2
08 is provided so as to overlap with the impurity diffusion region 204 as viewed from the direction perpendicular to the substrate surface.
Is provided so as to extend to a portion of the first wiring layer which overlaps with the impurity region 204 and the VSS wiring 208 as viewed from the direction perpendicular to the substrate surface.

As described above, in the layout structure shown in FIG. 2, the substrate or well potential can be supplied as an independent potential separated from the power supply potential. Further, the wiring 206 of the first wiring layer for connecting the VSS wiring 208 and the impurity diffusion region 202 forming the source is
Further, since the wiring extends to a portion overlapping with the VSS wiring 208, a potential drop in a power supply potential supply path can be prevented without increasing the wiring width of the VSS wiring 208, and the power supply potential can be further stabilized. Thereby, the degree of freedom of the wiring layout in the second wiring layer is improved. In addition, the wiring 206 is formed between the impurity region 104 and the VS.
The cell area does not increase due to the expansion of the wiring width of the wiring 206 because the wiring extends to a portion overlapping the S wiring 108.

In FIGS. 2B and 2C, the NMOS is used.
Although only the sectional structure of TN2 is shown, the PMOS TN
The cross-sectional structure of No. 2 is similar to the above, except that the potential to be supplied is different.

As described above, according to the second embodiment, in a layout structure capable of supplying the substrate or well potential independently of the power supply potential, the impurity diffusion region for supplying the substrate or well potential and the wiring for supplying the power supply potential are provided. Since the wiring connecting them was extended to the overlapping part,
It is possible to suppress a drop in the power supply potential while suppressing an increase in the layout area. As a result, the degree of freedom of the wiring layout in the second wiring layer is increased, and the cell packing ratio can be improved.

(Third Embodiment) By including cell data having a layout structure as shown in FIG. 1 or FIG. 2 in a standard cell library, the man-hour for layout design of a semiconductor device can be greatly reduced. . That is, in the layout structure shown in FIG. 1 or FIG. 2, although the substrate or well potential can be supplied independently of the power supply potential, the substrate or well potential and power supply can be supplied only by providing a contact hole in this structure. A layout structure sharing a potential can be easily generated.

FIG. 3 is a diagram for explaining a layout design method according to the present embodiment. The layout structure shares the substrate or well potential and the power supply potential from the layout structure in which the substrate or well potential is separated from the power supply potential. It is a figure showing the result of having changed to. In the figure, (a) is a change from the layout structure of FIG. 1, and (b) is a change from the layout structure of FIG.

In FIG. 3A, the VSS wiring 108 provided in the second wiring layer and the wiring 1 provided in the first wiring layer are shown.
06, a contact hole 121 for electrically connecting them is provided. Thereby, NM
A negative power supply potential VSS is supplied as a substrate or well potential of the OS TN1. In FIG. 3B, the wiring 2 provided in the first wiring layer and connected to the VSS wiring 208 is shown.
A contact hole 221 for electrically connecting the P-type impurity diffusion region 204 and the high-concentration P-type impurity diffusion region 204 on the P well is provided. Thereby, the NMOS T
Negative power supply potential VSS as substrate or well potential of N2
Is fed.

When a layout design is performed using cell data having a layout structure as shown in FIG. 1 or FIG. 2, provision of the contact holes 121 or 221 makes it extremely easy to set the substrate or well potential and the power supply potential. Can be shared. Therefore, for example, there is no need to control the threshold voltage of the MOS transistor,
When realizing simplification of LSI design such as reduction of the number of power supply wirings and power supply pins by sharing the substrate or well potential and the power supply potential, as shown in FIG.
Or 221 may be provided. On the other hand, when it is desired to separate the substrate or well potential from the power supply potential in order to control the threshold voltage of the MOS transistor, the contact hole 12
Without providing 1 or 221, the wiring 106 and the VSS wiring 108 or the wiring 206 and the impurity diffusion region 204 may be electrically disconnected.

When a large number of cell data in the cell library has a layout structure as shown in FIG. 1 or FIG. 2, the modification for sharing the substrate or well potential and the power supply potential can be easily performed by mask processing or the like. Can be easily performed by a simple process. For this reason, it is possible to avoid an increase in the TAT and man-hours required for newly creating and modifying the cell library.

In the PMOS TP1 shown in FIG. 1, a positive power supply potential VDD can be supplied as a substrate or well potential by providing a contact hole between the VDD wiring 107 and the NWVDD wiring 105. Also, for the PMOSTP2 of FIG.
By providing a contact hole between the wiring 205 of the first wiring layer connected to the D wiring 207 and the high-concentration N-type impurity diffusion region 203 on the N well, a positive power supply potential VDD is supplied as a substrate or well potential. Can be done.

As described above, according to the present embodiment, in the structure in which the wiring for supplying the power supply potential provided in the second wiring layer and the impurity diffusion region for supplying the substrate or well potential have an overlap, A layout design is performed using cell data in which wiring is provided in the wiring layer. In this cell data, a structure for sharing a substrate or well potential and a power supply potential and a structure for separating the same depending on the presence or absence of a contact hole can both be easily generated, and the design efficiency is significantly improved.

(Fourth Embodiment) In a fourth embodiment of the present invention, a layout is configured by arranging a plurality of cells having impurity diffusion regions for supplying a substrate or well potential different from a power supply potential in series. In this case, a reinforcing power supply cell for performing the reinforcing power supply is arranged between the cells. Thus, a potential drop in the power supply path of the substrate or well potential can be prevented, and the substrate or well potential can be further stabilized.

FIG. 4 is a diagram showing an example of a layout structure of a reinforcing power supply cell according to this embodiment. In the figure, (a)
FIG. 4B is a plan view, FIG. 4B is a cross-sectional view taken along line E-E of FIG.
FIG. 5 is a sectional view taken along line FF of FIG. The reinforcing power supply cell shown in FIG. 4 corresponds to the cell having the layout structure of FIG. 1 according to the first embodiment.

In FIG. 4A, a high-concentration N-type impurity diffusion region 3 serving as a power supply impurity diffusion region is formed on the N well.
01 is provided. This power supply impurity diffusion region 30
1 is configured such that when the cell shown in FIG. 1 is adjacent to this reinforcing power supply cell, it is electrically connected to the impurity diffusion region 103 of the adjacent cell to which a substrate or well potential is supplied. I have. A VDD wiring 303 is provided in the second wiring layer above the power supply impurity diffusion region 301. The VDD wiring 303 is adjacent to the reinforcing power supply cell when the cell shown in FIG. Is configured to be electrically connected to the VDD wiring 107 included in the cell. Further, the power supply impurity diffusion region 3
01 is drawn out to a region that does not overlap with the VDD wiring 303, and is connected to the power supply wiring 305.

Similarly, a high-concentration P-type impurity diffusion region 302 as a power supply impurity diffusion region is provided on the P well. When the cell shown in FIG. 1 is adjacent to the reinforcing power supply cell, the power supply impurity diffusion region 302 is electrically connected to the impurity diffusion region 104 of the adjacent cell to which a substrate or well potential is supplied. like,
It is configured. In the second wiring layer above the power supply impurity diffusion region 302, a VSS wiring 304 is provided. When the cell shown in FIG. 1 is adjacent to the reinforcing power supply cell, the VSS wiring 304 The cell is configured to be electrically connected to the VSS wiring 108 of the cell. Further, the power supply impurity diffusion region 302 is VS
It is drawn out to a region that does not overlap with the S wiring 304,
It is connected to the power supply wiring 306.

In FIG. 4B, the power supply impurity diffusion region 302 is connected to a wiring 307 provided in the first wiring layer and a power supply wiring 306 provided in the second wiring layer via a contact hole. ing. Further, a portion of the power supply impurity diffusion layer 302 extended from below the VSS wiring 304 is separated from an adjacent cell by an element isolation region 308 such as an STI, and the wirings 306 and 3 connected thereto are separated.
07 is also separated from the cell boundary. Reference numeral 309 denotes a salicide layer formed on the power supply impurity diffusion region 302.

As can be seen from FIG.
The wiring 304 and the power supply wiring 306 are electrically insulated. Therefore, the power supply potential VS
A negative potential NWVSS different from S can be supplied.

The reinforcing power supply cell as shown in FIG.
By properly inserting the cell into the cell row composed of the cells having the layout structure shown in (1) and supplying the potential to the power supply wirings 305 and 306, the potential drop of the substrate or well potential can be avoided.

FIG. 5A is a plan view showing a layout structure in which the reinforcing power supply cells shown in FIG. 4 are inserted in the cell rows in which the cells shown in FIG. 1 are arranged in series. In FIG. 5A, FIG.
As shown in the circuit diagram of (b), inverters are connected in three stages in series, and a reinforcing power supply cell is arranged between the second and third inverters.

In the layout structure shown in FIG. 1, an impurity diffusion region 103 for supplying a substrate or well potential is provided.
104 and the reinforcing wirings 105 and 106 of the first wiring layer connected thereto extend to both ends of the cell. Therefore, when the cells of FIG. 1 are arranged in series, as shown in FIG. 5, the impurity diffusion regions 103 and 104 and the reinforcing wirings 105 and 106 are respectively connected continuously.
Similarly, the VDD wiring 107 and the VSS wiring 108
Extend to both ends of the cell, when the cells are arranged side by side, the VDD wiring 107 and the VSS wiring 108
Are continuously connected.

Here, by arranging the reinforcing power supply cells shown in FIG. 4 between the cells, a positive potential NWVDD is supplied from the power supply wiring 305, a negative potential PWVSS is supplied from the power supply wiring 306, and the substrate or the well. Each of them can be supplied with power to reinforce the potential. Then, even if the reinforcing power supply cells shown in FIG. 4 are arranged between the cells, the impurity diffusion regions 103 and 104, the reinforcing wires 105 and
6. The continuity of the VDD wiring 107 and the VSS wiring 108 is not impaired.

In the structure shown in FIG. 4, the power supply impurity diffusion regions 301 and 302 themselves are connected to the VDD wiring 303 or VS.
Although the wiring is drawn from below the S wiring 304, the wiring in the first wiring layer may be drawn instead or together with this.

FIG. 6 is a diagram showing another example of the layout structure of the reinforcing power supply cells according to the present embodiment. In the figure,
6A is a plan view, FIG. 6B is a sectional view taken along line GG of FIG.
FIG. 7C is a sectional view taken along line HH of FIG. The reinforcing power supply cell shown in FIG. 6 corresponds to the cell having the layout structure of FIG. 2 according to the second embodiment.

In FIG. 6A, a high-concentration N-type impurity diffusion region 4 serving as a power supply impurity diffusion region is formed on the N well.
01 is provided. This power supply impurity diffusion region 40
1 is configured such that when the cell shown in FIG. 2 is adjacent to this reinforcing power supply cell, it is electrically connected to the impurity diffusion region 203 of the adjacent cell to which a substrate or well potential is supplied. I have. In addition, a VDD wiring 403 is provided in the second wiring layer above the power supply impurity diffusion region 401, and this VDD wiring 403 is adjacent when the cell shown in FIG. Is configured to be electrically connected to the VDD wiring 207 included in the cell. Further, the power supply impurity diffusion region 4
01 is extended to a region that does not overlap with the VDD wiring 403 and is connected to the power supply wiring 405.

Similarly, a high-concentration P-type impurity diffusion region 402 as a power supply impurity diffusion region is provided on the P well. When the cell shown in FIG. 2 is adjacent to the reinforcing power supply cell, the power supply impurity diffusion region 402 is electrically connected to the impurity diffusion region 204 of the adjacent cell to which a substrate or well potential is supplied. like,
It is configured. In addition, a VSS wiring 404 is provided in the second wiring layer above the power supply impurity diffusion region 402. When the cell shown in FIG. 2 is adjacent to the reinforcing power supply cell, the VSS wiring 404 is adjacent. The cell is configured to be electrically connected to the VSS wiring 208 included in the cell. Further, the power supply impurity diffusion region 342 is VS
It is drawn out to a region that does not overlap with the S wiring 404,
It is connected to the power supply wiring 406.

In FIG. 6B, the power supply impurity diffusion region 402 is connected to the wiring 407 provided in the first wiring layer and the power supply wiring 406 provided in the second wiring layer via a contact hole. ing. Further, a portion of the power supply impurity diffusion layer 402 that is drawn from below the VSS wiring 404 is separated from an adjacent cell by an element isolation region 408 such as an STI, and the wirings 406 and 4 connected thereto are separated.
07 is also separated from the cell boundary. Reference numeral 409 denotes a salicide layer formed on the power supply impurity diffusion region 402.

As can be seen from FIG.
The wiring 404 and the power supply wiring 406 are electrically insulated. Therefore, the power supply potential VS
A negative potential NWVSS different from S can be supplied.

The reinforcing power supply cell as shown in FIG.
By appropriately inserting the cell into the cell row composed of the cells having the layout structure shown in (1) and supplying the potential to the power supply wirings 405 and 406, the potential drop of the substrate or well potential can be avoided. In the layout structure shown in FIG. 2, a potential drop of the substrate or well potential is more likely to occur than in the layout structure shown in FIG. 1, but it is possible to avoid this by using a reinforcing power supply cell as shown in FIG. it can.

FIG. 7 is a plan view showing a layout structure in which the reinforcing power supply cells shown in FIG. 6 are inserted into the cell rows in which the cells shown in FIG. 2 are arranged in series. In FIG. 7, similarly to FIG. 5A, three stages of inverters are connected in series as shown in the circuit diagram of FIG. 5B, and a reinforcing power supply is provided between the second and third stages of inverters. The cell is located.

In the layout structure shown in FIG. 2, an impurity diffusion region 203 for supplying a substrate or well potential is provided.
204 extends to both ends of the cell. Therefore, when the cells of FIG. 2 are arranged in series, as shown in FIG. 7, the impurity diffusion regions 203 and 204 are connected continuously. Similarly, the VDD wiring 207 and the VSS wiring 208 and the wiring 2 of the first wiring layer
05 and 206 also extend to both ends of the cell, when the cells are arranged side by side, the VDD wiring 207 and the VS
The S wiring 208 and the wirings 205 and 206 are connected continuously.

Here, by arranging the reinforcing power supply cells shown in FIG. 6 between the cells, a positive potential NWVDD is supplied from the power supply wiring 405, a negative potential PWVSS is supplied from the power supply wiring 406, and the substrate or the well. Each of them can be supplied with power to reinforce the potential. Then, even if the reinforcing power supply cells shown in FIG. 6 are arranged between the cells, the impurity diffusion regions 203 and 204, the wirings 205 and 206, and the V
The continuity of the DD wiring 207 and the VSS wiring 208 is not impaired.

FIG. 8 is a diagram showing an example of a layout structure in which reinforcing power supply cells as shown in FIG. 4 or 6 are arranged. In FIG. 8, reference numeral 321 denotes a cell, 322 denotes a reinforcing power supply cell, and 323 denotes a potential reinforcing wiring. Each cell row is configured by arranging a plurality of cells 321 in series, and the reinforcing power supply cells 322 are arranged at substantially constant intervals in each cell row. Further, in the upper layer of the layout structure, the potential reinforcing wires 3 arranged in a direction orthogonal to the cell rows are provided.
23, the reinforcing power supply cells 322 are arranged in each cell row so as to be substantially linear in a direction orthogonal to the cell row.

In recent LSIs, the chip size tends to be determined according to the area occupied by the wiring. In addition, the reinforcing power supply cell 322 is arranged below the potential reinforcing wiring 323 as shown in FIG. Therefore, the layout area hardly increases by inserting the reinforcing power supply cells.

FIG. 9 is a diagram showing another example of a layout structure in which reinforcing power supply cells are arranged. As shown in FIG. 9, the reinforcing power supply cell 322 does not necessarily need to be arranged below the potential reinforcing wiring 323. By arranging in the vicinity of the potential reinforcing wiring 323, the potential reinforcing wiring 323 can be extended and connected. As described above, by relaxing the restriction on the arrangement of the reinforcing power supply cells 322, the degree of freedom of arrangement of the cells 321 having different cell widths is improved. As a result, an effect that the layout area is reduced is obtained.

[0086]

As described above, according to the present invention, in a structure in which the substrate or well potential can be supplied as an independent potential separated from the power supply potential, the substrate or well potential can be stabilized without increasing the layout area. Or stabilization of the power supply potential can be realized. In addition, a structure in which the substrate or well potential and the power supply potential are shared and a structure in which the power supply potential is separated can be easily generated, and the design efficiency of the layout design is significantly improved.

[Brief description of the drawings]

FIGS. 1A and 1B are diagrams showing a layout structure of a semiconductor device according to a first embodiment of the present invention, wherein FIG. 1A is a layout plan view, and FIGS.

FIGS. 2A and 2B are diagrams showing a layout structure of a semiconductor device according to a second embodiment of the present invention, wherein FIG. 2A is a layout plan view, and FIGS.

3A and 3B are diagrams for explaining a layout design method according to a third embodiment of the present invention, wherein FIG. 3A is a diagram in which contact holes are provided in the layout structure of FIG. 1, and FIG.
FIG. 5 is a diagram in which contact holes are provided in the layout structure of FIG.

4A and 4B are diagrams illustrating an example of a layout structure of a reinforcing power supply cell according to a fourth embodiment of the present invention, where FIG. 4A is a layout plan view, and FIGS. 4B and 4C are cross-sectional views.

5A is a plan view showing a layout structure in which the reinforcing power supply cells of FIG. 4 are inserted, and FIG. 5B is a circuit diagram showing the structure of FIG.

FIGS. 6A and 6B are diagrams showing another example of the layout structure of the reinforcing power supply cell according to the fourth embodiment of the present invention, wherein FIG. 6A is a layout plan view, and FIGS. is there.

7 is a plan view showing a layout structure in which the reinforcing power supply cells of FIG. 6 are inserted.

FIG. 8 is a diagram showing an example of a layout structure in which reinforcing power supply cells are arranged.

FIG. 9 is a diagram showing an example of a layout structure in which reinforcing power supply cells are arranged.

FIG. 10 is a diagram showing an example of a conventional cell layout structure.

FIG. 11 is a diagram illustrating an example of a conventional cell layout structure, and is a diagram illustrating a structure in which a substrate or well potential and a power supply potential are separated and power can be supplied.

FIG. 12 is a diagram showing an example of a conventional cell layout structure, and is a diagram showing a structure in which a substrate or well potential and a power supply potential are separated so that power can be supplied.

[Explanation of symbols]

VDD Positive power supply potential VSS Negative power supply potential NWVDD Positive potential (substrate or well potential) PWVSS Negative potential (substrate or well potential) 101, 201 High-concentration P-type impurity diffusion region (first impurity diffusion region) 102, 202 High concentration N-type impurity diffusion region (first impurity diffusion region) 103, 203 High concentration N-type impurity diffusion region (second impurity diffusion region) 104, 204 High concentration P-type impurity diffusion region (second impurity diffusion region) Area) 105 NWVDD wiring (reinforcing wiring) 106 PWVSS wiring (reinforcing wiring) 107, 207 VDD wiring (second wiring) 108, 208 VSS wiring (second wiring) 111 wiring (first wiring) 112 wiring (First wiring) 206 Wiring (first wiring) 109,209 Salicide layer 121,221 Contact hole 30 1,302,401,402 Power supply impurity diffusion region 305,306,405,406 Power supply wiring 321 cell 322 Reinforcement power supply cell

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 27/04 H01L 27/04 D 21/822 27/08 321B F term (Reference) 5F033 HH19 KK01 KK19 KK26 KK27 KK28 MM05 QQ37 QQ70 QQ73 RR04 UU05 VV00 VV04 VV05 XX03 XX10 XX25 5F038 CA03 CA07 CA17 CD04 5F048 AA00 AA01 AB04 AC03 BA01 BE03 BE09 BF06 BF07 BF12 BF16 BF17 BG14 5F004 AA05 CC12 DD12

Claims (12)

[Claims] 1. A first impurity diffusion region formed on a substrate surface and a second impurity formed on the substrate surface separately from the first impurity diffusion region for supplying a substrate or well potential. A diffusion region, a first wiring provided on a first wiring layer formed on the substrate, and electrically connected to the first impurity diffusion region; and a first wiring formed on the first wiring layer. In the second wiring layer,
The first impurity diffusion region is provided so as to overlap with the second impurity diffusion region when viewed from a direction perpendicular to the substrate surface, is electrically connected to the first wiring, and supplies a power supply potential to the first impurity diffusion region. A second wiring of the first wiring layer as viewed from a direction perpendicular to the substrate surface;
A reinforcing wiring, which is provided separately from the first wiring in a portion overlapping with the impurity diffusion region and the second wiring, and which is electrically connected to the second impurity diffusion region. And a layout structure of the semiconductor device. 2. A first impurity diffusion region formed on a substrate surface and a second impurity formed on the substrate surface separately from the first impurity diffusion region to supply a substrate or well potential. A diffusion region, a first wiring provided on a first wiring layer formed on the substrate, and electrically connected to the first impurity diffusion region; and a first wiring formed on the first wiring layer. In the second wiring layer,
The first impurity diffusion region is provided so as to overlap with the second impurity diffusion region when viewed from a direction perpendicular to the substrate surface, is electrically connected to the first wiring, and supplies a power supply potential to the first impurity diffusion region. Wherein the first wiring extends to a portion of the first wiring layer overlapping the second impurity diffusion region and the second wiring when viewed from a direction perpendicular to the substrate surface. A layout structure of a semiconductor device, characterized in that: 3. The layout structure of a semiconductor device according to claim 1, wherein a salicide layer is formed on surfaces of said first and second impurity diffusion regions. . 4. The semiconductor device according to claim 1, wherein said first wiring layer is formed of a conductive high-melting material such as tungsten. Layout structure. 5. A layout design method using a cell library, wherein at least one of the cell data included in the cell library includes: a first impurity diffusion region formed on a substrate surface; A second impurity diffusion region formed separately from the first impurity diffusion region for supplying a substrate or well potential; and a first wiring layer formed on an upper layer of the substrate; A first wiring connected to the impurity diffusion region of the first and second wiring layers formed on the first wiring layer;
The first impurity diffusion region is provided so as to overlap with the second impurity diffusion region when viewed from a direction perpendicular to the substrate surface, is electrically connected to the first wiring, and supplies a power supply potential to the first impurity diffusion region. A second wiring of the first wiring layer as viewed from a direction perpendicular to the substrate surface;
Provided at a portion overlapping with the impurity diffusion region and the second wiring, separately provided from the first wiring, and provided with a reinforcing wiring electrically connected to the second impurity diffusion region. When the substrate or well potential and the power supply potential are shared by the cell, a contact hole is provided to electrically connect the second wiring and the reinforcing wiring, while the substrate or well potential is provided. A step of electrically disconnecting the second wiring and the reinforcing wiring when the power supply potential and the power supply potential are separated from each other. 6. A layout design method using a cell library, wherein at least one of cell data included in the cell library includes: a first impurity diffusion region formed on a substrate surface; A second impurity diffusion region formed separately from the first impurity diffusion region for supplying a substrate or well potential.
An impurity diffusion region, a first wiring provided in a first wiring layer formed on the substrate, and electrically connected to the first impurity diffusion region; and an upper layer of the first wiring layer. In the second wiring layer formed in
The first impurity diffusion region is provided so as to overlap with the second impurity diffusion region when viewed from a direction perpendicular to the substrate surface, is electrically connected to the first wiring, and supplies a power supply potential to the first impurity diffusion region. And the first wiring extends to a portion of the first wiring layer overlapping the second impurity diffusion region and the second wiring when viewed from a direction perpendicular to the substrate surface. When the substrate or the well potential and the power supply potential are shared by the cell, the first wiring and the second impurity diffusion region are electrically connected by providing a contact hole. On the other hand, when the potential of the substrate or the well is separated from the potential of the power supply, a step of electrically disconnecting the first wiring and the second impurity diffusion region is provided. A total way. 7. A power supply potential comprising: a cell row in which a plurality of cells are arranged in series; and a reinforcing power supply cell arranged in the cell row, somewhere between the cells. And an impurity diffusion region for supplying a substrate or well potential different from the above. The impurity diffusion region is electrically connected between adjacent cells, and the reinforcing power supply cell is provided in an adjacent cell. A power supply impurity diffusion region electrically connecting the impurity diffusion region; a power supply impurity diffusion region provided in a wiring layer formed above the power supply impurity diffusion region and electrically connected to the power supply impurity diffusion region. A layout structure of a semiconductor device, comprising wiring. 8. The layout structure of a semiconductor device according to claim 7, wherein said reinforcing power supply cells are arranged at substantially constant intervals in said cell row. 9. The layout structure of a semiconductor device according to claim 7, wherein a plurality of said cell rows are provided, and said reinforcing power supply cells are substantially linear in a direction orthogonal to the cell rows. , The layout structure of the semiconductor device being arranged in each of the cell rows. 10. A first step of arranging a plurality of cells in series to form a cell row, and a second step of arranging a reinforcing power supply cell between the cells in the cell row. Wherein each of the cells has an impurity diffusion region for supplying a substrate or well potential different from a power supply potential, and the impurity diffusion region is electrically connected between adjacent cells. The reinforcing power supply cell is provided in a power supply impurity diffusion region electrically connected to the impurity diffusion region of an adjacent cell, and in a wiring layer formed above the reinforcing power supply impurity diffusion region. A power supply wiring electrically connected to the impurity diffusion region for power supply. 11. The layout design method according to claim 10, wherein in the second step, the reinforcing power supply cells are arranged at substantially constant intervals in the cell row. Method. 12. The layout design method according to claim 10, wherein the first step is to provide a plurality of the cell rows, and the second step is to replace the reinforcing power supply cells with the cell rows. A layout design method in which the cells are arranged in each of the cell rows so as to be substantially linear in a direction orthogonal to.