JP2009158728A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the area of a semiconductor cell by reducing the resistance of a wire. <P>SOLUTION: A semiconductor device includes a semiconductor substrate 1, a contact region 4 formed on the surface of the semiconductor substrate 1, and an interlayer dielectric 21 formed on the semiconductor substrate 1. In the interlayer dielectric 21, an opening groove provided so as to extend linearly to the contact region 4. Then, the semiconductor device further includes a conductive layer 8 embedded in the opening groove and electrically connected with the contact region 4. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device including an impurity diffusion region.

  In recent years, semiconductor devices such as advanced SoCs are required to further reduce the area of a semiconductor cell in order to reduce the chip area. However, if the width of the wiring is reduced in order to reduce the cell area, the resistance of the wiring increases.

  Therefore, various inventions have been made to reduce the resistance related to the wiring. In the semiconductor device described in Patent Document 1, the resistance between the contact and the wiring is lowered by making the contact shape vertically long in the width direction of the transistor. In the semiconductor integrated circuit device described in Patent Document 2, the resistance of the contact region is lowered by forming an extended impurity diffusion region. In the semiconductor device described in Patent Document 3, by forming a source line on the inner wall of the contact groove, the resistance of the wiring is reduced and the number of layers is reduced. In the semiconductor device described in Patent Document 4, a contact groove is formed in the upper layer of the control gate, and a conductive layer is embedded in the groove, thereby reducing the resistance of the wiring.

Japanese Patent Laid-Open No. 2003-7844 JP 2000-353747 A JP-A-11-220112 JP 2000-82805 A

  However, in order to further reduce the cell area, it is necessary to further reduce the resistance related to the wiring.

  The present invention has been made to solve the above-described problems, and aims to reduce resistance related to wiring and reduce the area of a semiconductor cell.

  A semiconductor device according to an embodiment includes a semiconductor substrate, an impurity diffusion region formed on the surface of the semiconductor substrate, and an interlayer insulating film formed on the semiconductor substrate. The interlayer insulating film is provided with an opening groove extending linearly reaching the impurity diffusion region. The semiconductor device further includes a conductive layer embedded in the opening groove and electrically connected to the impurity diffusion region.

  According to the semiconductor device of the present invention, since the resistance related to the wiring can be reduced, the area of the semiconductor device can be reduced.

<Embodiment 1>
A top view of the semiconductor device according to the present embodiment is shown in FIG. The semiconductor device according to the present embodiment will be described as a NOT gate of a cell included in the SoC. As shown in FIG. 1, the semiconductor device according to the present embodiment includes an insulating layer 2, an impurity diffusion region composed of contact regions 3 and 4, source / drain regions 5 and 6, conductive layers 7 and 8, and contacts. A layer 9, metal layers 10, 11, 12, 13 and a gate electrode 14 are provided.

  The insulating layer 2 is formed on the semiconductor substrate 1 and corresponds to, for example, STI (Shallow Trench Isolation). Contact regions 3 and 4 and source / drain regions 5 and 6 are formed on the surface of semiconductor substrate 1. Since FIG. 1 is a top view, the insulating layer 2, the contact regions 3 and 4, and the source / drain regions 5 and 6 appear on the surface.

  In the present embodiment, conductive layers 7 and 8 indicated by dotted lines in FIG. 1 are formed above contact regions 3 and 4 that are impurity diffusion regions. A contact layer 9 indicated by a dotted line in the same figure is formed on each of the source / drain regions 5 and 6. For example, tungsten is used as the material of the contact layer 9.

  A common metal layer 10 is formed on the conductive layer 7 and the contact layer 9 in the upper half of the drawing, and a common metal is formed on the conductive layer 8 and the contact layer 9 in the lower half of the drawing. Layer 11 is formed. In the left half of the drawing, a metal layer 12 is formed on the gate electrode 14. In the right half of the drawing, a common metal layer 13 is formed on the upper contact layer 9 and the lower contact layer 9. In the present embodiment, these metal layers 10, 11, 12, and 13 are used as wiring together with the conductive layers 7 and 8. The metal layers 10, 11, 12, and 13 are formed of, for example, aluminum or copper.

  In the semiconductor substrate 1, an N well and a P well are formed in contact with each other. 1 indicates the boundary between the N well and the P well. In the present embodiment, an N well is formed above the alternate long and short dash line AA ′, and the alternate long and short dash line A A P-well is formed below −A ′.

  In the present embodiment, the contact region 3 formed on the surface of the N-well semiconductor substrate 1 has N + conductivity type, and the source / drain region 5 formed on the surface of the N-well semiconductor substrate 1 has P + conductivity type. Have. On the other hand, the contact region 4 formed on the surface of the P-well semiconductor substrate 1 has P + conductivity type, and the source / drain region 6 formed on the surface of the P-well semiconductor substrate 1 has N + conductivity type. In the following description, the N-well semiconductor substrate 1 may be referred to as an N-conductivity type semiconductor substrate 1, and the P-well semiconductor substrate 1 may be referred to as a P-conductivity type semiconductor substrate 1.

  2 is a cross-sectional view taken along one-dot chain line B-B ′ in FIG. 1. As shown in FIG. 2, the semiconductor device according to the present embodiment includes an N-type MOSFET (Metal Insulator Semiconductor Field Effective Transistor) that is a transistor formed on a P-well semiconductor substrate 1. The N-type MOSFET according to the present embodiment includes a P-conductivity-type semiconductor substrate 1, a gate insulating film 17, a gate electrode 14, an N-conductivity-type extension region 18, an N + -conductivity-type source / drain region 6, Silicide layers 16 and 20 and sidewalls 19 are provided.

  The gate electrode 14 is formed on the P-conductivity type semiconductor substrate 1 via a gate insulating film 17. A silicide layer 20 is formed on the gate electrode 14. The source / drain region 6 is formed on the surface of the P conductivity type semiconductor substrate 1 with the gate electrode 14 interposed therebetween. The extension region 18 is formed so as to overlap with the source / drain region 6, and is provided to extend under the side wall 19. The silicide layer 16 included in the semiconductor device according to the present embodiment is formed on the source / drain region 6. The sidewall 19 is formed adjacent to the side surface of the gate electrode 14.

  As shown in FIG. 2, the semiconductor device according to the present embodiment includes an interlayer insulating film 21 and an insulating film 22. The interlayer insulating film 21 is formed on the P conductivity type semiconductor substrate 1. The metal layers 11 and 13 and the insulating film 22 are formed on the interlayer insulating film 21. The interlayer insulating film 21 is provided with an opening hole (contact hole) formed in a square shape reaching the source / drain region 6, and the contact layer 9 is formed in the opening hole.

  The source / drain region 6 on the left side of the source / drain region 6 shown in FIG. 2 is electrically connected to the metal layer 11 via the contact layer 9, and the source / drain region 6 on the right side of FIG. It is electrically connected to the metal layer 13.

  As described above, the semiconductor device according to the present embodiment includes the N-type MOSFET formed on the lower semiconductor substrate 1 of FIG. 1, that is, the P-well semiconductor substrate 1. The semiconductor device according to the present embodiment includes a P-type MOSFET formed on the upper semiconductor substrate 1 in FIG. 1, that is, the N-well semiconductor substrate 1.

  In FIG. 1, the P-type MOSFET includes an N-conductivity type semiconductor substrate 1, a gate electrode 14, a P + conductivity-type source / drain region 5, a silicide layer (not shown), and an interlayer insulating film. The source / drain region 5 is formed on the surface of the N conductivity type semiconductor substrate 1. A silicide layer (not shown) is formed on the source / drain region 5. An interlayer insulating film (not shown) is formed on the N conductivity type semiconductor substrate 1. The interlayer insulating film is provided with an opening hole formed in a square shape reaching the source / drain region 5, and a contact layer 9 is formed in the opening hole.

  In the P-type MOSFET, the source / drain region 5 on the left side of the source / drain region 5 shown in FIG. 1 is electrically connected to the metal layer 10 via the contact layer 9, and the source / drain region 5 on the right side in FIG. The metal layer 13 and the contact layer 9 are electrically connected.

  The conductive layer 7 applies the potential (VDD) of the power supply voltage from the metal layer 10 to the source / drain region 5 of the P-type MOSFET. The conductive layer 8 applies the ground potential (GND) from the metal layer 11 to the source / drain region 6 of the N-type MOSFET. The metal layer 12 provides input to the gate electrode 14 through a gate contact, and the metal layer 13 derives the outputs of the above-described P-type MOSFET and the above-described N-type MOSFET. As described above, the semiconductor device according to the present embodiment is a NOT gate including the above-described N-type MOSFET and the above-described P-type MOSFET.

  Next, a configuration in which the semiconductor device according to the present embodiment is different from the conventional semiconductor device will be described. 3 is a cross-sectional view taken along one-dot chain line C-C ′ in FIG. 1. As shown in FIG. 3, the semiconductor device according to the present embodiment includes a semiconductor substrate 1, a contact region 4, a conductive layer 8, a metal layer 11, a silicide layer 16, an interlayer insulating film 21, and an insulating film. 22.

  Contact region 4 which is an impurity diffusion region provided in the semiconductor device according to the present embodiment is formed on the surface of P-conductivity type semiconductor substrate 1. The interlayer insulating film 21 is formed on the P conductivity type semiconductor substrate 1. The interlayer insulating film 21 is provided with an opening groove extending linearly reaching the contact region 4. The conductive layer 8 is embedded in the opening groove. The conductive layer 8 is made of a metal such as tungsten. 4 is a cross-sectional view taken along one-dot chain line D-D ′ in FIG. 1. Since the conductive layer 8 is provided so as to be embedded in the above-described opening groove, it extends linearly as shown in FIG.

  As shown in FIG. 3, the silicide layer 16 is formed on the contact region 4 in the present embodiment. Conductive layer 8 is electrically connected to contact region 4 through silicide layer 16. Thus, the conductive layer 8 is buried in the above-described opening groove and is electrically connected to the contact region 4. The contact region 4 applies a ground potential (GND) that is a potential from the conductive layer 8 to the P-conductivity type semiconductor substrate 1 through the silicide layer 16 as the substrate potential of the N-type MOSFET. In the present embodiment, as shown in FIG. 1, the metal layer 11 is formed on the conductive layer 8 on the contact region 4 along the conductive layer 8.

  Although the contact region 4, the conductive layer 8, and the metal layer 11 in FIG. 1 have been described above, the same applies to the contact region 3, the conductive layer 7, and the metal layer 10. That is, the contact region 3 which is an impurity diffusion region provided in the semiconductor device according to the present embodiment is formed on the surface of the N conductivity type semiconductor substrate 1. The interlayer insulating film 21 is formed on the N conductivity type semiconductor substrate 1. The interlayer insulating film 21 is provided with an opening groove extending linearly reaching the contact region 3. The conductive layer 7 is embedded in the opening groove and is electrically connected to the contact region 3 through the silicide layer 16. The contact region 3 applies a power supply voltage potential (VDD), which is a potential from the conductive layer 7, to the N conductive semiconductor substrate 1 through the silicide layer 16 as the substrate potential of the P-type MOSFET described above. In the present embodiment, as shown in FIG. 1, the metal layer 10 is formed on the conductive layer 7 on the contact region 3 along the conductive layer 7.

  Here, the conventional semiconductor device and the semiconductor device according to this embodiment are compared. In the conventional semiconductor device, a conductive layer having the same square shape as the contact layer 9 in FIG. 1 is formed above the contact regions 3 and 4, and a metal layer as a wiring is formed on the conductive layer. The metal layer and the contact regions 3 and 4 are electrically connected via a square conductive layer.

  On the other hand, in the semiconductor device according to the present embodiment, conductive layers 7 and 8 extending linearly are formed above contact regions 3 and 4, and contact regions 3 and 4 are formed of conductive layers 7 and 8. And is electrically connected. As a result, the substantial contact area between the contact region 3 and the conductive layer 7 and between the contact region 4 and the conductive layer 8 is increased, so that the respective resistances between them are reduced. Thus, the width of the metal layers 10 and 11 and the conductive layers 7 and 8 constituting the wiring can be reduced by an amount corresponding to the reduction in resistance, so that the cell area can be reduced.

  In the present embodiment, the silicide layer 16 is formed on the contact regions 3 and 4. Therefore, the respective resistances between contact region 3 and conductive layer 7 and between contact region 4 and conductive layer 8 are reduced. As a result, the width of the metal layers 10 and 11 and the conductive layers 7 and 8 constituting the wiring can be reduced by an amount corresponding to the reduction in resistance, so that the cell area can be reduced.

<Embodiment 2>
FIG. 5 shows a top view of the semiconductor device according to the present embodiment. Hereinafter, of the configuration of the semiconductor device according to the present embodiment, the same configuration as that of the first embodiment is denoted by the same reference numeral, and the configuration not newly described is the same as that of the first embodiment. Shall.

  In the present embodiment, the metal layers 10, 11, 12, and 13 according to the first embodiment are not provided. Instead, a common conductive layer 7 extending linearly is formed on the contact region 3 and the source / drain region 5. A common conductive layer 8 extending linearly is formed on the contact region 4 and the source / drain region 6. On the gate electrode 14, a conductive layer 23 extending in a linear shape is formed. In addition, a common conductive layer 24 extending linearly is formed on the source / drain region 5 and the source / drain region 6. That is, the conductive layers 7, 8, 23, and 24 extended in a linear shape have a role of wiring as well as a role of a contact layer.

  6 is a cross-sectional view taken along one-dot chain line B-B ′ in FIG. 5. As shown in FIG. 6, the semiconductor device according to the present embodiment includes an N-type MOSFET that is a transistor formed on a P-well semiconductor substrate 1. The N-type MOSFET according to the present embodiment includes a P-conductivity-type semiconductor substrate 1, a gate insulating film 17, a gate electrode 14, an N-conductivity-type extension region 18, an N + -conductivity-type source / drain region 6, Silicide layers 16 and 20 and sidewalls 19 are provided.

  The gate electrode 14 is formed on the P-conductivity type semiconductor substrate 1 via a gate insulating film 17. A source / drain region 6, which is an impurity diffusion region provided in the semiconductor device according to the present embodiment, is formed on the surface of a P-conductivity type semiconductor substrate 1 with a gate electrode 14 interposed therebetween. Silicide layer 16 included in the semiconductor device according to the present embodiment is formed on source / drain region 6 which is an impurity diffusion region. As described above, the semiconductor device according to the present embodiment includes an N-type MOSFET that is a transistor having the gate electrode 14 formed on the semiconductor substrate 1 with the gate insulating film 17 interposed therebetween.

  As shown in FIG. 6, the semiconductor device according to the present embodiment includes an interlayer insulating film 21 and an insulating film 22. The interlayer insulating film 21 is formed on the P conductivity type semiconductor substrate 1. The insulating film 22 is formed on the interlayer insulating film 21. The interlayer insulating film 21 is provided with an opening groove extending linearly reaching the source / drain region 6.

  The conductive layer 8 is embedded in the left-side opening groove of the opening grooves shown in FIG. 6 and is electrically connected to the source / drain region 6. The conductive layer 24 is buried in the opening groove on the right side of the opening groove shown in FIG. 6 and is electrically connected to the source / drain region 6.

  As described above, the semiconductor device according to the present embodiment includes an N-type MOSFET that is a transistor formed on the lower semiconductor substrate 1 of FIG. 5, that is, the P-well semiconductor substrate 1. Further, the semiconductor device according to the present embodiment includes a P-type MOSFET which is a transistor formed on the upper semiconductor substrate 1 in FIG. 5, that is, the N-well semiconductor substrate 1.

  The P-type MOSFET according to the present embodiment includes an N-conductivity type semiconductor substrate 1, a gate electrode 14, a P + conductivity-type source / drain region 5, a silicide layer (not shown), and an interlayer insulating film in FIG. 5. Prepare. The source / drain region 5 which is an impurity diffusion layer provided in the semiconductor device according to the present embodiment is formed on the surface of the N conductivity type semiconductor substrate 1. A silicide layer (not shown) is formed on the source / drain region 5. An interlayer insulating film (not shown) is formed on the N conductivity type semiconductor substrate 1. The interlayer insulating film is provided with an opening groove extending linearly reaching the source / drain region 5. The conductive layer 7 is embedded in the left-side opening groove of the opening grooves shown in FIG. 5 and is electrically connected to the source / drain region 5. The conductive layer 24 is embedded in the opening groove on the right side of the opening groove shown in FIG. 5 and is electrically connected to the source / drain region 5.

  The conductive layer 7 gives a potential (VDD) of an external power supply voltage to the source / drain region 5 of the P-type MOSFET. The conductive layer 8 applies a ground potential (GND) from the outside to the source / drain region 6 of the N-type MOSFET. The conductive layer 23 provides an input to the gate electrode 14, and the conductive layer 24 derives the output of the above-described P-type MOSFET and the above-described N-type MOSFET. As described above, the semiconductor device according to the present embodiment is a NOT gate including the above-described N-type MOSFET and the above-described P-type MOSFET.

  FIG. 7 is a cross-sectional view taken along one-dot chain line C-C ′ in FIG. 5. As shown in FIG. 7, the semiconductor device according to the present embodiment includes a semiconductor substrate 1, a contact region 4, a conductive layer 8, a silicide layer 16, an interlayer insulating film 21, and an insulating film 22.

  Contact region 4 which is an impurity diffusion region provided in the semiconductor device according to the present embodiment is formed on the surface of P-conductivity type semiconductor substrate 1. The interlayer insulating film 21 is formed on the P conductivity type semiconductor substrate 1. The interlayer insulating film 21 is provided with an opening groove extending linearly reaching the contact region 4. The conductive layer 8 is embedded in the opening groove. Thus, since the conductive layer 8 is embedded in the above-described opening groove, it extends in a linear shape.

  As shown in FIG. 7, in the present embodiment, the silicide layer 16 is formed on the contact region 4. Conductive layer 8 is electrically connected to contact region 4 through silicide layer 16. Thus, the conductive layer 8 is buried in the above-described opening groove and is electrically connected to the contact region 4. The contact region 4 applies a ground potential (GND) that is a potential from the conductive layer 8 to the P-conductivity type semiconductor substrate 1 through the silicide layer 16 as the substrate potential of the N-type MOSFET.

  Although the contact region 4 and the conductive layer 8 in FIG. 5 have been described above, the same applies to the contact region 3 and the conductive layer 7. That is, the contact region 3 which is an impurity diffusion region provided in the semiconductor device according to the present embodiment is formed on the surface of the N conductivity type semiconductor substrate 1. The interlayer insulating film 21 is formed on the N conductivity type semiconductor substrate 1. The interlayer insulating film 21 is provided with an opening groove extending linearly reaching the contact region 3. The conductive layer 7 is embedded in the opening groove and is electrically connected to the contact region 3 through the silicide layer 16. The contact region 3 applies a power supply voltage potential (VDD) as a potential from the conductive layer 7 to the N-conductivity type semiconductor substrate 1 as a substrate potential of the P-type MOSFET through the silicide layer 16 (not shown). .

  In the semiconductor device according to the present embodiment having the above-described configuration, conductive layers 7 and 8 extending linearly are formed on contact regions 3 and 4, as in the first embodiment. 4 is electrically connected to the conductive layers 7 and 8. As a result, the substantial contact area between the contact region 3 and the conductive layer 7 and between the contact region 4 and the conductive layer 8 is increased, so that the respective resistances between them are reduced. As a result, the width of the conductive layers 7 and 8 constituting the wiring can be reduced by an amount corresponding to the reduction in resistance, so that the cell area can be reduced.

  Further, in the semiconductor device according to the present embodiment, conductive layers 7 and 8 extending linearly are formed on the source / drain regions 5 and 6, and the source / drain regions 5 and 6 8 is electrically connected. As a result, the substantial contact area between the source / drain region 3 and the conductive layer 7 and between the source / drain region 4 and the conductive layer 8 is increased, so that the respective resistances between them are reduced. Thus, the width of the conductive layers 7 and 8 constituting the wiring can be reduced by an amount corresponding to the reduction in resistance, so that the cell area can be reduced.

  In the present embodiment, the metal layers 10, 11, 12, 13 according to the first embodiment are omitted. As a result, the resistance of the wiring is increased, but the cover margin of the metal layers 10, 11, 12, and 13 is not necessary, so that the cell area can be reduced.

<Embodiment 3>
A top view of the semiconductor device according to the present embodiment is shown in FIG. Hereinafter, among the configurations of the semiconductor device according to the present embodiment, the same configurations as those of the second embodiment are denoted by the same reference numerals, and the configurations not newly described are the same as those of the second embodiment. Shall.

  The semiconductor device of this embodiment is different from that of Embodiment 2 in that metal layers 10, 11, 25 are added. The metal layers 10, 11, 25 are formed on the conductive layers 7, 8, 22 along the conductive layers 7, 8, 22.

  FIG. 9 is a cross-sectional view taken along one-dot chain line B-B ′ in FIG. 8. As shown in FIG. 9, the semiconductor device according to the present embodiment includes an interlayer insulating film 21, metal layers 11 and 25, and an insulating film 22. The interlayer insulating film 21 is formed on the P-conductivity type semiconductor substrate 1, and the metal layers 11, 25 and the insulating film 22 are formed on the interlayer insulating film 21. The interlayer insulating film 21 is provided with an opening groove extending linearly reaching the source / drain region 6.

  The conductive layer 8 is embedded in the left-side opening groove of the opening grooves shown in FIG. 9 and is electrically connected to the source / drain region 6. The metal layer 11 is formed on the conductive layer 8 along the conductive layer 8. The conductive layer 24 is embedded in the opening groove on the right side of the opening groove shown in FIG. 9 and is electrically connected to the source / drain region 6. The metal layer 25 is formed on the conductive layer 24 along the conductive layer 24. Note that the cross-sectional view taken along the alternate long and short dash line C-C 'in FIG.

  In the semiconductor device according to the present embodiment having the above configuration, the metal layers 10, 11, 25 are provided on the conductive layers 7, 8, 24, so that the resistance of the conductive layers 7, 8, 24 constituting the wirings is increased. Can be reduced. As a result, the width of the conductive layers 7, 8, 24 constituting the wiring can be reduced by an amount corresponding to the reduction in resistance, so that the cell area can be further reduced.

  In the first embodiment, conductive layers 7 and 8 are provided on contact regions 3 and 4, and contact layer 9 is provided on source / drain regions 5 and 6. A common metal layer 10 is provided on the conductive layer 7 and the contact layer 9, a common metal layer 11 is provided on the conductive layer 8 and the contact layer 9, and a common metal layer 13 is provided only on the contact layer 9. It was.

  In the present embodiment, a common conductive layer 7 is provided on the contact region 3 and the source / drain region 5, and a common conductive layer 8 is provided on the contact region 4 and the source / drain region 6. A common conductive layer 24 was provided on the source / drain region 5 and the source / drain region 6.

  However, the present invention is not limited to these semiconductor devices, but a configuration in which a square contact layer 9 is provided on the contact regions 3 and 4 and linear conductive layers 7 and 8 are provided only on the source / drain regions 5 and 6. You may do. As a result, the substantial contact area between the source / drain region 5 and the conductive layer 7 and between the source / drain region 6 and the conductive layer 8 is increased, so that the respective resistances between them are reduced. In this way, the width of the conductive layers 7 and 8 as wiring can be reduced by the amount of resistance reduction, so that the cell area can be reduced. Further, the metal layer is not limited to FIG. 8, and may be provided only on the contact regions 3 and 4 as shown in FIG.

<Embodiment 4>
A top view of the semiconductor device according to the present embodiment is shown in FIG. Hereinafter, of the configuration of the semiconductor device according to the present embodiment, the same configuration as that of the third embodiment is denoted by the same reference numeral, and the configuration not newly described is the same as that of the third embodiment. Shall.

  As shown in FIG. 11, the source / drain regions 5 and 6 according to the present embodiment extend toward the contact regions 3 and 4. Thus, in the present embodiment, the source / drain regions 5 and 6 and the contact regions 3 and 4 are provided in contact with each other under the conductive layers 7 and 8.

  As a result, the substantial contact area between the source / drain region 5 and the conductive layer 7 and between the source / drain region 4 and the conductive layer 8 is increased, so that the respective resistances between them are reduced. In this way, the width of the conductive layers 7 and 8 as the wiring can be reduced by an amount corresponding to the reduced resistance.

<Embodiment 5>
FIG. 12 shows the configuration of the semiconductor device according to this embodiment. The semiconductor device according to the present embodiment includes NAND gates G30 to G38 formed of semiconductor cells. That is, the semiconductor device according to the present embodiment includes a plurality of semiconductor cells.

  The semiconductor cell includes a high-speed semiconductor cell and a small area semiconductor cell. In the present embodiment, NAND gates G30 to G35 include high-speed semiconductor cells, and NAND gates G36 to G38 include small area semiconductor cells. In the present embodiment, the NAND gates G30 to G35 are critical paths, and the NAND gates G36 to G38 are non-critical paths.

  Here, the semiconductor device shown in FIG. 11 is provided with longer metal layers 10 and 11 than the semiconductor device shown in FIG. 10, and under the source / drain regions 5 and 6 and the conductive layers 7 and 8. The contact regions 3 and 4 are provided in contact with each other. Therefore, the semiconductor device illustrated in FIG. 11 has a larger area but a lower resistance than the semiconductor device illustrated in FIG. Therefore, in this embodiment, the semiconductor device shown in FIG. 11 is used for the high-speed semiconductor cell described above.

  On the other hand, the semiconductor device shown in FIG. 10 is smaller in the portion provided with the metal layers 10 and 11 than the semiconductor device shown in FIG. Therefore, the semiconductor device illustrated in FIG. 10 has a larger resistance than the semiconductor device illustrated in FIG. 11, but the area of the semiconductor device is small. Therefore, in this embodiment, the NOT gate shown in FIG. 10 is used for the above-described small area semiconductor cell. Thus, in this embodiment, the semiconductor device shown in FIGS. 10 and 11 is used for a desired cell among a plurality of semiconductor cells.

  Flip-flops F30 and F31 are provided at the ends of the NAND gates G30 to G35, and flip-flops F32 and F33 are provided at the ends of the NAND gates G36 to G38. Then, according to the input CK, the flip-flops F30 to F33 switch between a path composed of NAND gates G30 to G35 and a path composed of NAND gates G36 to G38.

  In the semiconductor device according to the present embodiment configured as described above, the semiconductor device shown in FIG. 11 is used for the critical path, and the semiconductor device shown in FIG. 10 is used for the non-critical path. As a result, high-speed operation can be ensured in the critical path, and the area of the semiconductor device can be reduced in the non-critical path.

  In this embodiment, the semiconductor device shown in FIGS. 10 and 11 is used as a semiconductor device used in a desired semiconductor cell. However, the semiconductor device is not limited to this, and FIGS. Any of the semiconductor devices shown in FIGS. 10 and 11 may be used.

1 is a top view showing a configuration of a semiconductor device according to a first embodiment. 1 is a cross-sectional view showing a configuration of a semiconductor device according to a first embodiment. 1 is a cross-sectional view showing a configuration of a semiconductor device according to a first embodiment. 1 is a cross-sectional view showing a configuration of a semiconductor device according to a first embodiment. FIG. 6 is a top view showing a configuration of a semiconductor device according to a second embodiment. FIG. 6 is a cross-sectional view showing a configuration of a semiconductor device according to a second embodiment. FIG. 6 is a cross-sectional view showing a configuration of a semiconductor device according to a second embodiment. FIG. 6 is a top view illustrating a configuration of a semiconductor device according to a third embodiment. FIG. 6 is a cross-sectional view showing a configuration of a semiconductor device according to a third embodiment. FIG. 6 is a top view illustrating a configuration of a semiconductor device according to a third embodiment. FIG. 6 is a top view illustrating a configuration of a semiconductor device according to a fourth embodiment. FIG. 10 is a diagram showing a configuration of a semiconductor device according to a fifth embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Semiconductor substrate, 2 Insulating layer, 3, 4 Contact region, 5, 6 Source / drain region, 7, 8, 23, 24 Conductive layer, 9 Contact layer 10, 11, 12, 13, 25 Metal layer, 14 Gate electrode 16, 20 Silicide layer, 17 Gate insulating film, 18 Extension region, 19 Side wall, 20 Silicide layer, 21 Interlayer insulating film, 22 Insulating film, F30-F33 flip-flop, G30-G38 NAND gate.

Claims (8)

A semiconductor substrate;
An impurity diffusion region formed on the surface of the semiconductor substrate;
An interlayer insulating film formed on the semiconductor substrate,
The interlayer insulating film is provided with an opening groove extending linearly reaching the impurity diffusion region,
A conductive layer embedded in the opening groove and electrically connected to the impurity diffusion region;
Semiconductor device. A silicide layer formed on the impurity diffusion region;
The semiconductor device according to claim 1. A metal layer formed on the conductive layer is further provided along the conductive layer.
The semiconductor device according to claim 1 or 2. A transistor formed on the semiconductor substrate;
The impurity diffusion region is
A contact region for applying a potential from the conductive layer to the semiconductor substrate as a substrate potential of the transistor;
The semiconductor device according to claim 1. A gate electrode formed on the semiconductor substrate through a gate insulating film;
The impurity diffusion region is
A source / drain region formed across the gate electrode;
The semiconductor device according to claim 1. A transistor including a gate electrode formed on the semiconductor substrate through a gate insulating film;
The impurity diffusion region is
A contact region for applying a potential from the conductive layer to the semiconductor substrate as a substrate potential of the transistor;
A source / drain region formed across the gate electrode,
The semiconductor device according to claim 1. The source / drain region and the contact region are:
Provided in contact with each other under the conductive layer,
The semiconductor device according to claim 6. A plurality of semiconductor cells,
The semiconductor device according to claim 3 or the semiconductor device according to claim 7 is used for a desired cell among the plurality of semiconductor cells.
Semiconductor device.

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