WO2011077940A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
WO2011077940A1
WO2011077940A1 PCT/JP2010/071884 JP2010071884W WO2011077940A1 WO 2011077940 A1 WO2011077940 A1 WO 2011077940A1 JP 2010071884 W JP2010071884 W JP 2010071884W WO 2011077940 A1 WO2011077940 A1 WO 2011077940A1
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Prior art keywords
region
drain region
semiconductor device
electrode
drain
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PCT/JP2010/071884
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French (fr)
Japanese (ja)
Inventor
正樹 笠原
敦 渡邊
朋潔 亀田
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ミツミ電機株式会社
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Publication of WO2011077940A1 publication Critical patent/WO2011077940A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11803—Masterslice integrated circuits using field effect technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1087—Substrate region of field-effect devices of field-effect transistors with insulated gate characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41758—Source or drain electrodes for field effect devices for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform

Definitions

  • the present invention relates to a semiconductor device, and more particularly to a semiconductor device having a source region and a drain region which are formed in a surface region of a semiconductor substrate and extend opposite to each other.
  • LDMOS Laterally Diffused Metal Metal Oxide Semiconductor, lateral MOS transistor
  • FIG. 7 is a diagram showing an example of a circuit diagram of a step-down DC / DC converter using a conventional LDMOS.
  • the step-down DC / DC converter includes a low-potential side LDMOS 300, a high-potential side LDMOS 301, a control unit 330 that controls the low-potential side LDMOS 300, and a control unit 331 that controls the high-potential side LDMOS 301.
  • Both the low potential side LDMOS 300 and the high potential side LDMOS 301 are n-channel LDMOSs, and the drain of the low potential side LDMOS 300 and the source of the high potential side LDMOS 301 are connected to form a switch terminal SW.
  • the low-potential side LDMOS 300 and the high-potential side LDMOS 301 each have a drain-back gate parasitic diode 310, 311 and a drain-semiconductor substrate parasitic diode 320, 321.
  • a coil 340 and a capacitor 350 are connected to the switch terminal SW.
  • two LDMOSs 300 and 301 are driven by separate control circuits 330 and 331 on the low potential side and the high potential side to control the current to the coil 340, thereby realizing a step-down operation.
  • the LDMOS 301 on the high potential side is ON, the current I1 flows into the coil 340.
  • the power supply Vdd of the entire circuit is shut down, the path of the current I1 is cut off.
  • the coil 340 has a property of continuing a current flow, the current I2 flows out through the parasitic diode 310 of the LDMOS 300 on the low potential side and the current I3 flows out through the parasitic diode 320.
  • FIG. 8 is a diagram showing an example of the configuration of conventional LDMOSs 300 and 301 formed on the semiconductor substrate 210.
  • 8A is an example of a plan configuration diagram of the LDMOSs 300 and 301
  • FIG. 8B is an example of a cross-sectional configuration diagram of the LDMOSs 300 and 301.
  • FIG. 8A is an example of a plan configuration diagram of the LDMOSs 300 and 301
  • FIG. 8B is an example of a cross-sectional configuration diagram of the LDMOSs 300 and 301.
  • conventional LDMOSs 300 and 301 include a source region 220, drain regions 230 and 231, a gate 240, a back gate 250, a LOCOS (Local Oxidation of Silicon) 260 on a semiconductor substrate 210. And a substrate electrode 280.
  • the source region 220 and the drain region 230 extend in parallel, and a gate 240 extends between the source region 220 and the drain region 230 so as to be adjacent to the source region 220. Is provided.
  • a back gate region 250 is provided so as to surround the adjacent source regions 220 facing each other between the two gates 240. The other space is covered with the LOCOS 160 and the outer periphery is surrounded by the substrate electrode 280.
  • the LDMOSs 300 and 301 in FIG. 8 include four transistor cells.
  • the formation positions of contact holes 225, 235, 236, 255, and 285 for energizing are shown.
  • FIG. 8B shows a cross-sectional configuration of conventional LDMOSs 300 and 301, and an n layer 215 is formed on a p-type silicon substrate 210.
  • Drain regions 230 and 231 and a back gate region 250 are formed in the surface region of the n layer 215, and source regions 220 are formed on both ends of the surface of the back gate region 250.
  • LOCOS 260 is formed on both sides of the drain regions 230 and 231 and is isolated.
  • An oxide film 290 is formed on the surfaces of the source region 220, the drain region 230, and the back gate region 250, and a gate 240 is formed on the oxide film 290 adjacent to the source region 220 so as to straddle the LOCOS 260.
  • Substrate electrodes 280 are formed in the surface region of the semiconductor substrate 210 further outside the LOCOS 260 at both ends of the n layer 215.
  • the semiconductor substrate 210 is configured as a p-type semiconductor
  • the substrate electrode 280 and the back gate region 250 are configured as a p-type diffusion layer.
  • the n layer 215, the source region 220, and the drain regions 230 and 231 are configured as an n-type diffusion layer. Therefore, the parasitic diode 310 is formed between the back gate region 250 and the drain regions 230 and 231, and the parasitic diode 320 is formed between the semiconductor substrate 210 and the drain regions 230 and 231.
  • Such parasitic diodes 310 and 320 are necessarily formed due to the structure in the case of general n-channel LDMOSs 300 and 310.
  • the LDMOS 300, 301 having such a configuration is used as a power transistor for the step-down DC / DC converter shown in FIG. 7, as described in FIG. 7, the high potential side LDMOS 300 is turned on.
  • the power source Vdd is switched to OFF, a current in the same direction as the current I1 tends to continue to flow through the coil 340.
  • the currents I2 and I3 indicated by the broken lines flow toward the drain region 230 by the parasitic diodes 310 and 320.
  • source cells and drain cells are alternately arranged in the cell region in order to increase the surge withstand capability without lowering the withstand voltage, and the entire periphery of the cell region is terminated at the source cell.
  • LDMOS having a configuration in which a surge current is dispersed inside a cell region when a surge enters from a drain (see, for example, Patent Document 1).
  • the current caused by the parasitic diode 310 of the low potential LDMOS 300 A relatively small current flows through I2, but a considerably large current flows through the current I3 generated by the parasitic diode 320.
  • the current I3 flows into the drain region 230 from the side surface and the bottom surface of the semiconductor substrate 210, and the drain region 231 existing at both ends has the entire one surface of the drain region 231; Current I3 flows into both ends in the extending direction.
  • an object of the present invention is to provide a semiconductor device having a layout pattern that increases resistance to a reverse current.
  • a semiconductor device (100, 101, 102) is formed in a surface region of a semiconductor substrate (10) and extends oppositely, a source region (20) and a drain region. (30, 31, 32, 33) and the source region (20) between the source region (20) and the drain region (30, 31, 32, 33) formed on the surface of the semiconductor substrate (10).
  • a substrate electrode (80) surrounding the periphery of the plurality of transistor cells and defining a reference potential of the semiconductor substrate (10).
  • a current concentration relaxation electrode (70, 71, 72) having the same potential as the drain region (30, 31, 32, 33) is provided.
  • the backflow current that flows from the semiconductor substrate in a concentrated manner to the end of the drain region can be distributed and flowed to the current concentration relaxation electrode, and the wiring at the end of the drain region can be prevented from being damaged.
  • a second invention is a semiconductor device (100, 101, 102) according to the first invention.
  • the current concentration relaxation electrode (70, 71, 72) is longer than the width of the drain region (30, 31, 32, 33) in the width direction of the drain region (30, 31, 32, 33) or It is characterized by a long width.
  • the concentrated current in the drain region can be surely guarded by the current concentration relaxation electrode, and damage to the wiring at the end of the drain region can be surely prevented.
  • the current concentration relaxation electrodes (70, 71, 72) are electrically connected to the drain regions (30, 31, 32, 33) by wiring layers (150, 151).
  • the current concentration relaxation electrode can be reliably set to the same potential as the drain region by supplying power from the same power source.
  • the current concentration relaxation electrode (70, 71, 72) is provided on the surface region of the semiconductor substrate (10) continuously with the drain region (30, 31, 32, 33).
  • the drain region and the current concentration relaxation electrode can be set to the same potential also by the diffusion layer in the surface region of the semiconductor substrate.
  • a fifth invention is a semiconductor device (100) according to the fourth invention, wherein: The current concentration relaxation electrode (70) is provided on the surface region of the semiconductor substrate (10) continuously with all the drain regions (30, 31), and the drain region (30, 31) and the current concentration are provided. A relaxation electrode (70) surrounds the gate (40) and the source region (20) in a plane.
  • the backflow current concentration at the end of the drain region can be almost completely eliminated, and damage to the wiring portion at the end of the drain region can be reliably eliminated.
  • a sixth invention is the semiconductor device according to any one of the first to fifth inventions,
  • the drain region (30, 31, 32, 33) is composed of an n-type diffusion layer
  • the substrate electrode (80) is composed of a p-type diffusion layer
  • the current concentration relaxation electrodes (70, 71, 72) are formed of an n-type diffusion layer.
  • the concentration of the backflow current at the end of the drain region can be reduced, and damage to the wiring portion at the end of the drain region due to the backflow current can be prevented.
  • FIG. 1 is a diagram illustrating an example of a planar configuration of a semiconductor device 100 according to Example 1.
  • FIG. FIG. 2 is a diagram showing a cross-sectional configuration of the AA ′ cross section of FIG. 1.
  • 6 is a diagram transparently showing an example of a planar configuration of a wiring layer 150 of the semiconductor device according to Example 1.
  • FIG. FIG. 6 is a diagram illustrating an example of a planar configuration of a semiconductor device 101 according to a second embodiment.
  • 7 is a diagram transparently showing an example of a planar configuration of a wiring layer 151 of a semiconductor device 101 according to Example 2.
  • FIG. FIG. 6 is a diagram illustrating an example of a planar configuration of a semiconductor device 102 according to a third embodiment.
  • FIG. 1 is a diagram illustrating an example of a planar configuration of the semiconductor device 100 according to the first embodiment of the present invention.
  • a semiconductor device 100 according to the first embodiment includes a semiconductor substrate 10, a source region 20, drain regions 30 and 31, a gate 40, a back gate region 50, a LOCOS 60, and a current concentration relaxation electrode 70. And a substrate electrode 80.
  • positions where the contact holes 25, 35, 36, 55, 75, and 85 are provided in the source region 20, the drain regions 30 and 31, the back gate region 50, and the current concentration relaxation electrode 70 are shown, respectively.
  • the source region 20 and the drain regions 30 and 31 have an elongated rectangular shape and extend in parallel to face each other.
  • a gate 40 is disposed between the source region 20 and the drain regions 30 and 31.
  • the gate 40 is provided adjacent to the source region 20 and away from the drain region 30 so as to extend along the source region 20 in parallel with the source region 20 and the drain region 30.
  • the back gate region 50 is provided between the adjacent source regions 20 facing each other, and has a shape and a width including the source region 20 in the extending direction.
  • a LOCOS 60 is provided in a region between the gate 40 and the drain regions 30 and 31.
  • One drain region 30 at the center is opposed to the gate 40 via the LOCOS 60, and both sides are disposed between the gates 40.
  • the two drain regions 31 at both ends are opposed to the gate 40 through the LOCOS 60 on the center side, but are arranged to face the substrate electrode through the LOCOS 60 on the end side.
  • the current concentration relaxation electrode 70 is provided so as to extend in a direction perpendicular to the extending direction of the drain region 30. Since the drain region 30 is a portion facing the source region 20 having the same length as the source region 20, the current concentration relaxation electrode 70 is elongated and linearly connected so as to be continuously connected to the drain region 30. It has a close E shape. Therefore, the current concentration relaxation electrode 70 is connected to both ends in the extending direction of all the drain regions 30 and 31 (three in FIG. 1) in the semiconductor device 100 and is formed continuously with the drain regions 30 and 31. Has been.
  • the drain regions 30 and 31 and the current concentration relaxation electrode 70 surround the two gates 40 and the source region 20 and the one back gate region 50. Furthermore, the substrate electrode 80 surrounds the region surrounded by the drain region 31 at both ends in the longitudinal direction of the semiconductor device 100 and the current concentration relaxation electrode 70 via the LOCOS 60, thereby forming the semiconductor device 100. Yes.
  • the gate 40, the source region 20 and the drain regions 30 and 31 on both sides of the gate 40, and the back gate 50 constitute one transistor cell. Therefore, the semiconductor device 100 illustrated in FIG. 1 includes four transistor cells. That is, one drain region 31 at both ends corresponds to one transistor cell, but one central drain region 30 also serves as the drain region 30 of two transistor cells.
  • the semiconductor substrate 10 is a substrate on which the semiconductor device 100 according to the present embodiment is formed.
  • a substrate made of various semiconductor materials may be used.
  • a silicon substrate may be used.
  • the semiconductor substrate 10 is configured as a p-type semiconductor substrate when the semiconductor device 100 is configured as an n-channel LDMOS.
  • the source region 20 is a diffusion layer formed in the surface region of the semiconductor substrate 10 and functions as a source of the semiconductor device 100 configured as an LDMOS.
  • the surface region of the semiconductor substrate 10 means a region on the surface side including the surface of the semiconductor substrate 10, and an insulating film such as an oxide film is formed on the source region 20, or a metal, polysilicon, or the like is formed.
  • a conductive film may be formed.
  • An insulating layer is formed above the source region 20, and a wiring layer made of metal is formed above the insulating layer.
  • a plurality of contact holes 25 are formed in the insulating layer for electrical connection with the wiring layer. The position of the contact hole 25 is shown in FIG.
  • the source region 20 is configured by an n-type diffusion layer when the semiconductor device 100 is configured as an n-channel LDMOS.
  • the drain regions 30 and 31 are diffusion layers formed in the surface region of the semiconductor substrate 10 and function as drains of the semiconductor device 100 configured as an LDMOS.
  • the drain is formed on the back surface of the semiconductor substrate 10.
  • the semiconductor device 100 according to this embodiment is configured as a horizontal MOS transistor, the drain regions 30 and 31 are formed on the semiconductor substrate 100. Formed in the surface region.
  • the drain regions 30 and 31 are formed as a diffusion layer continuous with the current concentration relaxation electrode 70, but it is a portion facing the source region 20 that functions as the drain of the LDMOS. Therefore, even if it is formed continuously with the current concentration relaxation electrode 70, it is functionally distinguished from the current concentration relaxation electrode 70.
  • the drain region 30 is a drain region sandwiched between the gates 40 via the LOCOS 60 in plan view.
  • one drain region 30 existing in the center corresponds.
  • all the drain regions 30 except for the two drain regions 31 at both ends are sandwiched between the gates 40, and there are a plurality of drain regions 30. Will do.
  • an insulating layer is formed as an upper layer, and a metal wiring layer is formed as an upper layer of the insulating layer, and a plurality of contact holes 35 for electrical connection are formed in the insulating layer. In FIG. 1, the position of the contact hole 35 is shown.
  • the drain region 31 is a drain region 31 of a transistor cell that exists at both ends of the plurality of transistor cells arranged in the longitudinal direction of the semiconductor device 100, and one side in the extending direction faces the gate 40, and the other This side is the drain region 31 facing the substrate electrode 80. Therefore, when the transistor cells are arranged in one column, two drain regions 31 are provided for each column. Also in the drain region 31, a plurality of contact holes 36 are formed in the same manner as the contact holes 35, and electrical connection with the upper wiring layer is performed. Further, the drain region 30 and the drain region 31 are connected by the same wiring layer, and the drain regions 30 and 31 are configured to have the same potential.
  • the drain regions 30 and 31 are configured as n-type diffusion layers when the semiconductor device 100 is configured as an n-channel LDMOS.
  • the gate 40 is an electrode formed on the surface of the semiconductor substrate 10 and functions as an LDMOS gate.
  • the back gate region 50 is a diffusion layer formed in the surface region of the semiconductor substrate 10 and is configured as a body region for the source region 20. Therefore, the back gate region 50 is configured to cover the side surface and the bottom surface of the source region 20 from the side and below.
  • FIG. 2 is a diagram showing a cross-sectional configuration of the AA ′ cross section of FIG.
  • the back gate region 50 is configured to cover the side surface and bottom surface of the source region 20 from the side and from below. 2 also shows that the gate 40 described above is formed on the surface of the semiconductor substrate 10 so as to straddle the oxide film 90 and the LOCOS 60.
  • FIG. 2 is a diagram showing a cross-sectional configuration of the AA ′ cross section of FIG.
  • the back gate region 50 is configured to cover the side surface and bottom surface of the source region 20 from the side and from below. 2 also shows that the gate 40 described above is formed on the surface of the semiconductor substrate 10 so as to straddle the oxide film 90 and the LOCOS 60.
  • the back gate region 50 similarly to the source region 20, an insulating layer is formed on the upper layer, a wiring layer is further formed on the insulating layer, and a plurality of contact holes 55 are formed on the insulating layer. In FIG. 1, the position of the contact hole 55 is shown.
  • the back gate region 50 and the source region 20 are often supplied with the same potential. Therefore, the back gate region 50 and the source region 20 may be connected to the same wiring layer and supplied with the same potential.
  • the supplied potential may be, for example, 0 V of the ground potential.
  • the back gate region 50 is configured as a p-type diffusion layer when the semiconductor device 100 is configured as an n-channel LDMOS.
  • LOCOS 60 is an insulating film for insulating and isolating the drain region 30 in the lateral direction, and is provided so as to sandwich the drain region 30 from both sides. Further, the LOCOS 60 surrounds the drain region 30 from both ends in the extending direction, and is insulated and isolated from other diffusion layers.
  • the current concentration relaxation electrode 70 is a diffusion layer that guards both ends of the drain region 30 in the extending direction and relaxes the backflow current. Similar to the drain region 30, the current concentration relaxation electrode 70 is provided in the surface region of the semiconductor substrate 10. The current concentration relaxation electrode 70 extends in a direction perpendicular to the extending direction of the drain regions 30 and 31 in a plan configuration, is provided between the drain regions 30 and 31 and the substrate electrode 80, and It is formed by being continuously connected to both end portions of 30,31. Thus, the backflow current I3 flowing from the semiconductor substrate 10 toward the drain region 30 is sucked up by the current concentration relaxation electrode 70 before reaching the drain region 30, and the backflow current to the contact hole 35 at the end of the drain region 30 is absorbed. Concentration can be avoided. Further, in the configuration of FIG. 1, the current concentration relaxation electrode 70 also relaxes the backflow current to the end of the drain region 31.
  • a wiring layer is formed over the current concentration relaxation electrode 70 via an insulating layer, and a plurality of contact holes 75 are formed in the insulating layer. Since the plurality of contact holes 75 are densely formed along the extending direction of the current concentration relaxation electrode 70, the backflow current I 3 flowing into the end of the drain region 30 is caused to flow into each contact hole 75 of the current concentration relaxation electrode 70. The current can be passed through the wiring layer and the current can be dispersed by the plurality of contact holes 75.
  • the reverse current I3 is indicated by a broken-line arrow, but both end portions of the drain region 30 sandwiched by the center gate 40 are guarded by the current concentration relaxation electrode 70, and the concentration of the reverse current I3 is reduced. It has been avoided. Further, since the current concentration relaxation electrode 70 and the drain region 31 are formed so as to face the substrate electrode 80, the backflow current I3 does not concentrate on any part, but the current concentration is almost uniform throughout. It flows into the relaxation electrode 70 and the drain region 31. As described above, in the semiconductor device 100 according to the first embodiment, the current concentration relaxation electrode 70 is disposed on the extension line in the extending direction of the drain region 30 between the end portion in the extending direction of the drain region 30 and the substrate electrode 80. By forming a diffusion layer that is present in the region and continuous with the drain regions 30 and 31, the concentration of the backflow current I3 at the end of the central drain region 30 can be reliably mitigated.
  • the substrate electrode 80 is an electrode for determining the reference potential of the semiconductor substrate 10 and is supplied with the reference potential. Usually, the reference potential may be set to 0 V of the ground potential.
  • the substrate electrode 80 surrounds a plurality of transistor cells and constitutes one semiconductor device 100. Then, a reference potential is supplied to the semiconductor device 100.
  • An insulating layer is formed on the substrate electrode 80, and a metal wiring layer is further formed on the insulating layer.
  • a plurality of contact holes 85 are formed in the insulating layer, and the reference potential of the semiconductor substrate 10 is supplied to the substrate electrode 80 from the wiring layer through the contact holes 85.
  • FIG. 1 shows the position of the contact hole 85, and the contact hole 85 is formed over four sides of the substrate electrode 80.
  • the substrate electrode 80 is configured as a p-type diffusion layer when the semiconductor device 100 according to the present embodiment is configured as an n-channel LDMOS.
  • FIG. 2 is a diagram showing a configuration in the section AA ′ of FIG.
  • the same reference numerals are assigned to the components described in FIG.
  • FIG. 1 only the points not described in FIG. 1 will be described.
  • an n layer 15 is formed in a region inside the substrate electrode 80 of the semiconductor substrate 10, and a transistor cell is formed in a surface region of the n layer 15.
  • the n layer 15 is configured as a diffusion layer having a lower concentration than the source region 20, the drain region 30, and the current concentration relaxation electrode 70.
  • the n layer 15 may be a well layer, an epitaxial growth layer, or a diffusion layer formed by another manufacturing method.
  • the surface of the n layer 15 including the source region 20, the drain region 30, the back gate region 50, and the current concentration relaxation electrode 70, that is, the region not covered with the LOCOS 60 is covered with the oxide film 90.
  • the oxide film 90 at the position where the contact holes 25, 35, 36, 55, 75 are formed is removed, and the contact holes 25, 35, 36, It forms so that electrical connection with 55 and 75 and each diffusion region may be performed appropriately.
  • a parasitic diode 110 is formed between the back gate region 50 and the drain region 30, and a parasitic diode 120 is formed between the semiconductor substrate 10 and the drain region 30.
  • the influence of the current I2 flowing through the parasitic diode 110 is conventionally small.
  • the influence of the current I3 flowing through the parasitic diode 120 has hitherto been large in the central drain region 30 sandwiched between the gates 40 on both sides.
  • the current concentration relaxation electrode 70 is It has become smaller by providing it. As shown in FIG. 2, it can be seen that the current I3 flows only from the lower side of the semiconductor substrate 10.
  • the backflow current I3 can be prevented from being concentrated on the end of the drain region 30 sandwiched between the gates 40, and the semiconductor device 100 can be prevented from being damaged. Can do.
  • FIG. 3 is a diagram transparently showing an example of a planar configuration of the wiring layer 150 provided on the upper layer of the semiconductor substrate 10 of the semiconductor device 100 according to the first embodiment.
  • the wiring layer 150 includes a source wiring layer 110, a drain wiring layer 120, and a substrate electrode wiring layer 130.
  • a metal used as a wiring material such as aluminum or copper is used.
  • the source wiring layer 110 is a wiring for supplying power to the source region 20 and the back gate region 50.
  • the source wiring layer 110 is provided in a rectangular shape so as to cover the contact hole 25 in the source region 20 and the contact hole 55 in the back gate region 50 from above.
  • the drain wiring layer 120 is a wiring layer for supplying power to the drain regions 30 and 31 and the current concentration relaxation electrode 70.
  • the drain regions 30 and 31 and the power concentration relaxation electrode 70 are supplied with the potential from the same drain wiring layer 120 so that they all have the same potential.
  • the drain wiring layer 120 covers all of the contact hole 35 of the drain region 30, the contact hole 36 of the drain region, and the contact hole 70 of the current concentration relaxation electrode 70, and surrounds the source wiring layer 110 without contact. It is provided in the shape of figure 8.
  • the substrate electrode wiring layer 130 is a wiring layer for supplying a reference potential to the substrate electrode 80, and is provided in a frame shape so as to cover the contact hole 85 of the substrate electrode 80 from above.
  • the drain regions 30 and 31 and the current concentration relaxation electrode 70 are supplied with power from the same drain wiring layer 120 in the wiring layer 150 on the upper layer of the semiconductor substrate 10.
  • the drain regions 30 and 31 and the current concentration relaxation electrode 70 can be easily set to the same potential.
  • the pattern of the wiring layer 150 is formed so as to conform to the planar configuration of FIG. 1. However, if the planar configuration of FIG. 1 changes, the pattern of the wiring layer 150 may change accordingly. Needless to say.
  • the end portion of the drain region 30 sandwiched between the gates 40 on both sides in the extending direction is the current concentration relaxation electrode 70 formed continuously with the drain regions 30 and 31. Since it is completely guarded, it is possible to prevent the backflow current I3 from concentrating on the end of the drain region 30, and to prevent the semiconductor device 100 from being damaged by the induced current.
  • FIG. 4 is a diagram illustrating an example of a planar configuration of the semiconductor device 101 according to the second embodiment of the present invention.
  • the same components as those of the semiconductor device 100 according to the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.
  • the semiconductor device 101 according to the second embodiment includes a semiconductor substrate 10, a source region 20, a gate 40, a back gate region 50, a LOCOS 60, a substrate electrode 80, and contact holes 25, 55, and 85.
  • a semiconductor substrate 10 a semiconductor substrate 10
  • a source region 20 a gate 40
  • a back gate region 50 a LOCOS 60
  • a substrate electrode 80 a substrate electrode 80
  • contact holes 25, 55, and 85 are the same constituent elements as those of the semiconductor device 100 according to the first embodiment, and the arrangement thereof is also the same.
  • the semiconductor device 101 according to the second embodiment is related to the first embodiment in that the drain regions 32 and 33 and the current concentration relaxation electrode 71 are separately formed independently and are not formed continuously. Different from the semiconductor device 100. However, the current concentration relaxation electrode 71 extends in a direction perpendicular to the extending direction of the source region 20 and the drain region 32, and exists between the end portion of the extending direction of the drain region 30 and the substrate electrode 80. In common, the semiconductor device 100 according to the first embodiment is common.
  • the drain regions 32 and 33 and the current concentration relaxation electrode 71 are not necessarily formed continuously in the surface region of the semiconductor substrate 10. Even in this case, the current concentration relaxation electrode 71 guards the backflow current I3 that flows from the semiconductor substrate 10 to both ends of the drain region 32, and the backflow current I3 flows to the drain region 32 via the plurality of contact holes 76. Since the backflow current is sucked up before reaching, concentration of current in the contact holes 37 at both ends of the drain region 32 can be avoided.
  • the current concentration relaxation electrode 71 has an elongated rectangular shape, and extends so as to guard the drain regions 32 and 33 in the longitudinal direction of the semiconductor device 100.
  • a plurality of contact holes 76 are densely formed on the current concentration relaxation electrode 71 along the extending direction of the current concentration relaxation electrode 71, and the backflow current I3 is distributed to flow through the wiring layer. It is configured to be possible.
  • FIG. 5 is a diagram transparently showing an example of a planar configuration of the wiring layer 151 formed in the upper layer of the semiconductor substrate 10 of the semiconductor device 101 according to the second embodiment.
  • the wiring layer 151 includes a source wiring layer 111, a drain wiring layer 121, and a substrate electrode wiring layer 131.
  • the source wiring layer 111 is a wiring layer that supplies power to the source region 20 and the back gate region 50
  • the drain wiring layer 121 is a wiring layer that supplies power to the drain regions 32 and 33 and the current concentration relaxation electrode 71.
  • the point is the same as in the first embodiment.
  • the substrate electrode wiring layer 131 is the same as the first embodiment in that the substrate electrode wiring layer 131 is a wiring layer that applies a reference potential to the substrate electrode 81.
  • the drain wiring layer 121 covers all of the contact hole 37 formed on the drain region 32, the contact hole 38 formed on the drain region 33, and the contact hole 76 formed on the current concentration relaxation electrode 71. It is formed as follows. That is, the drain regions 32 and 33 and the current concentration relaxation electrode 71 are electrically connected via the drain wiring layer 121 and have the same potential. Thus, even if the drain regions 32 and 33 and the current concentration relaxation electrode 71 are not connected in the surface region of the semiconductor substrate 10, the drain regions 32 and 33 and the current concentration are separated by the upper drain wiring layer 121.
  • the relaxing electrode 71 can be set to the same potential.
  • the configurations of the drain regions 32 and 33 and the current concentration relaxation electrode 71 in the surface region of the semiconductor substrate 10 are slightly different from those in the first embodiment, but the overall arrangement is substantially the same.
  • the arrangement of the contact holes 37, 38, and 76 is substantially the same as that of the semiconductor device 100 according to the first embodiment. Therefore, the shape of the drain wiring layer 121 is substantially the same as that of the drain wiring layer 120 according to the first embodiment.
  • the drain regions 32 and 33 and the current concentration relaxation electrode 71 may be formed in a continuous manner or in an independent manner.
  • the wiring layers 120 and 121 can be used.
  • the source wiring layer 111 and the substrate electrode are arranged.
  • the configuration of the wiring layer 131 is the same as that of the source wiring layer 110 and the substrate electrode wiring layer 130 of the first embodiment.
  • the wiring layer 151 of the semiconductor device 101 according to the second embodiment can use the same wiring pattern as the wiring layer 150 of the semiconductor device 100 according to the first embodiment.
  • the drain regions 32 and 33 and the current concentration relaxation region 71 are separately provided on the surface region of the semiconductor substrate 10, but the drain regions 32 and 33 and the current concentration relaxation are provided.
  • the electrode 71 can be electrically connected to the wiring layer 151 to have the same potential.
  • FIG. 6 is a diagram illustrating an example of a planar configuration of the semiconductor device 102 according to the third embodiment of the present invention.
  • the same components as those of the semiconductor device 101 according to the second embodiment are denoted by the same reference numerals, and the description thereof is omitted.
  • the semiconductor device 102 includes a semiconductor substrate 10, a source region 20, drain regions 32 and 33, a gate 40, a back gate region 50, a LOCOS 60, a substrate electrode 80, Since the contact holes 25, 37, 38, 55, and 85 are the same as those of the semiconductor device 101 according to the second embodiment, the same reference numerals as those in the second embodiment are given to the contact holes 25, 37, 38, 55, and 85, and the description thereof is omitted.
  • the current concentration relaxation electrodes 72 do not extend to the drain regions 33 at both ends in the longitudinal direction of the semiconductor device 102 and have a length that guards only the central drain region 72. This is different from the semiconductor device 101 according to the second embodiment.
  • the current concentration relaxation electrode 72 is provided between the end portion and the substrate electrode 80 outside the end portion in the extending direction of the drain region 72.
  • the semiconductor devices 100 and 101 according to the first and second embodiments are common.
  • the current concentration relaxation electrode 72 may have a length that guards only both ends of the drain region 32.
  • the current concentration relaxation electrode 72 has a plurality of contact holes 77 between the drain region 32 and the substrate electrode 80, the current concentration relaxation electrode 72 has an effect of reducing the concentration of the backflow current I3.
  • the length is short, the backflow current I3 flowing from the side cannot be guarded, so that the length or width is preferably larger than the width of the drain region 32. More preferably, if the length or width of the current concentration relaxation electrode 72 is larger than the distance between the two gates 40 sandwiching the drain region 32, the concentration of the backflow current I3 can be sufficiently prevented.
  • the current concentration relaxation electrode 72 since the length or width of the current concentration relaxation electrode 72 is small, the current concentration relaxation electrode 72 may be disposed so as to be surely present on the extension line in the extending direction of the drain region 32. preferable.
  • the contact holes 77 are densely formed on the current concentration relaxation electrode 72 as in the semiconductor devices 100 and 101 according to the first and second embodiments.
  • the wiring layer having the same pattern as the wiring layer 151 according to the second embodiment can be used as the upper wiring layer of the semiconductor substrate 10 of the semiconductor device 102 according to the third embodiment.
  • the pattern of the wiring layer is not limited to the pattern of the wiring layer 151 of the second embodiment, and the contact holes 37 and 38 of the drain regions 32 and 33 and the contact hole 77 of the current concentration relaxation electrode 72 are formed in the same drain. If it can be connected in the wiring layer, it can be configured with various wiring patterns.
  • the present invention can be used for a semiconductor device including an LDMOS.

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Abstract

Disclosed is a semiconductor device that is provided with: a plurality of transistor cells, each of which includes a source region and a drain region that are formed to face each other and extend on the surface region of a semiconductor substrate, and a gate that is formed on the surface of the semiconductor substrate so as to extend along the source region between the source region and the drain region; and a substrate electrode, which surrounds the circumferences of the transistor cells, and which specifies the reference potential of the semiconductor substrate. A current crowding relaxing electrode having a potential equal to that of the drain region is provided on the extended line of the drain region between the substrate electrode and the end portions of the drain region having the gates on both the sides on the surface region of the semiconductor substrate.

Description

半導体装置Semiconductor device
　　本発明は、半導体装置に関し、特に、半導体基板の表面領域に形成され、対向して延在するソース領域及びドレイン領域を有する半導体装置に関する。 The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a source region and a drain region which are formed in a surface region of a semiconductor substrate and extend opposite to each other.
　　従来から、ＬＤＭＯＳ（Laterally Diffused Metal Oxide Semiconductor、横型ＭＯＳトランジスタ）を用いた降圧ＤＣ／ＤＣコンバータが知られている。 Conventionally, a step-down DC / DC converter using LDMOS (Laterally Diffused Metal Metal Oxide Semiconductor, lateral MOS transistor) is known.
　　図７は、従来のＬＤＭＯＳを用いた降圧ＤＣ／ＤＣコンバータの回路図の一例を示した図である。図７において、降圧ＤＣ／ＤＣコンバータは、低電位側のＬＤＭＯＳ３００と、高電位側のＬＤＭＯＳ３０１と、低電位側ＬＤＭＯＳ３００を制御する制御部３３０と、高電位側ＬＤＭＯＳ３０１を制御する制御部３３１とを備える。低電位側ＬＤＭＯＳ３００及び高電位側ＬＤＭＯＳ３０１の双方ともｎチャネル型ＬＤＭＯＳであり、低電位側ＬＤＭＯＳ３００のドレインと、高電位側ＬＤＭＯＳ３０１のソースとが接続され、スイッチ端子ＳＷを構成する。また、低電位側ＬＤＭＯＳ３００及び高電位側ＬＤＭＯＳ３０１は各々、ドレイン－バックゲート間の寄生ダイオード３１０、３１１と、ドレイン－半導体基板間の寄生ダイオード３２０、３２１とを有した構成となる。また、外付けの部品として、コイル３４０と、コンデンサ３５０とがスイッチ端子ＳＷに接続されている。 FIG. 7 is a diagram showing an example of a circuit diagram of a step-down DC / DC converter using a conventional LDMOS. 7, the step-down DC / DC converter includes a low-potential side LDMOS 300, a high-potential side LDMOS 301, a control unit 330 that controls the low-potential side LDMOS 300, and a control unit 331 that controls the high-potential side LDMOS 301. . Both the low potential side LDMOS 300 and the high potential side LDMOS 301 are n-channel LDMOSs, and the drain of the low potential side LDMOS 300 and the source of the high potential side LDMOS 301 are connected to form a switch terminal SW. The low-potential side LDMOS 300 and the high-potential side LDMOS 301 each have a drain-back gate parasitic diode 310, 311 and a drain-semiconductor substrate parasitic diode 320, 321. In addition, as an external component, a coil 340 and a capacitor 350 are connected to the switch terminal SW.
　　かかる降圧ＤＣ／ＤＣコンバータにおいて、低電位側と高電位側の別々の制御回路３３０、３３１により、２個のＬＤＭＯＳ３００、３０１を駆動し、コイル３４０への電流を制御することにより、降圧動作を実現する。まず、高電位側のＬＤＭＯＳ３０１がＯＮしているときには、コイル３４０に電流Ｉ１が流れ込んでいる。このタイミングで、回路全体の電源Ｖｄｄがシャットダウンされると、電流Ｉ１の経路が遮断される。ここで、コイル３４０には、電流を流し続ける性質があるため、低電位側のＬＤＭＯＳ３００の寄生ダイオード３１０を介して電流Ｉ２、寄生ダイオード３２０を介して電流Ｉ３が流れ出る。 In such a step-down DC / DC converter, two LDMOSs 300 and 301 are driven by separate control circuits 330 and 331 on the low potential side and the high potential side to control the current to the coil 340, thereby realizing a step-down operation. To do. First, when the LDMOS 301 on the high potential side is ON, the current I1 flows into the coil 340. At this timing, when the power supply Vdd of the entire circuit is shut down, the path of the current I1 is cut off. Here, since the coil 340 has a property of continuing a current flow, the current I2 flows out through the parasitic diode 310 of the LDMOS 300 on the low potential side and the current I3 flows out through the parasitic diode 320.
　　図８は、半導体基板２１０に形成された従来のＬＤＭＯＳ３００、３０１の構成の一例を示した図である。図８（Ａ）はＬＤＭＯＳ３００、３０１の平面構成図の一例であり、図８（Ｂ）は、ＬＤＭＯＳ３００、３０１の断面構成図の一例である。 FIG. 8 is a diagram showing an example of the configuration of conventional LDMOSs 300 and 301 formed on the semiconductor substrate 210. 8A is an example of a plan configuration diagram of the LDMOSs 300 and 301, and FIG. 8B is an example of a cross-sectional configuration diagram of the LDMOSs 300 and 301. FIG.
　　図８（Ａ）において、従来のＬＤＭＯＳ３００、３０１は、半導体基板２１０上に、ソース領域２２０と、ドレイン領域２３０、２３１と、ゲート２４０と、バックゲート２５０と、ＬＯＣＯＳ（Local Oxidation of Silicon）２６０と、基板電極２８０とを備えている。従来のＬＤＭＯＳ３００、３０１においては、ソース領域２２０とドレイン領域２３０とが平行に延在し、ソース領域２２０とドレイン領域２３０の間には、ソース領域２２０に隣接するようにゲート２４０が延在して設けられている。また、２つのゲート２４０間で対向して隣り合うソース領域２２０を囲むように、バックゲート領域２５０が設けられている。それ以外の空間は、ＬＯＣＯＳ１６０に覆われており、外周は基板電極２８０で囲まれている。上述のゲート２４０、ソース領域２２０及びドレイン領域２３０の１組、又はゲート２４０、ソース領域２２０及びドレイン領域２３１の１組で１つのトランジスタセルを構成している。よって、図８のＬＤＭＯＳ３００、３０１には、４個のトランジスタセルが含まれている。また、ソース領域２２０、ドレイン領域２３０、２３１、バックゲート領域２５０及び基板電極２８０には、各々通電を行うためのコンタクトホール２２５、２３５、２３６、２５５、２８５の形成位置が示されている。 8A, conventional LDMOSs 300 and 301 include a source region 220, drain regions 230 and 231, a gate 240, a back gate 250, a LOCOS (Local Oxidation of Silicon) 260 on a semiconductor substrate 210. And a substrate electrode 280. In conventional LDMOS 300 and 301, the source region 220 and the drain region 230 extend in parallel, and a gate 240 extends between the source region 220 and the drain region 230 so as to be adjacent to the source region 220. Is provided. Further, a back gate region 250 is provided so as to surround the adjacent source regions 220 facing each other between the two gates 240. The other space is covered with the LOCOS 160 and the outer periphery is surrounded by the substrate electrode 280. One set of the above-described gate 240, source region 220 and drain region 230, or one set of the gate 240, source region 220 and drain region 231 constitutes one transistor cell. Therefore, the LDMOSs 300 and 301 in FIG. 8 include four transistor cells. In addition, in the source region 220, the drain regions 230 and 231, the back gate region 250, and the substrate electrode 280, the formation positions of contact holes 225, 235, 236, 255, and 285 for energizing are shown.
　　図８（Ｂ）において、従来のＬＤＭＯＳ３００、３０１の断面構成が示されているが、ｐ型のシリコン基板２１０に、ｎ層２１５が形成されている。ｎ層２１５の表面領域に、ドレイン領域２３０、２３１とバックゲート領域２５０が形成され、更にバックゲート領域２５０の表面の両端側に、ソース領域２２０が形成されている。ドレイン領域２３０、２３１の両側には、ＬＯＣＯＳ２６０が形成され、絶縁分離されている。また、ソース領域２２０、ドレイン領域２３０及びバックゲート領域２５０の表面には、酸化膜２９０が形成されており、ソース領域２２０と隣接する酸化膜２９０上に、ＬＯＣＯＳ２６０を跨ぐようにゲート２４０が形成されている。そして、ｎ層２１５の両端部にあるＬＯＣＯＳ２６０よりも更に外側の半導体基板２１０の表面領域に、基板電極２８０が形成されている。 FIG. 8B shows a cross-sectional configuration of conventional LDMOSs 300 and 301, and an n layer 215 is formed on a p-type silicon substrate 210. Drain regions 230 and 231 and a back gate region 250 are formed in the surface region of the n layer 215, and source regions 220 are formed on both ends of the surface of the back gate region 250. LOCOS 260 is formed on both sides of the drain regions 230 and 231 and is isolated. An oxide film 290 is formed on the surfaces of the source region 220, the drain region 230, and the back gate region 250, and a gate 240 is formed on the oxide film 290 adjacent to the source region 220 so as to straddle the LOCOS 260. ing. Substrate electrodes 280 are formed in the surface region of the semiconductor substrate 210 further outside the LOCOS 260 at both ends of the n layer 215.
　　ここで、半導体基板２１０はｐ型半導体として構成され、基板電極２８０、バックゲート領域２５０はｐ型拡散層として構成されている。また、ｎ層２１５、ソース領域２２０及びドレイン領域２３０、２３１は、ｎ型拡散層として構成されている。よって、バックゲート領域２５０とドレイン領域２３０、２３１との間に寄生ダイオード３１０、半導体基板２１０とドレイン領域２３０、２３１との間に、寄生ダイオード３２０が形成された構成となっている。かかる寄生ダイオード３１０、３２０は、一般的なｎチャネル型ＬＤＭＯＳ３００、３１０の場合には、構造上、必ず形成されるものである。例えば、このような構成のＬＤＭＯＳ３００、３０１を、図７で示した降圧ＤＣ／ＤＣコンバータ用のパワートランジスタとして使用した場合には、図７において説明したように、高電位側ＬＤＭＯＳ３００がＯＮの状態から、電源ＶｄｄをＯＦＦに切り替えたときに、電流Ｉ１と同じ向きの電流がコイル３４０に流れ続けようとする。そうすると、低電位側ＬＤＭＯＳ３００において、寄生ダイオード３１０、３２０により、破線で示した電流Ｉ２、Ｉ３がドレイン領域２３０に向かって流れることになる。 Here, the semiconductor substrate 210 is configured as a p-type semiconductor, and the substrate electrode 280 and the back gate region 250 are configured as a p-type diffusion layer. The n layer 215, the source region 220, and the drain regions 230 and 231 are configured as an n-type diffusion layer. Therefore, the parasitic diode 310 is formed between the back gate region 250 and the drain regions 230 and 231, and the parasitic diode 320 is formed between the semiconductor substrate 210 and the drain regions 230 and 231. Such parasitic diodes 310 and 320 are necessarily formed due to the structure in the case of general n- channel LDMOSs 300 and 310. For example, when the LDMOS 300, 301 having such a configuration is used as a power transistor for the step-down DC / DC converter shown in FIG. 7, as described in FIG. 7, the high potential side LDMOS 300 is turned on. When the power source Vdd is switched to OFF, a current in the same direction as the current I1 tends to continue to flow through the coil 340. Then, in the low potential side LDMOS 300, the currents I2 and I3 indicated by the broken lines flow toward the drain region 230 by the parasitic diodes 310 and 320.
　　なお、ＬＤＭＯＳに関連する発明として、耐圧を低下させることなく、サージ耐量を大きくするため、セル領域にはソースセルとドレインセルを交互に配置し、セル領域の外周をソースセルにて全て終端させるようにし、ドレインからサージが入った場合に、サージ電流をセル領域の内部で分散させるようにした構成のＬＤＭＯＳが知られている（例えば、特許文献１参照）。 As an invention related to LDMOS, source cells and drain cells are alternately arranged in the cell region in order to increase the surge withstand capability without lowering the withstand voltage, and the entire periphery of the cell region is terminated at the source cell. Thus, there is known an LDMOS having a configuration in which a surge current is dispersed inside a cell region when a surge enters from a drain (see, for example, Patent Document 1).
特開平１０－３１３０６４号公報Japanese Patent Laid-Open No. 10-313064
　　ところで、上述の図８において説明した従来のＬＤＭＯＳ３００、３０１を、図７の降圧ＤＣ／ＤＣコンバータに用い、高電位側ＬＤＭＯＳ３０１をＯＮからＯＦＦに切り替えた場合、低電位側ＬＤＭＯＳ３００の寄生ダイオード３１０による電流Ｉ２は、比較的小さな電流が流れるが、寄生ダイオード３２０による電流Ｉ３は、相当に大きな電流が流れる。このとき、図８（Ａ）に示すように、ドレイン領域２３０には、半導体基板２１０の側面及び底面から電流Ｉ３が流れ込み、両端に存在するドレイン領域２３１には、ドレイン領域２３１の片面全体と、延在方向の両端部の双方に電流Ｉ３が流れ込む。ドレイン領域２３１においては、ドレイン領域２３１の全体に形成されているコンタクトホール２３６が総て用いられるので、電流Ｉ３は配線層に逃げ込む。ところが、中央部の、両側がゲート２４０により挟まれているドレイン領域２３０には、両端部に電流Ｉ３が集中して流れ込む。このとき、両端部に形成されているコンタクトホール２３５に電流Ｉ３が集中してしまい、コンタクトホール２３５又はこれに接続されている配線層（図示せず）が焼けてしまうおそれがあるという問題があった。この場合、図７においては、接点Ｄ１の箇所で、配線が焼け、ＬＤＭＯＳ３００が破壊に至ってしまうという問題があった。 When the conventional LDMOS 300 and 301 described in FIG. 8 is used in the step-down DC / DC converter of FIG. 7 and the high potential LDMOS 301 is switched from ON to OFF, the current caused by the parasitic diode 310 of the low potential LDMOS 300 A relatively small current flows through I2, but a considerably large current flows through the current I3 generated by the parasitic diode 320. At this time, as shown in FIG. 8A, the current I3 flows into the drain region 230 from the side surface and the bottom surface of the semiconductor substrate 210, and the drain region 231 existing at both ends has the entire one surface of the drain region 231; Current I3 flows into both ends in the extending direction. In the drain region 231, all the contact holes 236 formed in the entire drain region 231 are used, so that the current I3 escapes to the wiring layer. However, the current I3 flows in a concentrated manner at both ends of the drain region 230, which is sandwiched between the gates 240 on both sides. At this time, there is a problem that the current I3 concentrates on the contact holes 235 formed at both ends, and the contact hole 235 or a wiring layer (not shown) connected thereto may be burned. It was. In this case, in FIG. 7, there is a problem that the wiring is burnt at the point of the contact D <b> 1 and the LDMOS 300 is destroyed.
　　そこで、本発明は、逆流電流への耐性を高めるレイアウトパターンを有する半導体装置を提供することを目的とする。 Therefore, an object of the present invention is to provide a semiconductor device having a layout pattern that increases resistance to a reverse current.
　　上記目的を達成するため、第１の発明に係る半導体装置（１００、１０１、１０２）は、半導体基板（１０）の表面領域に形成され、対向して延在するソース領域（２０）及びドレイン領域（３０、３１、３２、３３）と、前記半導体基板（１０）の表面上に形成され、前記ソース領域（２０）及びドレイン領域（３０、３１、３２、３３）の間で前記ソース領域（２０）に沿って延在するゲート（４０）とを含む複数のトランジスタセルと、前記複数のトランジスタセルの周囲を囲み、前記半導体基板（１０）の基準電位を定める基板電極（８０）とを備えた半導体装置（１００、１０１、１０２）において、
　前記半導体基板（１０）の表面領域の、前記ゲート（４０）に両側を挟まれた前記ドレイン領域の延在方向における端部と、前記基板電極との間の前記ドレイン領域の延長線上に、前記ドレイン領域（３０、３１、３２、３３）と同電位の電流集中緩和電極（７０、７１、７２）が設けられたことを特徴とする。 In order to achieve the above object, a semiconductor device (100, 101, 102) according to a first invention is formed in a surface region of a semiconductor substrate (10) and extends oppositely, a source region (20) and a drain region. (30, 31, 32, 33) and the source region (20) between the source region (20) and the drain region (30, 31, 32, 33) formed on the surface of the semiconductor substrate (10). ) And a substrate electrode (80) surrounding the periphery of the plurality of transistor cells and defining a reference potential of the semiconductor substrate (10). In the semiconductor device (100, 101, 102),
On the extended line of the drain region between the substrate electrode and the end of the surface region of the semiconductor substrate (10) in the extending direction of the drain region sandwiched on both sides by the gate (40), A current concentration relaxation electrode (70, 71, 72) having the same potential as the drain region (30, 31, 32, 33) is provided.
　　これにより、半導体基板から、ドレイン領域の端部に集中して流れ込む逆流電流を、電流集中緩和電極に分散させて流れ込ませることができ、ドレイン領域の端部の配線の破損を防ぐことができる。 Thereby, the backflow current that flows from the semiconductor substrate in a concentrated manner to the end of the drain region can be distributed and flowed to the current concentration relaxation electrode, and the wiring at the end of the drain region can be prevented from being damaged.
　　第２の発明は、第１の発明に係る半導体装置（１００、１０１、１０２）において、
　前記電流集中緩和電極（７０、７１、７２）は、前記ドレイン領域（３０、３１、３２、３３）の幅方向において、前記ドレイン領域（３０、３１、３２、３３）の幅よりも長さ又は幅が長いことを特徴とする。 A second invention is a semiconductor device (100, 101, 102) according to the first invention.
The current concentration relaxation electrode (70, 71, 72) is longer than the width of the drain region (30, 31, 32, 33) in the width direction of the drain region (30, 31, 32, 33) or It is characterized by a long width.
　　これにより、ドレイン領域への集中電流を、確実に電流集中緩和電極でガードすることができ、ドレイン領域の端部の配線の破損を確実に防止することができる。 Thereby, the concentrated current in the drain region can be surely guarded by the current concentration relaxation electrode, and damage to the wiring at the end of the drain region can be surely prevented.
　　第３の発明は、第１又は第２の発明に係る半導体装置（１００、１０１、１０２）において、
　前記電流集中緩和電極（７０、７１、７２）は、配線層（１５０、１５１）により前記ドレイン領域（３０、３１、３２、３３）と電気的に接続されていることを特徴とする。 According to a third invention, in the semiconductor device (100, 101, 102) according to the first or second invention,
The current concentration relaxation electrodes (70, 71, 72) are electrically connected to the drain regions (30, 31, 32, 33) by wiring layers (150, 151).
　　これにより、電流集中緩和電極を、同一電源からの電力の供給により、確実にドレイン領域と同電位とすることができる。 Thus, the current concentration relaxation electrode can be reliably set to the same potential as the drain region by supplying power from the same power source.
　　第４の発明は、第３の発明に係る半導体装置（１００、１０１、１０２）において、
　前記電流集中緩和電極（７０、７１、７２）は、前記ドレイン領域（３０、３１、３２、３３）と連続的に前記半導体基板（１０）の表面領域に設けられたことを特徴とする。 According to a fourth invention, in the semiconductor device (100, 101, 102) according to the third invention,
The current concentration relaxation electrode (70, 71, 72) is provided on the surface region of the semiconductor substrate (10) continuously with the drain region (30, 31, 32, 33).
　　これにより、半導体基板の表面領域の拡散層によっても、ドレイン領域と電流集中緩和電極を同電位にすることができる。 Thereby, the drain region and the current concentration relaxation electrode can be set to the same potential also by the diffusion layer in the surface region of the semiconductor substrate.
　　第５の発明は、第４の発明に係る半導体装置（１００）において、
　前記電流集中緩和電極（７０）は、総ての前記ドレイン領域（３０、３１）と連続的に前記半導体基板（１０）の表面領域に設けられ、前記ドレイン領域（３０、３１）と前記電流集中緩和電極（７０）とで、前記ゲート（４０）及び前記ソース領域（２０）を平面的に囲むことを特徴とする。 A fifth invention is a semiconductor device (100) according to the fourth invention, wherein:
The current concentration relaxation electrode (70) is provided on the surface region of the semiconductor substrate (10) continuously with all the drain regions (30, 31), and the drain region (30, 31) and the current concentration are provided. A relaxation electrode (70) surrounds the gate (40) and the source region (20) in a plane.
　　これにより、ドレイン領域の端部への逆流電流の集中をほぼ完全に無くすことができ、確実にドレイン領域の端部の配線部の破損を無くすことができる。 As a result, the backflow current concentration at the end of the drain region can be almost completely eliminated, and damage to the wiring portion at the end of the drain region can be reliably eliminated.
　　第６の発明は、第１～５のいずれかの発明に係る半導体装置において、
　前記ドレイン領域（３０、３１、３２、３３）は、ｎ型拡散層から構成され、
　前記基板電極（８０）は、ｐ型拡散層から構成され、
　前記電流集中緩和電極（７０、７１、７２）は、ｎ型拡散層から構成されていることを特徴とする。 A sixth invention is the semiconductor device according to any one of the first to fifth inventions,
The drain region (30, 31, 32, 33) is composed of an n-type diffusion layer,
The substrate electrode (80) is composed of a p-type diffusion layer,
The current concentration relaxation electrodes (70, 71, 72) are formed of an n-type diffusion layer.
　　これにより、使用頻度の高いｎチャネル型の半導体装置において、ドレイン領域の端部の破損を防止することができる。 This can prevent the end of the drain region from being damaged in an n-channel semiconductor device that is frequently used.
　　なお、括弧内の参照符号は、理解を容易にするために付したものであり、一例に過ぎず、図示の態様に限定されるものではない。 The reference numerals in parentheses are given for ease of understanding, and are merely examples, and are not limited to the illustrated modes.
　　本発明によれば、ドレイン領域の端部への逆流電流の集中を低減し、逆流電流によるドレイン領域端部の配線部の破損を防止することができる。 According to the present invention, the concentration of the backflow current at the end of the drain region can be reduced, and damage to the wiring portion at the end of the drain region due to the backflow current can be prevented.
実施例１に係る半導体装置１００の平面構成の一例を示した図である。1 is a diagram illustrating an example of a planar configuration of a semiconductor device 100 according to Example 1. FIG. 図１のＡ－Ａ'断面の断面構成を示した図である。FIG. 2 is a diagram showing a cross-sectional configuration of the AA ′ cross section of FIG. 1. 実施例１に係る半導体装置の配線層１５０の平面構成の一例を透過的に示した図である。6 is a diagram transparently showing an example of a planar configuration of a wiring layer 150 of the semiconductor device according to Example 1. FIG. 実施例２に係る半導体装置１０１の平面構成の一例を示した図である。FIG. 6 is a diagram illustrating an example of a planar configuration of a semiconductor device 101 according to a second embodiment. 実施例２に係る半導体装置１０１の配線層１５１の平面構成の一例を透過的に示した図である。7 is a diagram transparently showing an example of a planar configuration of a wiring layer 151 of a semiconductor device 101 according to Example 2. FIG. 実施例３に係る半導体装置１０２の平面構成の一例を示した図である。FIG. 6 is a diagram illustrating an example of a planar configuration of a semiconductor device 102 according to a third embodiment. 従来のＬＤＭＯＳを用いた降圧ＤＣ／ＤＣコンバータの回路図を示した図である。It is the figure which showed the circuit diagram of the step-down DC / DC converter using the conventional LDMOS. 従来のＬＤＭＯＳ３００、３０１の半導体基板２１０上の構成の一例を示した図であり、ＬＤＭＯＳ３００、３０１の平面構成図の一例である。It is a figure showing an example of composition on semiconductor substrate 210 of conventional LDMOS 300 and 301, and is an example of a plane composition diagram of LDMOS 300 and 301. 従来のＬＤＭＯＳ３００、３０１の半導体基板２１０上の構成の一例を示した図であり、ＬＤＭＯＳ３００、３０１の断面構成図の一例である。It is a figure showing an example of composition on semiconductor substrate 210 of conventional LDMOS 300 and 301, and is an example of a cross-sectional composition diagram of LDMOS 300 and 301.
　　以下、図面を参照して、本発明を実施するための形態の説明を行う。 Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings.
　　図１は、本発明の実施例１に係る半導体装置１００の平面構成の一例を示した図である。図１において、実施例１に係る半導体装置１００は、半導体基板１０と、ソース領域２０と、ドレイン領域３０、３１と、ゲート４０と、バックゲート領域５０と、ＬＯＣＯＳ６０と、電流集中緩和電極７０と、基板電極８０とを備える。また、ソース領域２０、ドレイン領域３０、３１、バックゲート領域５０及び電流集中緩和電極７０には、各々コンタクトホール２５、３５、３６、５５、７５、８５が設けられる位置が示されている。 FIG. 1 is a diagram illustrating an example of a planar configuration of the semiconductor device 100 according to the first embodiment of the present invention. 1, a semiconductor device 100 according to the first embodiment includes a semiconductor substrate 10, a source region 20, drain regions 30 and 31, a gate 40, a back gate region 50, a LOCOS 60, and a current concentration relaxation electrode 70. And a substrate electrode 80. In addition, positions where the contact holes 25, 35, 36, 55, 75, and 85 are provided in the source region 20, the drain regions 30 and 31, the back gate region 50, and the current concentration relaxation electrode 70 are shown, respectively.
　　ソース領域２０とドレイン領域３０、３１は、細長い長方形の形状をしており、互いに対向して平行に延在している。また、ソース領域２０とドレイン領域３０、３１との間には、ゲート４０が配置されている。ゲート４０は、ソース領域２０と隣接し、ドレイン領域３０とは離れた位置に、ソース領域２０及びドレイン領域３０と平行に、ソース領域２０に沿って延在して設けられている。バックゲート領域５０は、対向して隣り合うソース領域２０の間に設けられ、延在方向においては、ソース領域２０を包含する形状及び広さを有している。ゲート４０と、ドレイン領域３０、３１との間の領域には、ＬＯＣＯＳ６０が設けられている。中央の１本のドレイン領域３０は、ＬＯＣＯＳ６０を介してゲート４０と対向し、両側がゲート４０に挟まれて配置されている。一方、両端の２本のドレイン領域３１は、中央側がＬＯＣＯＳ６０を介してゲート４０と対向しているが、端部側が、ＬＯＣＯＳ６０を介して基板電極に対向して配置されている。電流集中緩和電極７０は、ドレイン領域３０の延在方向と垂直な方向に延在して設けられている。ドレイン領域３０は、ソース領域２０と同じ長さの、ソース領域２０と対向している部分であるので、電流集中緩和電極７０は、ドレイン領域３０と連続的に接続されるように、細長く直線に近いＥ字形状をしている。よって、電流集中緩和電極７０は、半導体装置１００内の総てのドレイン領域３０、３１（図１においては３本）の延在方向両端部と接続され、ドレイン領域３０、３１と連続的に形成されている。そして、ドレイン領域３０、３１及び電流集中緩和電極７０は、両者で２本のゲート４０及びソース領域２０と、１つのバックゲート領域５０の周囲を囲んでいる。更に、半導体装置１００の長手方向両端のドレイン領域３１と、電流集中緩和電極７０とで囲んでいる領域の周囲を、基板電極８０が、ＬＯＣＯＳ６０を介して囲んでおり、半導体装置１００が構成されている。 The source region 20 and the drain regions 30 and 31 have an elongated rectangular shape and extend in parallel to face each other. A gate 40 is disposed between the source region 20 and the drain regions 30 and 31. The gate 40 is provided adjacent to the source region 20 and away from the drain region 30 so as to extend along the source region 20 in parallel with the source region 20 and the drain region 30. The back gate region 50 is provided between the adjacent source regions 20 facing each other, and has a shape and a width including the source region 20 in the extending direction. A LOCOS 60 is provided in a region between the gate 40 and the drain regions 30 and 31. One drain region 30 at the center is opposed to the gate 40 via the LOCOS 60, and both sides are disposed between the gates 40. On the other hand, the two drain regions 31 at both ends are opposed to the gate 40 through the LOCOS 60 on the center side, but are arranged to face the substrate electrode through the LOCOS 60 on the end side. The current concentration relaxation electrode 70 is provided so as to extend in a direction perpendicular to the extending direction of the drain region 30. Since the drain region 30 is a portion facing the source region 20 having the same length as the source region 20, the current concentration relaxation electrode 70 is elongated and linearly connected so as to be continuously connected to the drain region 30. It has a close E shape. Therefore, the current concentration relaxation electrode 70 is connected to both ends in the extending direction of all the drain regions 30 and 31 (three in FIG. 1) in the semiconductor device 100 and is formed continuously with the drain regions 30 and 31. Has been. The drain regions 30 and 31 and the current concentration relaxation electrode 70 surround the two gates 40 and the source region 20 and the one back gate region 50. Furthermore, the substrate electrode 80 surrounds the region surrounded by the drain region 31 at both ends in the longitudinal direction of the semiconductor device 100 and the current concentration relaxation electrode 70 via the LOCOS 60, thereby forming the semiconductor device 100. Yes.
　　ここで、ゲート４０と、ゲート４０の両側のソース領域２０及びドレイン領域３０、３１と、バックゲート５０とで１つのトランジスタセルを構成する。よって、図１に示す半導体装置１００には、４つのトランジスタセルが含まれていることになる。つまり、両端のドレイン領域３１は、１本で１つのトランジスタセルに対応しているが、中央のドレイン領域３０は、１本で２つのトランジスタセルのドレイン領域３０を兼ねていることになる。 Here, the gate 40, the source region 20 and the drain regions 30 and 31 on both sides of the gate 40, and the back gate 50 constitute one transistor cell. Therefore, the semiconductor device 100 illustrated in FIG. 1 includes four transistor cells. That is, one drain region 31 at both ends corresponds to one transistor cell, but one central drain region 30 also serves as the drain region 30 of two transistor cells.
　　次に、個々の構成要素について説明する。 Next, each component will be described.
　　半導体基板１０は、本実施例に係る半導体装置１００が形成される基板である。半導体基板１０は、種々の半導体材料からなる基板が用いられてよいが、例えば、シリコン基板が用いられてもよい。なお、半導体基板１０は、半導体装置１００がｎチャネル型ＬＤＭＯＳとして構成される場合には、ｐ型半導体基板として構成される。 The semiconductor substrate 10 is a substrate on which the semiconductor device 100 according to the present embodiment is formed. As the semiconductor substrate 10, a substrate made of various semiconductor materials may be used. For example, a silicon substrate may be used. The semiconductor substrate 10 is configured as a p-type semiconductor substrate when the semiconductor device 100 is configured as an n-channel LDMOS.
　　ソース領域２０は、半導体基板１０の表面領域に形成された拡散層であり、ＬＤＭＯＳとして構成される半導体装置１００のソースとして機能する。なお、半導体基板１０の表面領域とは、半導体基板１０の表面を含む表面側の領域を意味し、ソース領域２０の上に、酸化膜等の絶縁膜が形成されたり、金属やポリシリコン等の導電膜が形成されたりしていてもよい。 The source region 20 is a diffusion layer formed in the surface region of the semiconductor substrate 10 and functions as a source of the semiconductor device 100 configured as an LDMOS. Note that the surface region of the semiconductor substrate 10 means a region on the surface side including the surface of the semiconductor substrate 10, and an insulating film such as an oxide film is formed on the source region 20, or a metal, polysilicon, or the like is formed. A conductive film may be formed.
　　ソース領域２０の上層には、絶縁層が形成され、絶縁層の上層には、金属からなる配線層が形成される。そして、配線層との電気的接続を行うために、絶縁層にコンタクトホール２５が複数形成される。そのコンタクトホール２５の位置が、図１において示されている。 An insulating layer is formed above the source region 20, and a wiring layer made of metal is formed above the insulating layer. A plurality of contact holes 25 are formed in the insulating layer for electrical connection with the wiring layer. The position of the contact hole 25 is shown in FIG.
　　ソース領域２０は、半導体装置１００がｎチャネル型ＬＤＭＯＳとして構成される場合には、ｎ型拡散層で構成される。 The source region 20 is configured by an n-type diffusion layer when the semiconductor device 100 is configured as an n-channel LDMOS.
　　ドレイン領域３０、３１は、半導体基板１０の表面領域に形成された拡散層であり、ＬＤＭＯＳとして構成される半導体装置１００のドレインとして機能する。縦型ＭＯＳトランジスタにおいては、ドレインは半導体基板１０の裏面に形成されるが、本実施例に係る半導体装置１００は、横型ＭＯＳトランジスタとして構成されるので、ドレイン領域３０、３１は、半導体基板１００の表面領域に形成される。 The drain regions 30 and 31 are diffusion layers formed in the surface region of the semiconductor substrate 10 and function as drains of the semiconductor device 100 configured as an LDMOS. In the vertical MOS transistor, the drain is formed on the back surface of the semiconductor substrate 10. However, since the semiconductor device 100 according to this embodiment is configured as a horizontal MOS transistor, the drain regions 30 and 31 are formed on the semiconductor substrate 100. Formed in the surface region.
　　ドレイン領域３０、３１は、電流集中緩和電極７０と連続的な拡散層として形成されるが、ＬＤＭＯＳのドレインとして機能するのは、ソース領域２０と対向している部分である。よって、電流集中緩和電極７０と連続的に形成されていても、機能的には電流集中緩和電極７０と区別される。 The drain regions 30 and 31 are formed as a diffusion layer continuous with the current concentration relaxation electrode 70, but it is a portion facing the source region 20 that functions as the drain of the LDMOS. Therefore, even if it is formed continuously with the current concentration relaxation electrode 70, it is functionally distinguished from the current concentration relaxation electrode 70.
　　ドレイン領域３０は、平面構成的に、両側がＬＯＣＯＳ６０を介してゲート４０に挟まれているドレイン領域である。図１においては、中央に存在する１つのドレイン領域３０が該当する。但し、図１の構成よりもトランジスタセルの数が多い場合には、両端の２つのドレイン領域３１以外は、総て両側がゲート４０で挟まれたドレイン領域３０となり、複数のドレイン領域３０が存在することになる。ドレイン領域３０においても、上層に絶縁層、更に絶縁層の上層に金属の配線層が形成され、絶縁層には電気的接続を図るためのコンタクトホール３５が複数形成される。図１において、コンタクトホール３５の位置が示されている。 The drain region 30 is a drain region sandwiched between the gates 40 via the LOCOS 60 in plan view. In FIG. 1, one drain region 30 existing in the center corresponds. However, when the number of transistor cells is larger than that in the configuration of FIG. 1, all the drain regions 30 except for the two drain regions 31 at both ends are sandwiched between the gates 40, and there are a plurality of drain regions 30. Will do. Also in the drain region 30, an insulating layer is formed as an upper layer, and a metal wiring layer is formed as an upper layer of the insulating layer, and a plurality of contact holes 35 for electrical connection are formed in the insulating layer. In FIG. 1, the position of the contact hole 35 is shown.
　　ドレイン領域３１は、半導体装置１００の長手方向に配置された複数のトランジスタセルのうち、両端に存在するトランジスタセルのドレイン領域３１であり、延在方向の一方の辺はゲート４０と対向し、他方の辺は基板電極８０と対向するドレイン領域３１である。よって、トランジスタセルが１列に配列されている場合には、１列につき２つのドレイン領域３１を有する。ドレイン領域３１においても、コンタクトホール３５と同様に複数のコンタクトホール３６が形成され、上層の配線層との電気的接続が行われる。また、ドレイン領域３０とドレイン領域３１とは同一の配線層で接続され、ドレイン領域３０、３１が同電位となるように構成される。 The drain region 31 is a drain region 31 of a transistor cell that exists at both ends of the plurality of transistor cells arranged in the longitudinal direction of the semiconductor device 100, and one side in the extending direction faces the gate 40, and the other This side is the drain region 31 facing the substrate electrode 80. Therefore, when the transistor cells are arranged in one column, two drain regions 31 are provided for each column. Also in the drain region 31, a plurality of contact holes 36 are formed in the same manner as the contact holes 35, and electrical connection with the upper wiring layer is performed. Further, the drain region 30 and the drain region 31 are connected by the same wiring layer, and the drain regions 30 and 31 are configured to have the same potential.
　　ドレイン領域３０、３１は、半導体装置１００がｎチャネルＬＤＭＯＳとして構成される場合には、ｎ型拡散層として構成される。 The drain regions 30 and 31 are configured as n-type diffusion layers when the semiconductor device 100 is configured as an n-channel LDMOS.
　　ゲート４０は、半導体基板１０の表面上に形成された電極であり、ＬＤＭＯＳのゲートとして機能する。 The gate 40 is an electrode formed on the surface of the semiconductor substrate 10 and functions as an LDMOS gate.
　　バックゲート領域５０は、半導体基板１０の表面領域に形成された拡散層であり、ソース領域２０に対するボディ領域として構成される。よって、バックゲート領域５０は、ソース領域２０の側面及び底面を側方及び下方から覆うようにして構成される。 The back gate region 50 is a diffusion layer formed in the surface region of the semiconductor substrate 10 and is configured as a body region for the source region 20. Therefore, the back gate region 50 is configured to cover the side surface and the bottom surface of the source region 20 from the side and below.
　　図２は、図１のＡ－Ａ'断面の断面構成を示した図である。図２に示すように、バックゲート領域５０は、ソース領域２０の側面及び底面を側方及び下方から覆うようにして構成されていることが分かる。また、図２から、上述のゲート４０が、半導体基板１０の表面上に、酸化膜９０とＬＯＣＯＳ６０を跨ぐように形成されていることも分かる。 FIG. 2 is a diagram showing a cross-sectional configuration of the AA ′ cross section of FIG. As shown in FIG. 2, it can be seen that the back gate region 50 is configured to cover the side surface and bottom surface of the source region 20 from the side and from below. 2 also shows that the gate 40 described above is formed on the surface of the semiconductor substrate 10 so as to straddle the oxide film 90 and the LOCOS 60. FIG.
　　図１に戻る。バックゲート領域５０は、ソース領域２０と同様に、上層に絶縁層が形成され、絶縁層の上層に更に配線層が形成され、絶縁層にコンタクトホール５５が複数形成される。図１において、コンタクトホール５５の位置が示されている。一般的に、バックゲート領域５０とソース領域２０には、同電位が供給される場合が多い。よって、バックゲート領域５０とソース領域２０は、同一の配線層に接続され、同電位が供給されてよい。供給される電位は、例えば、接地電位の０Ｖであってもよい。 Return to Figure 1. In the back gate region 50, similarly to the source region 20, an insulating layer is formed on the upper layer, a wiring layer is further formed on the insulating layer, and a plurality of contact holes 55 are formed on the insulating layer. In FIG. 1, the position of the contact hole 55 is shown. In general, the back gate region 50 and the source region 20 are often supplied with the same potential. Therefore, the back gate region 50 and the source region 20 may be connected to the same wiring layer and supplied with the same potential. The supplied potential may be, for example, 0 V of the ground potential.
　　バックゲート領域５０は、半導体装置１００が、ｎチャネルＬＤＭＯＳとして構成されている場合には、ｐ型拡散層として構成される。 The back gate region 50 is configured as a p-type diffusion layer when the semiconductor device 100 is configured as an n-channel LDMOS.
　　ＬＯＣＯＳ６０は、ドレイン領域３０を、横方向に絶縁分離するための絶縁膜であり、ドレイン領域３０を両側から挟むようにして設けられる。また、ＬＯＣＯＳ６０は、ドレイン領域３０を、延在方向の両端側からも囲み、他の拡散層から絶縁分離している。 LOCOS 60 is an insulating film for insulating and isolating the drain region 30 in the lateral direction, and is provided so as to sandwich the drain region 30 from both sides. Further, the LOCOS 60 surrounds the drain region 30 from both ends in the extending direction, and is insulated and isolated from other diffusion layers.
　　電流集中緩和電極７０は、ドレイン領域３０の延在方向の両端部をガードし、逆流電流を緩和するための拡散層である。電流集中緩和電極７０は、ドレイン領域３０と同様に、半導体基板１０の表面領域に設けられる。電流集中緩和電極７０は、平面構成的には、ドレイン領域３０、３１の延在方向と垂直な方向に延在し、ドレイン領域３０、３１と基板電極８０との間に設けられるとともに、ドレイン領域３０、３１の両端部と連続的に接続して形成される。これにより、半導体基板１０側からドレイン領域３０に向かって流れる逆流電流Ｉ３を、ドレイン領域３０に到達する前に電流集中緩和電極７０で吸い上げ、ドレイン領域３０の端部のコンタクトホール３５への逆流電流の集中を回避することができる。また、電流集中緩和電極７０は、図１の構成においては、ドレイン領域３１の端部への逆流電流も緩和している。 The current concentration relaxation electrode 70 is a diffusion layer that guards both ends of the drain region 30 in the extending direction and relaxes the backflow current. Similar to the drain region 30, the current concentration relaxation electrode 70 is provided in the surface region of the semiconductor substrate 10. The current concentration relaxation electrode 70 extends in a direction perpendicular to the extending direction of the drain regions 30 and 31 in a plan configuration, is provided between the drain regions 30 and 31 and the substrate electrode 80, and It is formed by being continuously connected to both end portions of 30,31. Thus, the backflow current I3 flowing from the semiconductor substrate 10 toward the drain region 30 is sucked up by the current concentration relaxation electrode 70 before reaching the drain region 30, and the backflow current to the contact hole 35 at the end of the drain region 30 is absorbed. Concentration can be avoided. Further, in the configuration of FIG. 1, the current concentration relaxation electrode 70 also relaxes the backflow current to the end of the drain region 31.
　　電流集中緩和電極７０の上層には、ドレイン領域３０と同様に、絶縁層を介して配線層が形成され、絶縁層にはコンタクトホール７５が複数形成される。複数のコンタクトホール７５は、電流集中緩和電極７０の延在方向に沿って密に形成されているので、ドレイン領域３０の端部に流れ込む逆流電流Ｉ３を、電流集中緩和電極７０の各コンタクトホール７５で配線層に流し、電流を複数のコンタクトホール７５で分散することができる。 As in the drain region 30, a wiring layer is formed over the current concentration relaxation electrode 70 via an insulating layer, and a plurality of contact holes 75 are formed in the insulating layer. Since the plurality of contact holes 75 are densely formed along the extending direction of the current concentration relaxation electrode 70, the backflow current I 3 flowing into the end of the drain region 30 is caused to flow into each contact hole 75 of the current concentration relaxation electrode 70. The current can be passed through the wiring layer and the current can be dispersed by the plurality of contact holes 75.
　　図１において、逆流電流Ｉ３が破線矢印で示されているが、中央のゲート４０で両側を挟まれたドレイン領域３０の両端部は、電流集中緩和電極７０でガードされ、逆流電流Ｉ３の集中が回避されている。また、基板電極８０に対向するように電流集中緩和電極７０及びドレイン領域３１が形成されているので、逆流電流Ｉ３は、何れかの箇所に集中することなく、全体に亘ってほぼ均一に電流集中緩和電極７０及びドレイン領域３１に流れ込んでいる。このように、実施例１に係る半導体装置１００は、電流集中緩和電極７０を、ドレイン領域３０の延在方向の端部と基板電極８０との間に、ドレイン領域３０の延在方向の延長線上に存在し、かつドレイン領域３０、３１と連続的な拡散層を形成して設けることにより、中央のドレイン領域３０の端部への逆流電流Ｉ３の集中を確実に緩和することができる。 In FIG. 1, the reverse current I3 is indicated by a broken-line arrow, but both end portions of the drain region 30 sandwiched by the center gate 40 are guarded by the current concentration relaxation electrode 70, and the concentration of the reverse current I3 is reduced. It has been avoided. Further, since the current concentration relaxation electrode 70 and the drain region 31 are formed so as to face the substrate electrode 80, the backflow current I3 does not concentrate on any part, but the current concentration is almost uniform throughout. It flows into the relaxation electrode 70 and the drain region 31. As described above, in the semiconductor device 100 according to the first embodiment, the current concentration relaxation electrode 70 is disposed on the extension line in the extending direction of the drain region 30 between the end portion in the extending direction of the drain region 30 and the substrate electrode 80. By forming a diffusion layer that is present in the region and continuous with the drain regions 30 and 31, the concentration of the backflow current I3 at the end of the central drain region 30 can be reliably mitigated.
　　基板電極８０は、半導体基板１０の基準電位を定めるための電極であり、基準電位が供給される。通常、基準電位は、接地電位の０Ｖに設定されてよい。また、基板電極８０は、複数のトランジスタセルを囲み、１個の半導体装置１００を構成する。そして、半導体装置１００に、基準電位を供給する。 The substrate electrode 80 is an electrode for determining the reference potential of the semiconductor substrate 10 and is supplied with the reference potential. Usually, the reference potential may be set to 0 V of the ground potential. The substrate electrode 80 surrounds a plurality of transistor cells and constitutes one semiconductor device 100. Then, a reference potential is supplied to the semiconductor device 100.
　　基板電極８０の上層には、絶縁層が形成され、更に絶縁層の上に金属の配線層が形成される。絶縁層には、コンタクトホール８５が複数形成され、配線層からコンタクトホール８５を介して、基板電極８０に半導体基板１０の基準電位を供給する。図１には、コンタクトホール８５の位置が示されており、基板電極８０の４辺に亘り、コンタクトホール８５が形成されている。 An insulating layer is formed on the substrate electrode 80, and a metal wiring layer is further formed on the insulating layer. A plurality of contact holes 85 are formed in the insulating layer, and the reference potential of the semiconductor substrate 10 is supplied to the substrate electrode 80 from the wiring layer through the contact holes 85. FIG. 1 shows the position of the contact hole 85, and the contact hole 85 is formed over four sides of the substrate electrode 80.
　　基板電極８０は、本実施例に係る半導体装置１００がｎチャネルＬＤＭＯＳとして構成される場合には、ｐ型拡散層として構成される。 The substrate electrode 80 is configured as a p-type diffusion layer when the semiconductor device 100 according to the present embodiment is configured as an n-channel LDMOS.
　　図２は、図１のＡ－Ａ'断面における構成を示した図である。図２において、図１において説明した構成要素には同一の参照符号を付し、その説明を省略する。以下、図１において説明しなかった点についてのみ説明する。 FIG. 2 is a diagram showing a configuration in the section AA ′ of FIG. In FIG. 2, the same reference numerals are assigned to the components described in FIG. Hereinafter, only the points not described in FIG. 1 will be described.
　　図２において、半導体基板１０の、基板電極８０よりも内側の領域に、ｎ層１５が形成され、ｎ層１５の表面領域に、トランジスタセルが形成されている。ｎ層１５は、ソース領域２０、ドレイン領域３０及び電流集中緩和電極７０よりも、低濃度の拡散層として構成されている。ｎ層１５は、ウェル層であっても、エピタキシャル成長層であってもよいし、その他の製法による拡散層であってもよい。 In FIG. 2, an n layer 15 is formed in a region inside the substrate electrode 80 of the semiconductor substrate 10, and a transistor cell is formed in a surface region of the n layer 15. The n layer 15 is configured as a diffusion layer having a lower concentration than the source region 20, the drain region 30, and the current concentration relaxation electrode 70. The n layer 15 may be a well layer, an epitaxial growth layer, or a diffusion layer formed by another manufacturing method.
　　ソース領域２０、ドレイン領域３０、バックゲート領域５０及び電流集中緩和電極７０を含むｎ層１５の表面、つまりＬＯＣＯＳ６０で覆われていない領域は、酸化膜９０で表面が覆われている。コンタクトホール２５、３５、３６、５５、７５を形成する場合には、コンタクトホール２５、３５、３６、５５、７５が形成される位置の酸化膜９０を除去し、コンタクトホール２５、３５、３６、５５、７５と各拡散領域との電気的接続が適切に行われるように形成する。 The surface of the n layer 15 including the source region 20, the drain region 30, the back gate region 50, and the current concentration relaxation electrode 70, that is, the region not covered with the LOCOS 60 is covered with the oxide film 90. When forming the contact holes 25, 35, 36, 55, 75, the oxide film 90 at the position where the contact holes 25, 35, 36, 55, 75 are formed is removed, and the contact holes 25, 35, 36, It forms so that electrical connection with 55 and 75 and each diffusion region may be performed appropriately.
　　バックゲート領域５０と、ドレイン領域３０との間には、寄生ダイオード１１０が形成され、半導体基板１０と、ドレイン領域３０との間には、寄生ダイオード１２０が形成される。図８において説明したように、寄生ダーオード１１０を流れる電流Ｉ２の影響は、従来から小さい。一方、寄生ダイオード１２０を流れる電流Ｉ３の影響は、従来、両側がゲート４０に挟まれた中央のドレイン領域３０では大きかったが、本実施例に係る半導体装置１００においては、電流集中緩和電極７０を設けたことにより小さくなっている。図２に示すように、電流Ｉ３がほぼ半導体基板１０の下側から流れ込むものだけになっていることが分かる。 A parasitic diode 110 is formed between the back gate region 50 and the drain region 30, and a parasitic diode 120 is formed between the semiconductor substrate 10 and the drain region 30. As described with reference to FIG. 8, the influence of the current I2 flowing through the parasitic diode 110 is conventionally small. On the other hand, the influence of the current I3 flowing through the parasitic diode 120 has hitherto been large in the central drain region 30 sandwiched between the gates 40 on both sides. However, in the semiconductor device 100 according to the present embodiment, the current concentration relaxation electrode 70 is It has become smaller by providing it. As shown in FIG. 2, it can be seen that the current I3 flows only from the lower side of the semiconductor substrate 10.
　　このように、本実施例に係る半導体装置１００においては、ゲート４０に両側が挟まれたドレイン領域３０の端部への逆流電流Ｉ３の集中を防ぐことができ、半導体装置１００の破損を防ぐことができる。 As described above, in the semiconductor device 100 according to the present embodiment, the backflow current I3 can be prevented from being concentrated on the end of the drain region 30 sandwiched between the gates 40, and the semiconductor device 100 can be prevented from being damaged. Can do.
　　図３は、実施例１に係る半導体装置１００の半導体基板１０の上層に設けられた配線層１５０の平面構成の一例を透過的に示した図である。図３において、配線層１５０は、ソース配線層１１０と、ドレイン配線層１２０と、基板電極配線層１３０とを有する。ソース配線層１１０、ドレイン配線層１２０及び基板電極配線層１３０は、アルミニウムや銅等の配線材料として用いられる金属が用いられる。 FIG. 3 is a diagram transparently showing an example of a planar configuration of the wiring layer 150 provided on the upper layer of the semiconductor substrate 10 of the semiconductor device 100 according to the first embodiment. In FIG. 3, the wiring layer 150 includes a source wiring layer 110, a drain wiring layer 120, and a substrate electrode wiring layer 130. For the source wiring layer 110, the drain wiring layer 120, and the substrate electrode wiring layer 130, a metal used as a wiring material such as aluminum or copper is used.
　　ソース配線層１１０は、ソース領域２０とバックゲート領域５０に電力を供給するための配線である。ソース配線層１１０は、ソース領域２０のコンタクトホール２５と、バックゲート領域５０のコンタクトホール５５を上から覆うように、長方形状に設けられる。 The source wiring layer 110 is a wiring for supplying power to the source region 20 and the back gate region 50. The source wiring layer 110 is provided in a rectangular shape so as to cover the contact hole 25 in the source region 20 and the contact hole 55 in the back gate region 50 from above.
　　ドレイン配線層１２０は、ドレイン領域３０、３１及び電流集中緩和電極７０に電力を供給するための配線層である。ドレイン領域３０、３１及び電力集中緩和電極７０は、総て同電位となるように、同一のドレイン配線層１２０から電位が供給される。ドレイン配線層１２０は、ドレイン領域３０のコンタクトホール３５、ドレイン領域のコンタクトホール３６及び電流集中緩和電極７０のコンタクトホール７０の総てを覆い、かつソース配線層１１０を接触せずに囲むように、８の字状の形状で設けられる。 The drain wiring layer 120 is a wiring layer for supplying power to the drain regions 30 and 31 and the current concentration relaxation electrode 70. The drain regions 30 and 31 and the power concentration relaxation electrode 70 are supplied with the potential from the same drain wiring layer 120 so that they all have the same potential. The drain wiring layer 120 covers all of the contact hole 35 of the drain region 30, the contact hole 36 of the drain region, and the contact hole 70 of the current concentration relaxation electrode 70, and surrounds the source wiring layer 110 without contact. It is provided in the shape of figure 8.
　　基板電極配線層１３０は、基板電極８０に基準電位を供給するための配線層であり、基板電極８０のコンタクトホール８５を上から覆うように、枠状に設けられる。 The substrate electrode wiring layer 130 is a wiring layer for supplying a reference potential to the substrate electrode 80, and is provided in a frame shape so as to cover the contact hole 85 of the substrate electrode 80 from above.
　　このように、本実施例に係る半導体装置１００によれば、半導体基板１０の上層の配線層１５０において、ドレイン領域３０、３１と電流集中緩和電極７０とを同じドレイン配線層１２０から電力供給を行うことにより、ドレイン領域３０、３１と電流集中緩和電極７０とを容易に同電位とすることができる。 Thus, according to the semiconductor device 100 according to the present embodiment, the drain regions 30 and 31 and the current concentration relaxation electrode 70 are supplied with power from the same drain wiring layer 120 in the wiring layer 150 on the upper layer of the semiconductor substrate 10. Thus, the drain regions 30 and 31 and the current concentration relaxation electrode 70 can be easily set to the same potential.
　　なお、図３においては、図１の平面構成に適合するように配線層１５０のパターンを形成したが、図１の平面構成が変化すれば、それに合わせて配線層１５０のパターンも変化して良いことは言うまでもない。 In FIG. 3, the pattern of the wiring layer 150 is formed so as to conform to the planar configuration of FIG. 1. However, if the planar configuration of FIG. 1 changes, the pattern of the wiring layer 150 may change accordingly. Needless to say.
　　実施例１に係る半導体装置１００によれば、延在方向の両側がゲート４０で挟まれたドレイン領域３０の端部を、ドレイン領域３０、３１と連続的に形成された電流集中緩和電極７０で完全にガードするので、ドレイン領域３０の端部への逆流電流Ｉ３の集中を防ぐことができ、半導体装置１００の誘導電流による破壊を防止することができる。 According to the semiconductor device 100 according to the first embodiment, the end portion of the drain region 30 sandwiched between the gates 40 on both sides in the extending direction is the current concentration relaxation electrode 70 formed continuously with the drain regions 30 and 31. Since it is completely guarded, it is possible to prevent the backflow current I3 from concentrating on the end of the drain region 30, and to prevent the semiconductor device 100 from being damaged by the induced current.
　　図４は、本発明の実施例２に係る半導体装置１０１の平面構成の一例を示した図である。実施例２に係る半導体装置１０１において、実施例１に係る半導体装置１００と同様の構成要素には、同一の参照符号を付し、その説明を省略する。 FIG. 4 is a diagram illustrating an example of a planar configuration of the semiconductor device 101 according to the second embodiment of the present invention. In the semiconductor device 101 according to the second embodiment, the same components as those of the semiconductor device 100 according to the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.
　　具体的には、実施例２に係る半導体装置１０１は、半導体基板１０と、ソース領域２０と、ゲート４０と、バックゲート領域５０と、ＬＯＣＯＳ６０と、基板電極８０と、コンタクトホール２５、５５、８５については、実施例１に係る半導体装置１００と同一の構成要素であり、配置も同一であるので、同一の参照符号を付してその説明を省略する。 Specifically, the semiconductor device 101 according to the second embodiment includes a semiconductor substrate 10, a source region 20, a gate 40, a back gate region 50, a LOCOS 60, a substrate electrode 80, and contact holes 25, 55, and 85. Are the same constituent elements as those of the semiconductor device 100 according to the first embodiment, and the arrangement thereof is also the same.
　　実施例２に係る半導体装置１０１は、ドレイン領域３２、３３と電流集中緩和電極７１とが別個に独立して形成されており、双方が連続的に形成されていない点で、実施例１に係る半導体装置１００と異なっている。しかしながら、電流集中緩和電極７１が、ソース領域２０及びドレイン領域３２の延在方向と垂直な方向に延在し、ドレイン領域３０の延在方向の端部と基板電極８０との間に存在している点では、実施例１に係る半導体装置１００と共通している。 The semiconductor device 101 according to the second embodiment is related to the first embodiment in that the drain regions 32 and 33 and the current concentration relaxation electrode 71 are separately formed independently and are not formed continuously. Different from the semiconductor device 100. However, the current concentration relaxation electrode 71 extends in a direction perpendicular to the extending direction of the source region 20 and the drain region 32, and exists between the end portion of the extending direction of the drain region 30 and the substrate electrode 80. In common, the semiconductor device 100 according to the first embodiment is common.
　　このように、ドレイン領域３２、３３と電流集中緩和電極７１は、半導体基板１０の表面領域で必ずしも連続的に形成されていなくてもよい。この場合であっても、電流集中緩和電極７１は、半導体基板１０からドレイン領域３２の両端部に流れ込む逆流電流Ｉ３をガードし、複数のコンタクトホール７６を介して、ドレイン領域３２に逆流電流Ｉ３が到達する前に逆流電流を吸い上げてしまうので、ドレイン領域３２の両端部のコンタクトホール３７への電流の集中を回避することができる。 As described above, the drain regions 32 and 33 and the current concentration relaxation electrode 71 are not necessarily formed continuously in the surface region of the semiconductor substrate 10. Even in this case, the current concentration relaxation electrode 71 guards the backflow current I3 that flows from the semiconductor substrate 10 to both ends of the drain region 32, and the backflow current I3 flows to the drain region 32 via the plurality of contact holes 76. Since the backflow current is sucked up before reaching, concentration of current in the contact holes 37 at both ends of the drain region 32 can be avoided.
　　なお、電流集中緩和電極７１は、細長い長方形の形状をしており、半導体装置１００の長手方向において、ドレイン領域３２、３３を総てガードするように延在している。また、電流集中緩和電極７１の上には、複数のコンタクトホール７６が、電流集中緩和電極７１の延在方向に沿って密に形成されており、逆流電流Ｉ３を、分散させて配線層に流すことが可能に構成されている。 Note that the current concentration relaxation electrode 71 has an elongated rectangular shape, and extends so as to guard the drain regions 32 and 33 in the longitudinal direction of the semiconductor device 100. In addition, a plurality of contact holes 76 are densely formed on the current concentration relaxation electrode 71 along the extending direction of the current concentration relaxation electrode 71, and the backflow current I3 is distributed to flow through the wiring layer. It is configured to be possible.
　　図５は、実施例２に係る半導体装置１０１の半導体基板１０の上層に形成された配線層１５１の平面構成の一例を透過的に示した図である。図５において、配線層１５１は、ソース配線層１１１と、ドレイン配線層１２１と、基板電極配線層１３１とを備える。ソース配線層１１１は、ソース領域２０及びバックゲート領域５０に電力供給を行う配線層であり、ドレイン配線層１２１は、ドレイン領域３２、３３及び電流集中緩和電極７１に電力供給を行う配線層である点は、実施例１と同様である。また、基板電極配線層１３１が、基板電極８１に基準電位を与える配線層である点も、実施例１と同様である。 FIG. 5 is a diagram transparently showing an example of a planar configuration of the wiring layer 151 formed in the upper layer of the semiconductor substrate 10 of the semiconductor device 101 according to the second embodiment. In FIG. 5, the wiring layer 151 includes a source wiring layer 111, a drain wiring layer 121, and a substrate electrode wiring layer 131. The source wiring layer 111 is a wiring layer that supplies power to the source region 20 and the back gate region 50, and the drain wiring layer 121 is a wiring layer that supplies power to the drain regions 32 and 33 and the current concentration relaxation electrode 71. The point is the same as in the first embodiment. The substrate electrode wiring layer 131 is the same as the first embodiment in that the substrate electrode wiring layer 131 is a wiring layer that applies a reference potential to the substrate electrode 81.
　　ドレイン配線層１２１は、ドレイン領域３２上に形成されたコンタクトホール３７と、ドレイン領域３３上に形成されたコンタクトホール３８と、電流集中緩和電極７１上に形成されたコンタクトホール７６の総てを覆うように形成されている。つまり、ドレイン領域３２、３３及び電流集中緩和電極７１は、ドレイン配線層１２１を介して電気的に接続され、同電位となる。このように、半導体基板１０の表面領域において、ドレイン領域３２、３３と電流集中緩和電極７１が接続されていない場合であっても、上層のドレイン配線層１２１により、ドレイン領域３２、３３と電流集中緩和電極７１とを同電位にすることができる。 The drain wiring layer 121 covers all of the contact hole 37 formed on the drain region 32, the contact hole 38 formed on the drain region 33, and the contact hole 76 formed on the current concentration relaxation electrode 71. It is formed as follows. That is, the drain regions 32 and 33 and the current concentration relaxation electrode 71 are electrically connected via the drain wiring layer 121 and have the same potential. Thus, even if the drain regions 32 and 33 and the current concentration relaxation electrode 71 are not connected in the surface region of the semiconductor substrate 10, the drain regions 32 and 33 and the current concentration are separated by the upper drain wiring layer 121. The relaxing electrode 71 can be set to the same potential.
　　なお、半導体基板１０の表面領域のドレイン領域３２、３３及び電流集中緩和電極７１の構成は、実施例１とは若干異なるが、全体としての配置はほぼ同様である。その結果、コンタクトホール３７、３８、７６の配置も実施例１に係る半導体装置１００とほぼ同様となっている。よって、ドレイン配線層１２１の形状は、実施例１に係るドレイン配線層１２０とほぼ同様の形状となっている。このように、全体の配置構成がほぼ同様であれば、ドレイン領域３２、３３と電流集中緩和電極７１とが連続的に形成されていても、独立的に形成されていても、ほぼ同様のドレイン配線層１２０、１２１を用いることができる。 The configurations of the drain regions 32 and 33 and the current concentration relaxation electrode 71 in the surface region of the semiconductor substrate 10 are slightly different from those in the first embodiment, but the overall arrangement is substantially the same. As a result, the arrangement of the contact holes 37, 38, and 76 is substantially the same as that of the semiconductor device 100 according to the first embodiment. Therefore, the shape of the drain wiring layer 121 is substantially the same as that of the drain wiring layer 120 according to the first embodiment. As described above, if the overall arrangement is substantially the same, the drain regions 32 and 33 and the current concentration relaxation electrode 71 may be formed in a continuous manner or in an independent manner. The wiring layers 120 and 121 can be used.
　　実施例２に係る半導体装置１０１おいては、ソース領域２０、バックゲート領域５０及び基板電極８０の配置構成も、実施例１に係る半導体装置１００と同様であるので、ソース配線層１１１及び基板電極配線層１３１の構成も、実施例１のソース配線層１１０及び基板電極配線層１３０と同様の構成となる。よって、結果的に、実施例２に係る半導体装置１０１の配線層１５１は、実施例１に係る半導体装置１００の配線層１５０と同一の配線パターンを用いることができる。 In the semiconductor device 101 according to the second embodiment, since the arrangement configuration of the source region 20, the back gate region 50, and the substrate electrode 80 is the same as that of the semiconductor device 100 according to the first embodiment, the source wiring layer 111 and the substrate electrode are arranged. The configuration of the wiring layer 131 is the same as that of the source wiring layer 110 and the substrate electrode wiring layer 130 of the first embodiment. As a result, the wiring layer 151 of the semiconductor device 101 according to the second embodiment can use the same wiring pattern as the wiring layer 150 of the semiconductor device 100 according to the first embodiment.
　　このように、実施例２に係る半導体装置１０１によれば、ドレイン領域３２、３３と電流集中緩和領域７１を半導体基板１０の表面領域で別個に設けつつも、ドレイン領域３２、３３と電流集中緩和電極７１とを配線層１５１で電気的に接続し、同電位とすることができる。これにより、自由な半導体基板１０上のレイアウトを可能としつつ、両側がゲート４０に挟まれた配置のドレイン領域３２の両端に、逆流電流Ｉ３が集中する現象を回避することができ、半導体装置１０１の破壊を防止することができる。 Thus, according to the semiconductor device 101 according to the second embodiment, the drain regions 32 and 33 and the current concentration relaxation region 71 are separately provided on the surface region of the semiconductor substrate 10, but the drain regions 32 and 33 and the current concentration relaxation are provided. The electrode 71 can be electrically connected to the wiring layer 151 to have the same potential. Thereby, while allowing a free layout on the semiconductor substrate 10, it is possible to avoid a phenomenon in which the backflow current I3 concentrates on both ends of the drain region 32 arranged on both sides of the gate 40, and the semiconductor device 101 Can be prevented.
　　図６は、本発明の実施例３に係る半導体装置１０２の平面構成の一例を示した図である。図６において、実施例２に係る半導体装置１０１と同様の構成要素には、同一の参照符号を付し、その説明を省略する。 FIG. 6 is a diagram illustrating an example of a planar configuration of the semiconductor device 102 according to the third embodiment of the present invention. In FIG. 6, the same components as those of the semiconductor device 101 according to the second embodiment are denoted by the same reference numerals, and the description thereof is omitted.
　　具体的には、実施例３に係る半導体装置１０２は、半導体基板１０と、ソース領域２０と、ドレイン領域３２、３３と、ゲート４０と、バックゲート領域５０と、ＬＯＣＯＳ６０と、基板電極８０と、コンタクトホール２５、３７、３８、５５、８５については、実施例２に係る半導体装置１０１と同様であるので、これらには実施例２と同一の参照符号を付して、その説明を省略する。 Specifically, the semiconductor device 102 according to the third embodiment includes a semiconductor substrate 10, a source region 20, drain regions 32 and 33, a gate 40, a back gate region 50, a LOCOS 60, a substrate electrode 80, Since the contact holes 25, 37, 38, 55, and 85 are the same as those of the semiconductor device 101 according to the second embodiment, the same reference numerals as those in the second embodiment are given to the contact holes 25, 37, 38, 55, and 85, and the description thereof is omitted.
　　実施例３に係る半導体装置１０２は、電流集中緩和電極７２が、半導体装置１０２の長手方向両端のドレイン領域３３まで延在しておらず、中央のドレイン領域７２のみをガードした長さとなっている点で、実施例２に係る半導体装置１０１と異なっている。 In the semiconductor device 102 according to the third embodiment, the current concentration relaxation electrodes 72 do not extend to the drain regions 33 at both ends in the longitudinal direction of the semiconductor device 102 and have a length that guards only the central drain region 72. This is different from the semiconductor device 101 according to the second embodiment.
　　しかしながら、実施例３に係る半導体装置１０２は、電流集中緩和電極７２が、ドレイン領域７２の延在方向の端部よりも外側の、端部と基板電極８０との間に設けられている点では、実施例１及び実施例２に係る半導体装置１００、１０１と共通する。 However, in the semiconductor device 102 according to the third embodiment, the current concentration relaxation electrode 72 is provided between the end portion and the substrate electrode 80 outside the end portion in the extending direction of the drain region 72. The semiconductor devices 100 and 101 according to the first and second embodiments are common.
　　図８において説明したように、逆流電流Ｉ３が集中して問題が発生するのは、両側がゲート４０で挟まれ、基板電極８０と対向していないドレイン領域３２の両端部のみである。よって、電流集中緩和電極７２は、図６に示すように、ドレイン領域３２の両端部のみをガードする長さの構成であってもよい。この場合、電流集中緩和電極７２は、ドレイン領域３２と基板電極８０の間に、複数のコンタクトホール７７を有して配置されていれば、逆流電流Ｉ３の集中を低減する効果を有するが、あまり短いと、横から流れ込む逆流電流Ｉ３をガードできないので、ドレイン領域３２の幅よりも長さ又は幅が大きいことが好ましい。更に好ましくは、電流集中緩和電極７２は、ドレイン領域３２を挟む２つのゲート４０の間隔よりも長さ又は幅が大きければ、十分に逆流電流Ｉ３の集中を防ぐことができる。 As described with reference to FIG. 8, the backflow current I3 is concentrated and the problem occurs only at both ends of the drain region 32 sandwiched between the gates 40 on both sides and not facing the substrate electrode 80. Therefore, as shown in FIG. 6, the current concentration relaxation electrode 72 may have a length that guards only both ends of the drain region 32. In this case, if the current concentration relaxation electrode 72 has a plurality of contact holes 77 between the drain region 32 and the substrate electrode 80, the current concentration relaxation electrode 72 has an effect of reducing the concentration of the backflow current I3. If the length is short, the backflow current I3 flowing from the side cannot be guarded, so that the length or width is preferably larger than the width of the drain region 32. More preferably, if the length or width of the current concentration relaxation electrode 72 is larger than the distance between the two gates 40 sandwiching the drain region 32, the concentration of the backflow current I3 can be sufficiently prevented.
　　また、実施例３においては、電流集中緩和電極７２の長さ又は幅が小さいので、電流集中緩和電極７２が、ドレイン領域３２の延在方向の延長線上に確実に存在するように配置することが好ましい。 In the third embodiment, since the length or width of the current concentration relaxation electrode 72 is small, the current concentration relaxation electrode 72 may be disposed so as to be surely present on the extension line in the extending direction of the drain region 32. preferable.
　　なお、電流集中緩和電極７２の上に、コンタクトホール７７が密に形成されている点は、実施例１及び実施例２に係る半導体装置１００、１０１と同様である。 Note that the contact holes 77 are densely formed on the current concentration relaxation electrode 72 as in the semiconductor devices 100 and 101 according to the first and second embodiments.
　　また、実施例３に係る半導体装置１０２の半導体基板１０の上層の配線層は、実施例２に係る配線層１５１と同様のパターンの配線層を用いることができる。なお、配線層のパターンは、実施例２の配線層１５１のパターンに限るものではなく、ドレイン領域３２、３３のコンタクトホール３７、３８と、電流集中緩和電極７２のコンタクトホール７７を、同一のドレイン配線層で接続できれば、種々の配線パターンで構成することができる。 Also, the wiring layer having the same pattern as the wiring layer 151 according to the second embodiment can be used as the upper wiring layer of the semiconductor substrate 10 of the semiconductor device 102 according to the third embodiment. Note that the pattern of the wiring layer is not limited to the pattern of the wiring layer 151 of the second embodiment, and the contact holes 37 and 38 of the drain regions 32 and 33 and the contact hole 77 of the current concentration relaxation electrode 72 are formed in the same drain. If it can be connected in the wiring layer, it can be configured with various wiring patterns.
　　以上、本発明の好ましい実施例について詳説したが、本発明は、上述した実施例に制限されることはなく、本発明の範囲を逸脱することなく、上述した実施例に種々の変形及び置換を加えることができる。特に、本実施例においては、半導体装置が、ｎチャネルＬＤＭＯＳとして構成されている例を挙げて説明したが、ｐチャネルＬＤＭＯＳとして構成されている場合にも、同様に本発明を適用することができる。 The preferred embodiments of the present invention have been described in detail above. However, the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the present invention. Can be added. In particular, in this embodiment, the example in which the semiconductor device is configured as an n-channel LDMOS has been described. However, the present invention can be similarly applied to a case where the semiconductor device is configured as a p-channel LDMOS. .
　本国際出願は２００９年１２月２５日に出願された日本国特許出願２００９－２９３７７３号に基づく優先権を主張するものであり、日本国特許出願２００９－２９３７７３号の全内容をここに本国際出願に援用する。 This international application claims priority based on Japanese Patent Application No. 2009-293773 filed on Dec. 25, 2009. The entire contents of Japanese Patent Application No. 2009-293773 are hereby filed here. Incorporated into.
　　本発明は、ＬＤＭＯＳを含む半導体装置に利用することができる。 The present invention can be used for a semiconductor device including an LDMOS.
　　１０　　半導体基板
　１５　　ｎ層
　２０　　ソース領域
　２５、３５、３６、３７、３８、５５、８５　　コンタクトホール
　３０、３１、３２、３３　　ドレイン領域
　４０　　ゲート
　５０　　バックゲート領域
　６０　　ＬＯＣＯＳ
　７０、７１、７２　　電流集中緩和電極
　８０　　基板電極
　９０　　酸化膜
　１００、１０１、１０２　　半導体装置
　１１０、１１１　　ソース配線層
　１２０、１２１　　ドレイン配線層
　１３０、１３１　　基板電極配線層
　１５０、１５１　　配線層 DESCRIPTION OF SYMBOLS 10 Semiconductor substrate 15 N layer 20 Source region 25, 35, 36, 37, 38, 55, 85 Contact hole 30, 31, 32, 33 Drain region 40 Gate 50 Back gate region 60 LOCOS
70, 71, 72 Current concentration relaxation electrode 80 Substrate electrode 90 Oxide film 100, 101, 102 Semiconductor device 110, 111 Source wiring layer 120, 121 Drain wiring layer 130, 131 Substrate electrode wiring layer 150, 151 wiring layer

Claims (6)

  1. 　半導体基板の表面領域に形成され、対向して延在するソース領域及びドレイン領域と、前記半導体基板の表面上に形成され、前記ソース領域及びドレイン領域の間で前記ソース領域に沿って延在するゲートとを含む複数のトランジスタセルと、前記複数のトランジスタセルの周囲を囲み、前記半導体基板の基準電位を定める基板電極とを備えた半導体装置において、
    　前記半導体基板の表面領域の、前記ゲートに両側を挟まれた前記ドレイン領域の延在方向における端部と、前記基板電極との間の前記ドレイン領域の延長線上に、前記ドレイン領域と同電位の電流集中緩和電極が設けられたことを特徴とする半導体装置。     A source region and a drain region that are formed in a surface region of the semiconductor substrate and extend opposite to each other, and a surface that is formed on the surface of the semiconductor substrate and extends along the source region between the source region and the drain region. In a semiconductor device comprising: a plurality of transistor cells including gates; and a substrate electrode that surrounds the plurality of transistor cells and defines a reference potential of the semiconductor substrate.
    The surface region of the semiconductor substrate has the same potential as the drain region on the extension line of the drain region between the end of the drain region sandwiched between the gates in the extending direction and the substrate electrode. A semiconductor device comprising a current concentration relaxation electrode.
  2. 　前記電流集中緩和電極は、前記ドレイン領域の幅方向において、前記ドレイン領域の幅よりも長さ又は幅が長いことを特徴とする請求項１に記載の半導体装置。 2. The semiconductor device according to claim 1, wherein the current concentration relaxation electrode has a length or a width longer than a width of the drain region in a width direction of the drain region.
  3. 　前記電流集中緩和電極は、配線層により前記ドレイン領域と電気的に接続されていることを特徴とする請求項１に記載の半導体装置。 2. The semiconductor device according to claim 1, wherein the current concentration relaxation electrode is electrically connected to the drain region by a wiring layer.
  4. 　前記電流集中緩和電極は、前記ドレイン領域と連続的に前記半導体基板の表面領域に設けられたことを特徴とする請求項３に記載の半導体装置。 4. The semiconductor device according to claim 3, wherein the current concentration relaxation electrode is provided in a surface region of the semiconductor substrate continuously with the drain region.
  5. 　前記電流集中緩和電極は、総ての前記ドレイン領域と連続的に前記半導体基板の表面領域に設けられ、前記ドレイン領域と前記電流集中緩和電極とで、前記ゲート及び前記ソース領域を平面的に囲むことを特徴とする請求項４に記載の半導体装置。 The current concentration relaxation electrode is provided in the surface region of the semiconductor substrate continuously with all the drain regions, and the drain region and the current concentration relaxation electrode surround the gate and the source region in a plane. The semiconductor device according to claim 4.
  6. 　前記ドレイン領域は、ｎ型拡散層から構成され、
    　前記基板電極は、ｐ型拡散層から構成され、
    　前記電流集中緩和電極は、ｎ型拡散層から構成されていることを特徴とする請求項１に記載の半導体装置。     The drain region is composed of an n-type diffusion layer,
    The substrate electrode is composed of a p-type diffusion layer,
    The semiconductor device according to claim 1, wherein the current concentration relaxation electrode includes an n-type diffusion layer.
PCT/JP2010/071884 2009-12-25 2010-12-07 Semiconductor device WO2011077940A1 (en)

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0410474A (en) * 1990-04-26 1992-01-14 Fuji Electric Co Ltd Semiconductor device with mix type field-effect transistor
JPH11154732A (en) * 1997-11-20 1999-06-08 Nec Corp Protecting circuit of semiconductor integrated circuit against static electricity and manufacture thereof
JP2002164441A (en) * 2000-11-27 2002-06-07 Matsushita Electric Ind Co Ltd High frequency switch circuit device
JP2005191151A (en) * 2003-12-24 2005-07-14 Nec Electronics Corp Electrostatic discharge protection element
JP2006286800A (en) * 2005-03-31 2006-10-19 Ricoh Co Ltd Semiconductor device
JP2009130099A (en) * 2007-11-22 2009-06-11 Oki Engineering Kk High breakdown voltage mos transistor device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0410474A (en) * 1990-04-26 1992-01-14 Fuji Electric Co Ltd Semiconductor device with mix type field-effect transistor
JPH11154732A (en) * 1997-11-20 1999-06-08 Nec Corp Protecting circuit of semiconductor integrated circuit against static electricity and manufacture thereof
JP2002164441A (en) * 2000-11-27 2002-06-07 Matsushita Electric Ind Co Ltd High frequency switch circuit device
JP2005191151A (en) * 2003-12-24 2005-07-14 Nec Electronics Corp Electrostatic discharge protection element
JP2006286800A (en) * 2005-03-31 2006-10-19 Ricoh Co Ltd Semiconductor device
JP2009130099A (en) * 2007-11-22 2009-06-11 Oki Engineering Kk High breakdown voltage mos transistor device

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