JP2009130099A - High breakdown voltage mos transistor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enlarge an amount of the maximum current which a drain wiring can conduct, by making a width of the drain wiring larger than before. <P>SOLUTION: A high breakdown voltage MOS transistor device 10 is formed in a P-well region 103 provided in a substrate 102 and has a breakdown voltage between a source and a drain beyond 20 V. Region parts between sources 104a, 104b and a drain 108 in the P-well region include a conductive film preventing a conductive type from being inverted in response to an effect of an external electric field. This conductive film is continuously integrated with gate electrodes 120a, 120b as a belt shaped layer 12. When a surface of the substrate 102 is superficially seen, the belt shaped layer 12 is provided by surrounding one or both of the source and the drain. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a high voltage MOS transistor device capable of suppressing a leakage current between a source and a drain.

  In the semiconductor device formed on the main surface of the substrate, an inversion layer in which the conductivity type of the substrate in the vicinity of the main surface is inverted may be formed due to the influence of an external electric field derived from the wiring layer provided above the main surface. is there. This inversion layer may cause a leak between the semiconductor devices.

  In order to prevent the formation of an inversion layer due to the influence of an external electric field, a technique of providing a conductive layer between a wiring layer and a main surface of a substrate is disclosed (for example, see Patent Document 1). In the technique of Patent Document 1, by applying a predetermined bias voltage to this conductive layer, an external electric field derived from the wiring layer is shielded and the formation of the inversion layer is prevented.

  As an application example of the technique disclosed in Patent Document 1, for example, a high voltage MOS transistor device as shown in FIGS. 7 to 9 is known. Here, FIG. 7 is a plan view schematically showing the structure of the high voltage MOS transistor device. FIG. 8 is a plan view schematically showing the structure of the high voltage MOS transistor device excluding the interlayer insulating film and the wiring on the interlayer insulating film. FIG. 9A is an end view schematically showing a cut surface along the line AA in FIG. FIG. 9B is an end view schematically showing a cut surface along the line BB in FIG.

  7 to 9, the transistor device 101 includes two high voltage MOS transistors (hereinafter also simply referred to as “transistors”) 100a and 100b. The transistor device 101 is formed on a P-type substrate 102.

  More specifically, the transistors 100 a and 100 b are formed in a P-well region 103 having a rectangular planar shape formed near the surface of the substrate 102. The transistor 100a includes one drain 108, a source 104a, and a gate 106a that are used in common for both the transistors 100a and 100b. Similarly, the transistor 100b includes one drain 108, a source 104b, and a gate 106b that are used in common for both the transistors 100a and 100b.

  The P well region 103 is a region having a higher concentration of P-type impurities than the substrate 102. A field oxide film 118 is formed on the surface of the P well region 103.

  More specifically, the field oxide film 118 includes regions where gate oxide films 122a and 122b described later are formed, a high concentration N-type region 112 of the drain 108, and high concentration N-type regions 128a and 128b of the sources 104a and 104b. It is formed in the surface region of the P well region 103 excluding.

  The guard ring 110 is a belt-like body formed with a higher concentration of P-type impurities than the P well region 103, and is provided along the inner periphery of the P well region 103.

  A plurality of contacts 136, 136,... Are connected to the guard ring 110. The guard ring 110 is connected to the guard ring wiring 138 through these contacts 136, 136,... Through the interlayer insulating film 105 provided on the surface side of the substrate 102.

  The guard ring wiring 138 has a shape substantially corresponding to the guard ring 110. That is, the guard ring wiring 138 is formed so as to surround the P well region 103 except for the drain wiring 116 and the gate wirings 126a and 126b described later. Further, the guard ring wiring 138 is provided with metal covers 140a and 140b described in detail later.

  The drain 108 is a region having a rectangular planar shape, which is formed almost at the center of the P well region 103. The drain 108 is formed of a high concentration N-type region 112 and low concentration N-type regions 114a and 114b.

  The high-concentration N-type region 112 is a region whose conductivity type is N-type. A plurality of contacts 113, 113,... Are connected to the high concentration N-type region 112. The high-concentration N-type region 112 is connected to the drain wiring 116 provided above the substrate 102 in the thickness direction via these contacts 113, 113,. The drain wiring 116 is drawn outside the P well region 103 from the break of the guard ring wiring 138.

  The low-concentration N-type regions 114a and 114b are regions having an N-type impurity concentration lower than that of the high-concentration N-type region 112, and surround the high-concentration N-type region 112 and extend in the gate length direction. The low-concentration N-type regions 114a and 114b are provided to alleviate electric field concentration at the end of the drain 108. A field oxide film 118 is formed in contact with the low-concentration N-type regions 114a and 114b above the low-concentration N-type regions 114a and 114b, respectively.

  Gates 106a and 106b include gate electrodes 120a and 120b and gate oxide films 122a and 122b, respectively. The gates 106 a and 106 b are symmetrically arranged in the P well region 103 with the drain 108 interposed therebetween.

  As is well known, the gate electrodes 120a and 120b are formed using polysilicon as a material, and are formed longer than the gate width in the gate width direction. One end in the longitudinal direction of the gate electrodes 120a and 120b penetrates through the interlayer insulating film 105 provided on the entire surface of the substrate 102 via the contacts 124a and 124b, and the gate wirings 126a and 126b. Each is connected. The gate wirings 126 a and 126 b are led out of the P well region 103 from the break of the guard ring wiring 138.

  The sources 104a and 104b are symmetrically arranged outside the gates 106a and 106b with the drain 108 interposed therebetween in the P well region 103. The sources 104a and 104b are regions having a rectangular planar shape. The source 104a is formed of high-concentration N-type regions 128a and 128b and low-concentration N-type regions 130a and 130b. The source 104b is formed of a high concentration N-type region 128b and low concentration N-type regions 130b and 130b.

  The high-concentration N-type regions 128a and 128b are regions whose conductivity type is N-type. A plurality of contacts 132, 132,... Are connected to the high concentration N-type regions 128a and 128b. The high concentration N-type regions 128 a and 128 b are connected to the guard ring wiring 138 through the interlayer insulating film 105 through these contacts 132 and 132.

  The low-concentration N-type regions 130a and 130b are regions having a lower N-type impurity concentration than the high-concentration N-type regions 128a and 128b, and surround the high-concentration N-type regions 128a and 128b and extend in the gate length direction. Yes. A field oxide film 118 is formed in contact with the low-concentration N-type region 130 above the low-concentration N-type regions 130a and 130b.

  Here, the metal covers 140a and 140b will be described in more detail with reference to FIG. The metal covers 140 a and 140 b are formed as protruding portions in which the guard ring wiring 138 protrudes inside the P well region 103. When viewed from the surface side of the substrate 102, the metal covers 140a and 140b are formed so as to overlap the gate electrodes 120a and 120b, respectively (regions sandwiched by broken lines in the figure).

  The metal covers 140a and 140b have a function of preventing the formation of an inversion layer in the P well region 103 due to the influence of an external electric field in combination with the gate electrodes 120a and 120b and the gate wirings 126a and 126b.

  That is, the metal covers 140 a and 140 b shield the external electric field and prevent the external electric field from being directly applied to the surface of the P well region 103. Accordingly, the generation of the inversion layer is suppressed, and the leak that occurs between the sources 104a and 104b and the drain 108 through the inversion layer is prevented.

  However, in this technique, as is apparent from the drawing, the drain wiring 116 is restricted by the width W of the gap between the gate wirings 126a and 126b. That is, the drain wiring 116 could not be made larger than the width W. As a result, it has been difficult to increase the maximum amount of current that can conduct the drain wiring 116.

As a technique for preventing leakage between the source and the drain, a technique is known in which the periphery of the drain is surrounded by a gate electrode without interruption (see, for example, Patent Document 2).
However, in the technique disclosed in Patent Document 2, electric field concentration occurs at the four corners of the rectangular drain, and it is difficult to sufficiently increase the voltage resistance of the transistor.
JP 2000-31898 A JP 9-134966 A

  As a result of intensive studies, the inventors of the high voltage MOS transistor device provided that a high voltage MOS transistor device can be obtained by providing a strip layer made of a conductive film surrounding one or both of the source and drain in cooperation with the gate electrode. The inventors have conceived that leakage between the source and the drain can be prevented without impairing the voltage resistance of the device.

Therefore, the object of the present invention is to
(1) Without sacrificing voltage tolerance
(2) Prevent leakage current between source and drain,
(3) An object of the present invention is to provide a high voltage MOS transistor device capable of increasing the width of the drain wiring as compared with the prior art and increasing the maximum amount of current capable of conducting the drain wiring.

  In order to achieve the above object, a high voltage MOS transistor device of the present invention is formed in one conductivity type well region provided on a substrate and has a source-drain breakdown voltage of 20 V or more. ing.

  The region between the source and the drain in the well region includes a conductive film that prevents the conductivity type from being inverted by the influence of an external electric field. The conductive film includes a gate electrode, a gate, It includes an electrode and a continuously formed portion, and is formed as a strip layer as a whole.

  When the surface of the substrate is viewed in plan, the belt-like layer is provided so as to surround one or both of the source and the drain.

  Here, a portion formed continuously with the gate electrode is preferably a shielding wiring.

  Moreover, it is preferable that the belt-like layer is provided with a first shielding wiring and a second shielding wiring as described below.

  The first shielding wiring includes a gate electrode and a shielding wiring integrally formed with the gate electrode, and when the surface of the substrate is viewed in plan view, one or both of the source and drain are formed in a C shape. Is enclosed.

  The second shielding wiring is a metal ring having a height different from that of the guard ring wiring surrounding the well region and the first shielding wiring when the surface of the substrate is viewed in plan, and extends from the guard ring wiring. When the surface of the substrate is viewed in plan, the metal cover overlapping the first shielding wiring, and the gate wiring having a height different from that of the first shielding wiring and supplying a voltage to the gate electrode, It is preferable to include.

  According to the high voltage MOS transistor device of the present invention, (1) the leakage between the source and the drain is prevented without impairing the voltage resistance, and (3) the width of the drain wiring is made larger than before. The maximum amount of current that can conduct the drain wiring can be increased.

  Embodiments of the present invention will be described below with reference to the drawings. In addition, each figure showing the cross section of a component is only what showed roughly to such an extent that this invention can understand the shape, size, and arrangement | positioning relationship of each component. Moreover, although the preferable structural example of this invention is demonstrated below, the material, numerical condition, etc. of each component are only a preferable example. Therefore, the present invention is not limited to the following embodiment.

(Embodiment 1)
The high voltage MOS transistor device of the first embodiment will be described with reference to FIGS. FIG. 1 is a plan view schematically showing the structure of a high voltage MOS transistor device. FIG. 2 is a plan view schematically showing the structure of the high voltage MOS transistor device in which the interlayer insulating film and the wiring on the interlayer insulating film are removed from the components shown in FIG. FIG. 3 is an end view schematically showing a cut surface along the line AA in FIG. 1. In FIG. 1 to FIG. 3, the same reference numerals are given to the same components as those in the prior art shown in FIG. 7 to FIG. 9, and the description thereof is omitted unless necessary.

(Construction)
First, the structure of the high voltage MOS transistor device 10 of the first embodiment will be described. Hereinafter, the “high voltage MOS transistor device” may be simply referred to as “transistor device”.

  The high breakdown voltage MOS transistor device 10 has a source-drain breakdown voltage of 20 V or more, and is formed in one conductivity type region provided on the substrate 102, for example, a P well region 103. The transistor device 10 illustrated in this embodiment is of a dual gate type including one common drain 108 and sources 104a and 104b provided on both sides thereof.

  A region between the sources 104a and 104b and the drain 108 in the P well region 103 is provided with a conductive film 12 that prevents the conductivity type from being inverted to the other conductivity type due to the influence of an external electric field. Yes.

  The conductive film 12 is formed as a strip layer including the gate electrodes 120a and 120b. Further, the strip layer 12 is provided above the surface of the substrate 102, that is, above one well-type well region, here the P-well region 103. The band-shaped layer 12 may be provided so as to surround one or both of the sources 104a and 104b and the drain 108 when the surface of the substrate 102 is viewed in plan view. The example of a structure which enclosed is shown.

  Although FIG. 1 is not a cross-sectional view, the belt-like layer 12 is shown with hatching in order to emphasize the component region, and the hatching density is increased particularly in the gate electrodes 120a and 120b. It is shown.

  In this embodiment, the part formed integrally with the gate electrodes 120 a and 120 b of the strip layer 12 is the shielding wiring 14. The width of the shielding wiring 14 may be a suitable width depending on the design.

  As apparent from a comparison between the configuration of the prior art shown in FIGS. 7 and 8 and the configuration of the embodiment shown in FIGS. 1 and 2, the transistor device 10 of this embodiment has the following two points. Is different from the prior art transistor device 101.

 (1) The gate electrodes 120a and 120b are connected via the shielding wirings 14a and 14b, and the gate electrodes 120a and 120b are integrated so as to surround the drain 108.

 (2) The metal rings 140 a and 140 b are not provided on the guard ring wiring 16.

  Hereinafter, the difference from the conventional transistor device 101 will be mainly described.

  In the transistor device 10 of this embodiment, the shielding wiring 14a is formed integrally with the gate electrode 120a so as to surround the gate electrode 120a, and the shielding wiring 14b is surrounded around the gate electrode 120b. As described above, the gate electrodes 120b are integrally formed, but the connecting portions of the shielding wirings 14a and 14b with the gate electrodes 120a and 120b are made to have the same width in the gate length direction of the gate electrodes 120a and 120b. Thus, the gate electrodes 120a and 120b may be configured not to be formed integrally with the sides on the source and drain sides.

  In any case, the gate electrode 120a and the gate electrode 120b are connected by the shielding wiring 14a. Similarly, the gate electrode 120a and the gate electrode 120b are connected by a shielding wiring 14b.

  The shielding wirings 14a and 14b are formed simultaneously with the gate electrodes 120a and 120b by patterning the conductive film as the strip layer 12 in the step of forming the gate electrodes 120a and 120b. Therefore, the shielding wirings 14a and 14b are made of a conductive material, that is, polysilicon, like the gate electrodes 120a and 120b.

  As apparent from the cut end view shown in FIG. 3, the shielding wires 14 a and 14 b are formed on the field oxide film 118 covering the P well region 103.

  Further, the shielding wiring 14a is provided with a terminal portion 14c projecting to the side of the source 104a of the transistor 100a on the field oxide film 118 (FIGS. 1 and 2). The terminal portion 14 c is connected to the gate wiring 18 extending on the interlayer insulating film 105 toward the outside of the P well region 103 and contacts 20, 20,... Provided through the interlayer insulating film 105. It is connected.

  Thus, when the surface of the substrate 102 is viewed in a plan view with the gate electrodes 120a and 120b and the shielding wirings 14a and 14b, the belt 108 continuously surrounds the drain 108 in a rectangular shape over a round. 12 is formed.

  Further, in the transistor device 10, the conventional metal cover is not provided in the guard ring wiring 16 in contrast to the structure in which the metal covers 140 a and 140 b are provided in the guard ring wiring 138 in the conventional transistor device 101 (FIG. 1, FIG. 7 and FIG. 9 (B)). The reason for this will be described in detail in the description of the action.

(Function)
Next, the operation of the transistor device 10, in particular, the strip layer 12 will be described. A desired gate voltage is applied to the strip layer 12 surrounding the drain 108 via the terminal portion 14c. As a result, the gate electrodes 120a and 120b constituting the strip layer 12 control the on / off of the transistors 100a and 100b depending on the gate voltage.

  The shielding wires 14a and 14b of the strip layer 12 function differently from the gate electrodes 120a and 120b. Specifically, since the shielding wirings 14a and 14b are formed of a conductive material, the shielding wirings 14a and 14b function to shield the influence of an external electric field on the region below the shielding wirings 14a and 14b.

  That is, for example, when the transistor device 10 has a structure in which the shielding wirings 14a and 14b are not provided, when the wiring provided above the transistor device 10 is charged to a high potential (for example, 20 V or more), the wiring is generated from the wiring. An electric field (external electric field) may invert the P conductivity type near the surface of the P well region 103 to the N conductivity type.

  Thus, when the inversion layer is formed by inverting the conductivity type, even if the transistors 100a and 100b are in the off state, that is, the voltage is not applied to the gate electrodes 120a and 120b, the inversion layer is formed. As a result, a leak current flows between the source and the drain.

  However, according to the configuration of this embodiment, an external electric field is prevented from being directly applied to the surface of the P well region 103 due to the shielding effect of the shielding wirings 14 a and 14 b provided above the P well region 103. Is done. Therefore, the conductivity type of the P well region 103 immediately below the shielding wirings 14a and 14b is not reversed, and a conduction path is not formed between the source and the drain. Therefore, the leak path between the source and the drain is blocked.

(effect)
Next, the effect of the transistor device 10 of this embodiment will be described.

  (1) In the transistor device 10 according to this embodiment, the conventional metal covers 140a and 140b are not provided on the guard ring wiring 16 (see FIGS. 7 and 9B). As a result, it is possible to increase the width of the drain wiring 116, that is, the length in the gate length direction, which has been conventionally regulated by the distance between the metal covers 140a and 140b. As a result, the maximum amount of current that can be conducted through the drain wiring 116 of the drain wiring 116 can be increased, and the surge resistance can be improved.

  (2) In the transistor device 10 of this embodiment, the drain 108 is surrounded by the belt-like layer 12 composed of the shielding wirings 14a and 14b and the gate electrodes 120a and 120b. Accordingly, for example, it is possible to prevent a leakage path including an inversion layer from being formed between the source and the drain due to the influence of an external electric field from a wiring layer charged at a high potential provided above the transistor device 10. it can.

  (3) Unlike the prior art described in Patent Document 2, in the transistor device 10 of this embodiment, the electric field does not concentrate at the four corners of the drain 108. As a result, the voltage tolerance of the transistor device 10 can be increased as compared with the technique of Patent Document 2.

(Embodiment 2)
Next, the configuration of the second embodiment of the transistor device 10 of this embodiment will be described.

  In the first embodiment, the case where the strip 12 is provided so as to surround the drain 108 has been described. However, the strips may be provided so as to individually surround each of the sources 104a and 104b. By doing so as well, a leakage current between the source and the drain can be prevented.

  A high voltage MOS transistor device according to the second embodiment will be described with reference to FIGS. FIG. 4 is a plan view schematically showing the structure of the high voltage MOS transistor device. FIG. 5 is a plan view schematically showing the structure of the high voltage MOS transistor device in which the interlayer insulating film and the wiring on the interlayer insulating film are removed from the components shown in FIG. FIG. 6 is an end view schematically showing a cut surface along the line AA of FIG. 4 to 6, the same components as those in the prior art shown in FIGS. 7 to 9 are denoted by the same reference numerals, and the description thereof is omitted unless necessary.

(Construction)
First, the structure of the high voltage MOS transistor device 30 of the second embodiment will be described.

  In this embodiment, the belt-like layer 32 includes first shielding wirings 36a and 36b and second shielding wirings 40a and 40b.

  One first shielding wiring 36a includes a gate electrode 120a and shielding wirings 34a and 34b formed integrally with the gate electrode 120a. The shielding wirings 34a and 34b can be formed in a C shape so as to surround one or both of the source 104a and the drain 108 when the surface of the substrate 102 is viewed in plan.

  The other first shielding wiring 36b includes a gate electrode 120b and shielding wirings 34c and 34d formed integrally with the gate electrode 120b. The shielding wirings 34c and 34d can be formed in a C shape so as to surround one or both of the source 104b and the drain 108 when the surface of the substrate 102 is viewed in plan.

  In the configuration example shown in FIGS. 4 and 5, the first shielding wirings 36a and 36b are formed so as to surround the sources 104a and 104b, respectively.

  The second shielding wirings 40a and 40b include a guard ring wiring 38, metal covers 140a and 140b, and gate wirings 126a and 126b, respectively.

  The guard ring wiring 38 is formed on the interlayer insulating film 105 so as to surround the P well region 103 when the surface of the substrate 102 is viewed in plan.

  The metal covers 140a and 140b are formed on the interlayer insulating film 105 so as to extend from the guard ring wiring 38 at different heights from the first shielding wirings 36a and 36b, respectively, and the surface of the substrate 102 is planar. When viewed from the top, it is provided so as to overlap with the first shielding wires 36a and 36b, that is, to overlap from above.

  The gate wirings 126a and 126b are provided on the interlayer insulating film 105 so as to extend to the gate voltage supply source side. These gate lines 126a and 126b supply voltage to the gate electrodes 120a and 120b.

  Hereinafter, the transistor device 30 will be described focusing on differences from the transistor device 10 of the first embodiment described above.

  As shown in FIG. 5, one first shielding wiring 36a constituting the strip layer 32 includes a gate electrode 120a and shielding wirings 34a and 34b. The first shielding wiring 36a has a C-shaped planar shape and is formed so as to surround one long side and two short sides of one rectangular source 104a.

  More specifically, as in the case of the first embodiment, the shielding wiring 34a is formed integrally with the gate electrode 120a so as to surround the gate electrode 120a, and both are connected. The shielding wiring 34a extends along one short side of the source 104a on the one end 120a1 side in the gate width direction of the gate electrode 120a.

  As shown in FIG. 5, contacts 20a, 20a, 20a are provided on the shielding wiring 34a. These contacts 20 a, 20 a, 20 a are connected to a gate wiring 126 a extending on the interlayer insulating film 105 toward the outside of the P well region 103. As a result, a desired gate voltage is supplied to the gate electrode 120a from the gate wiring 126a via the contacts 20a, 20a, and 20a.

  Further, the other shielding wire 34b is connected to the other end portion 120a2 in the gate width direction of the gate electrode 120a in the same manner as the one shielding wire 34a. The shielding wiring 34b extends along the other short side of the source 104a.

  The shielding wirings 34a and 34b are formed simultaneously with the gate electrode 120a in the step of forming the gate electrode 120a, similarly to the shielding wiring described in the first embodiment. Therefore, the shielding wirings 34a and 34b are made of a conductive material, that is, polysilicon, like the gate electrode 120a.

  Similarly, the other first shielding wiring 36b constituting the strip layer 32 includes a gate electrode 120b and shielding wirings 34c and 34d. The first shielding wiring 36b has a C-shaped planar shape and is formed so as to surround one long side and two short sides of the other rectangular source 104b.

  The first shielding wiring 36b is arranged symmetrically with respect to the first shielding wiring 36a and the drain 108. Therefore, description of the details of the structure of the first shielding wiring 36b is omitted.

  As shown in FIG. 4, one second shielding wiring 40a constituting the strip layer 32 includes a metal cover 140a, a guard ring wiring 38, and a gate wiring 126a.

  The metal cover 140a extends from the guard ring wiring 38 provided on the interlayer insulating film 105 above the P well region 103 toward the inside of the source 104a. Referring to FIG. 6, the metal cover 140 a and the first shielding wiring 36 a overlap each other through the interlayer insulating film 105. That is, when viewed from the front side of the substrate 102, the metal cover 140a and the first shielding wiring 36a (shielding wiring 34b) overlap each other.

  As described in the section of the prior art, the guard ring wiring 38 is provided along the inner periphery of the P well region 103.

  As described in the first embodiment, the gate wiring 126a is connected to one shielding wiring 34a formed integrally with the gate electrode 120a through the contacts 20a, 20a, and 20a.

  With these components, the planar shape of one of the second shielding wires 40a is formed in a C shape with the opening facing away from one of the first shielding wires 36a, and surrounds one source 104a. Is provided.

  The other second shielding wiring 40b constituting the belt-like layer 32 includes the other metal cover 140b, the guard ring wiring 38, and the other gate wiring 126b.

  The other second shielding wiring line 40b is arranged symmetrically with respect to the one second shielding wiring line 40a and the drain. Therefore, description of the details of the structure of the other second shielding wiring 40b is omitted.

(Function)
Next, the operation of the transistor device 30, particularly the strip layer 32 will be described.

  The metal covers 140a and 140b of the strip layer 32 and the first shielding wirings 36a and 36b serve to shield the influence of the external electric field.

  That is, for example, when a wiring provided above the transistor device 30 is charged to a high potential, the electric field (external electric field) generated from this wiring causes the conductivity type of the region near the surface of the P-well region 103 to be opposite to the conductivity type. It may reverse to the mold.

  When the inversion layer having the inverted conductivity type is formed in this way, even if the transistors 100a and 100b are in an off state, that is, no voltage is applied to the gate electrodes 120a and 120b, the inversion layer is interposed between the inversion layers. As a result, a conduction path between the source and the drain is formed, so that a leakage current flows between the source and the drain.

  The metal covers 140 a and 140 b and the first shielding wirings 36 a and 36 b provided above the P well region 103 have an external electric field directly on the surface of the P well region 103 for the same reason as already described in the first embodiment. Prevents being applied. Then, the conductivity type of the P well region 103 immediately below the first shielding wirings 36a and 36b is prevented from being inverted. That is, the leak path between the source and drain is blocked.

(effect)
Next, the effect of the transistor device 30 of this embodiment will be described.

  (1) In the transistor device 30 of this embodiment, the gate wirings 126a and 126b are connected not to the gate electrodes 120a and 120b but to the shielding wirings 34a and 34c having a larger interval than the gate electrodes 120a and 120b, respectively. Yes. Further, the metal covers 140a and 140b are also connected to the shielding wirings 34b and 34d having a wider interval than the gate electrodes 120a and 120b, not the gate electrodes 120a and 120b.

  As a result, the width (length in the gate length direction) of the drain wiring 116 that has been conventionally regulated by the distance between the metal covers 140a and 140b can be increased. As a result, the maximum amount of current that can be conducted through the drain wiring 116 of the drain wiring 116 can be increased, and the surge resistance can be improved.

  (2) In the transistor device 30 of this embodiment, the drain 108 is surrounded by the belt-like layer 32 composed of the first shielding wirings 36a and 36b and the second shielding wirings 40a and 40b. Accordingly, for example, it is possible to prevent a leakage path including an inversion layer from being formed between the source and the drain due to the influence of an external electric field from a wiring layer charged at a high potential provided above the transistor device 10. it can.

  (3) Unlike the prior art described in Patent Document 2, in the transistor device 10 of this embodiment, the electric field does not concentrate at the four corners of the drain 108. As a result, the voltage tolerance of the transistor device 10 can be increased as compared with the technique of Patent Document 2.

1 is a plan view schematically showing the structure of a high voltage MOS transistor device according to a first embodiment. 1 is a plan view schematically showing a structure of a high voltage MOS transistor device of Embodiment 1 excluding an interlayer insulating film and wiring on the interlayer insulating film. These are the end views which show typically the cut surface along the AA line of FIG. FIG. 6 is a plan view schematically showing the structure of a high voltage MOS transistor device according to a second embodiment. FIG. 10 is a plan view schematically showing the structure of the high voltage MOS transistor device of the second embodiment excluding an interlayer insulating film and wiring on the interlayer insulating film. It is an end elevation which shows typically the cut surface along the AA line of FIG. It is a top view which shows typically the structure of the high voltage MOS transistor device of a prior art. It is a top view which shows typically the structure of the high voltage | pressure-resistant MOS transistor device of a prior art except the interlayer insulation film and the wiring on an interlayer insulation film. FIG. 8A is an end view schematically showing a cut surface along the line AA in FIG. 7. FIG. 8B is an end view schematically showing a cut surface along the line BB in FIG.

Explanation of symbols

10, 30 High voltage MOS transistor devices 12, 32 Strip layers 14a, 14b Shielding wiring 16, 38 Guard ring wiring 18 Gate wirings 20, 20a, 20b Contacts 34a, 34b, 34c, 34d Shielding wiring 36a, 36b First shielding Wiring 40a, 40b Second shielding wiring

Claims (3)

A high voltage MOS transistor device having a source-drain breakdown voltage of 20 V or more formed in a well region of one conductivity type provided on a substrate,
A region portion between the source and drain in the well region includes a conductive film that prevents the conductivity type from reversing to another conductivity type under the influence of an external electric field,
The conductive film includes a gate electrode and a portion formed continuously with the gate electrode, and is formed as a strip layer as a whole, and when the surface of the substrate is viewed in plan view, A high breakdown voltage MOS transistor device, wherein the belt-like layer is provided so as to surround one or both of the source and drain.   2. The high breakdown voltage MOS transistor device according to claim 1, wherein a portion continuously formed with the gate electrode is used as a shielding wiring. The belt-like layer includes a first shielding wiring and a second shielding wiring;
The first shielding wiring includes the gate electrode and a shielding wiring integrally formed with the gate electrode, and the source and drain are formed in a C shape when the surface of the substrate is viewed in a plan view. And the second shielding wiring includes a guard ring wiring that surrounds the well region when the surface of the substrate is viewed in a plane.
A metal cover having a height different from that of the first shielding wiring, the metal cover extending from the guard ring wiring and overlapping the first shielding wiring when the surface of the substrate is viewed in a plane. When,
2. The high breakdown voltage MOS transistor device according to claim 1, further comprising: a gate wiring that is different in height from the first shielding wiring and supplies a voltage to the gate electrode.

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