JP2009071173A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having an ESD protection element having sufficient discharge capability. <P>SOLUTION: Disclosed is the semiconductor device having the ESD protection element on a substrate 130, and the ESD protection element 100 has a p-type well region 101 formed on the substrate 130, an element isolation region 109 formed in the p-type well region 101, an n-type ESD protection transistor 120 formed on an active region 140 enclosed with the element isolation region 109, a p-type guard ring region 106 formed on the p-type well region 101 and enclosing the active region 140 with the element isolation region 109 interposed, and an n-type cathode region 107 formed on the p-type well region 101 and between the active region 140 and p-type guard ring region 106. The element isolation region 109 is formed between the n-type cathode region 107 and active region 140. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device including an electrostatic discharge (ESD) protection element.

  2. Description of the Related Art In recent years, semiconductor devices have been highly integrated in accordance with miniaturization and high density of elements, and accordingly, semiconductors are protected against damage caused by electrostatic discharge (hereinafter referred to as “surge”). The device is weak. For example, a surge entering from an external connection terminal destroys elements such as an input circuit, an output circuit, and an internal circuit, and there is a high possibility that the performance of the element is deteriorated. Therefore, the semiconductor device is provided with an electrostatic discharge (ESD) protection element connected to the external connection terminal in order to protect the input circuit, output circuit, input / output circuit or internal circuit from surge (for example, Patent Document 1).

  Hereinafter, a conventional semiconductor device including an ESD protection element will be described with reference to FIGS. FIG. 5A is a plan view showing a configuration of a conventional ESD protection element, and FIG. 5B is a cross-sectional view taken along the line Vb-Vb shown in FIG.

  As shown in FIGS. 5A and 5B, the conventional ESD protection element 50 includes a p-type well region 1 formed in the substrate 15, and an element isolation region 9 formed in the p-type well region 1. The n-type MIS transistor 60 formed in the p-type well region 1 and on the active region 30 made of the substrate 15 surrounded by the element isolation region 9 and the p-type well region 1 in the substrate 15 are formed. The p-type guard ring region 6 surrounding the active region 30 with the element isolation region 9 interposed therebetween. Note that the outer surface of the p-type guard ring region 6 is also surrounded by the element isolation region 9. The p-type guard ring region 6 is a region serving as a lead portion of the p-type well region 1 and has a higher impurity concentration and a lower resistance value than the p-type well region 1.

  Here, the n-type MIS transistor 60 includes a first gate insulating film 2a and a second gate insulating film 2b formed on the active region 30, and a first gate insulating film 2a and a second gate insulating film 2b. The first gate electrode 3a and the second gate electrode 3b respectively formed on the n-type drain region 4 and the n-type drain region 4 formed between the first gate electrode 3a and the second gate electrode 3b in the active region 30. A first n-type source region 5a formed in a region on the side of the active region 30 opposite to the n-type drain region 4 on the side of the first gate electrode 3a; And a second n-type source region 5b formed in a region on the side opposite to the n-type drain region 4 and on the side opposite to the n-type drain region 4.

  The conventional ESD protection element 50 includes a contact plug 8 and a first metal wiring 10 connected to the n-type drain region 4, a first n-type source region 5a, a second n-type source region 5b, and A contact plug 8 and a second metal wiring 11 connected to the p-type guard ring region 6 are provided. Here, the n-type drain region 4 is connected to an external connection pad 12 such as an input / output terminal via a contact plug 8 and a first metal wiring 10. On the other hand, the first n-type source region 5a, the second n-type source region 5b, and the p-type guard ring region 6 are, for example, a ground terminal or a power supply terminal via the contact plug 8 and the second metal wiring 11. Are connected to the reference voltage terminal 13. Although illustration is omitted, an interlayer insulating film is formed between the substrate 15 and the first metal wiring 10 and the second metal wiring 11, and the contact plug 8 penetrates the interlayer insulating film. Is formed.

In the conventional ESD protection element 50 having the above-described configuration, when a surge enters from the input / output terminal (external connection pad 12) connected to the n-type drain region 4, in the case of a surge of one polarity, the n-type drain region 4, a parasitic bipolar transistor including the first n-type source region 5a or the second n-type source region 5b, the p-type well region 1 and the p-type guard ring region 6 operates. In the case of the other polarity surge, a parasitic diode composed of the n-type drain region 4, the p-type well region 1 and the p-type guard ring region 6 operates. By operating the parasitic bipolar transistor or the parasitic diode in this way, a surge that has entered from the outside can be released to the reference voltage terminal 13 and the internal circuit can be protected from the surge.
JP-A-11-274404

  In order to ensure a high ESD tolerance (electrostatic discharge tolerance) of a semiconductor device, for example, an amperage-order current capability or a low-impedance operation is performed for a surge with an application time of several hundred ns or less. It is necessary to provide an ESD protection element having a high discharge capability.

  However, in the conventional ESD protection element 50, in the parasitic diode composed of the n-type drain region 4, the p-type well region 1 and the p-type guard ring region 6, the n-type drain region 4 and the p-type well region 1 Since the distance from the junction position to the p-type guard ring region 6 is long, the parasitic resistance is increased by the p-type well region 1. For this reason, when a surge enters, as a result of an increase in impedance, the discharge capability is reduced.

  In view of the above problems, an object of the present invention is to provide a semiconductor device including an ESD protection element having sufficient discharge capability even when miniaturized.

  In order to achieve the above object, a semiconductor device according to the present invention is a semiconductor device including an ESD protection element on a substrate, and the ESD protection element is a first conductivity type well region formed in the substrate. An element isolation region formed in the well region; and a second conductivity type MIS transistor formed in the well region and on the active region made of the substrate surrounded by the element isolation region; A guard ring region of a first conductivity type formed on the well region of the substrate and surrounding the active region across the element isolation region; and formed on the well region of the substrate, the active region and the A second conductivity type first impurity region formed between the guard ring region and the active region with the element isolation region interposed therebetween is provided.

  According to this configuration, since the first impurity region into which the same conductivity type impurity as that of the MIS transistor is introduced is formed between the active region and the guard ring region, for example, a surge has entered from the input / output terminal. In this case, a diode (first diode) composed of the first impurity region, the well region, and the guard ring region can be operated. In the first diode, since the first impurity region is formed in the vicinity of the guard ring region, for example, than the diode composed of the impurity region provided in the MIS transistor, the well region, and the guard ring region. The parasitic resistance due to the well region is reduced. As a result, since the ESD protection element provided in the semiconductor device of the present invention has a sufficiently small parasitic resistance, the discharge capability can be improved as compared with the conventional ESD protection element. Therefore, the semiconductor device of the present invention includes an ESD protection element having sufficient discharge capability even when miniaturized, and can suppress a surge from damaging an internal circuit, thereby realizing a highly reliable semiconductor device. be able to.

  According to the semiconductor device of the present invention, since the ESD protection element having sufficient discharge capability is provided, the internal circuit is not easily damaged by a surge even when miniaturized, and the reliability of the semiconductor device can be improved. it can.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings for a semiconductor device including an ESD protection element. In each embodiment of the present invention, components having substantially the same function are denoted by the same reference numerals.

(First embodiment)
FIG. 1A is a plan view showing a configuration of an ESD protection element provided in the semiconductor device according to the first embodiment of the present invention, and FIG. 1B is an Ib− shown in FIG. It is sectional drawing in the Ib line.

  As shown in FIGS. 1A and 1B, an ESD protection element 100 according to this embodiment includes a substrate 130 made of silicon or the like, and a p-type (first conductivity type) well region formed in the substrate 130. 101, an element isolation region 109 formed in the p-type well region 101, and an n region formed in the p-type well region 101 on the active region 140 made of the substrate 130 surrounded by the element isolation region 109. Type (second conductivity type) ESD protection transistor 120, p-type guard ring region 106 formed on p-type well region 101 in substrate 130 and surrounding active region 140 with element isolation region 109 interposed therebetween, and p in substrate 130 An element isolation region 109 is formed on the type well region 101 and between the active region 140 and the p-type guard ring region 106 and between the active region 140. And an n-type cathode region 107 formed Nde. The p-type guard ring region 106 is a region to be a lead portion of the p-type well region 101 and has a higher impurity concentration and a lower resistance value than the p-type well region 101.

  The n-type ESD protection transistor 120 is formed on the first gate insulating film 102a and the second gate insulating film 102b formed on the active region 140, and on the first gate insulating film 102a and the second gate insulating film 102b. A first gate electrode 103a and a second gate electrode 103b respectively formed on the active region 140; an n-type drain region 104 formed between the first gate electrode 103a and the second gate electrode 103b in the active region 140; A first n-type source region 105a formed in a region on the side of the first gate electrode 103a in the active region 140 and on the opposite side of the n-type drain region 104, and a second in the active region 140 A second n-type source region 10 formed in a region on the side of the gate electrode 103b and opposite to the n-type drain region 104. And a and b.

  Here, the n-type cathode region 107 is provided to extend in the gate width direction at a position facing the side surface on the first n-type source region 105a side among the side surfaces located in the gate length direction in the active region 140. And is surrounded by an element isolation region 109. The outer surface of the p-type guard ring region 106 (the side surface opposite to the n-type cathode region 107) is also surrounded by the element isolation region 109.

  In addition, the ESD protection element 100 of the present embodiment includes a contact plug 108 and a first metal wiring 110 connected to the n-type drain region 104 and the n-type cathode region 107, a first n-type source region 105a, and a second n-type source region 105a. Contact plug 108 connected to the n-type source region 105 b, p-type guard ring region 106, and a second metal wiring 111. Here, the n-type drain region 104 and the n-type cathode region 107 are connected to an external connection pad 112 such as an input / output terminal through a contact plug 108 and a first metal wiring 110. On the other hand, the first n-type source region 105a, the second n-type source region 105b, and the p-type guard ring region 106 are, for example, a ground terminal or a power supply terminal via the contact plug 108 and the second metal wiring 111. The reference voltage terminal 113 is connected. Although illustration is omitted, an interlayer insulating film is formed between the substrate 130 and the first metal wiring 110 and the second metal wiring 111, and each contact plug 108 penetrates the interlayer insulating film. Is formed.

The p-type well region 101 is formed by ion-implanting p-type impurity ions at a dose in the range of 1 × 10 ¹² to 1 × 10 ¹³ ions / cm ⁻² , for example. The n-type drain region 104, the first n-type source region 105a, the second n-type source region 105b, and the n-type cathode region 107 are, for example, 1 × 10 ¹⁵ to 4 × 10 ¹⁵ ions / cm ⁻² . The n-type impurity ions are ion-implanted with a dose amount within a range. Furthermore, the p-type guard ring region 106 is formed by ion implantation of p-type impurity ions at, for example, 1 × 10 ¹⁵ to 4 × 10 ¹⁵ ions / cm ⁻² .

  In the ESD protection element 100 provided in the semiconductor device of this embodiment, when a positive voltage surge enters from the external connection pad 112, for example, the n-type drain region 104, the p-type well region 101, and the first n-type A parasitic bipolar transistor composed of the source region 105a or the second n-type source region 105b operates. Specifically, when a positive voltage surge flows from the external connection pad 112, the current flows to the n-type drain region 104 through the first metal wiring 110 and the contact plug 108, and then the p-type well region 101, It flows out to the reference voltage terminal 113 (ground terminal) via the first n-type source region 105a or the second n-type source region 105b.

  On the other hand, when a negative voltage surge, for example, enters from the external connection pad 112, a parasitic diode (first parasitic diode) composed of the n-type cathode region 107, the p-type well region 101, and the p-type guard ring region 106; The parasitic diode (second diode) constituted by the n-type drain region 104, the p-type well region 101, and the p-type guard ring region 106 operates. Specifically, in the first parasitic diode, when a negative voltage surge flows from the external connection pad 112, the current flows through the p-type guard ring region 106 and the p-type well region 101, and flows through the n-type cathode region 107. After passing through, it flows out to the external connection pad 112 through the contact plug 108 and the first metal wiring 110. In this case, most of the current passes through the parasitic resistance R <b> 1 formed of the p-type well region 101 located between the p-type guard ring region 106 and the n-type cathode region 107. In the second parasitic diode, when a negative voltage surge entering from the external connection pad 112 flows, the current flows through the p-type guard ring region 106 and the p-type well region 101 and passes through the n-type drain region 104. After that, it flows out to the external connection pad 112 through the contact plug 108 and the first metal wiring 110. Accordingly, a part of the current passes through the parasitic resistance R 2 formed of the p-type well region 101 located between the p-type guard ring region 106 and the n-type drain region 104.

  In the semiconductor device of the present embodiment, the distance between the n-type cathode region 107 and the p-type guard ring region 106 is shorter than the distance between the n-type drain region 104 and the p-type guard ring region 106, The parasitic resistance R1 due to the formed p-type well region 101 is smaller than the parasitic resistance R2. Thereby, since the parasitic resistance as the whole ESD protection element 100 can be made small compared with the conventional ESD protection element, the discharge capability of a surge can be improved. The conventional ESD protection element diode has a discharge capacity of, for example, 2.0 A, whereas the ESD protection element 100 diode provided in the semiconductor device of the present embodiment has a discharge capacity of 3.0 A. It was found that the battery has a higher discharge capacity than before.

  As described above, the semiconductor device of the present embodiment is characterized by the n-type cathode region in which the same conductivity type impurity as that of the n-type drain region 104 is introduced between the active region 140 and the p-type guard ring region 106. 107 is formed. According to this configuration, when a surge enters from an external circuit, the n-type drain region 104, the p-type well region 101 and the p-type guard ring region 106 are used together with the n-type parasitic diode (second parasitic diode). The first parasitic diode, which includes the cathode region 107, the p-type well region 101, and the p-type guard ring region 106 and has a parasitic resistance smaller than that of the second parasitic diode, is also conducted. As a result, a surge can be released using a diode having a parasitic resistance smaller than that of a conventional ESD protection element, so that sufficient current capability can be exhibited and operation with low impedance is possible. As a result, the semiconductor device of this embodiment includes an ESD protection element having sufficient discharge capability even when miniaturized, and can suppress damage to the internal circuit due to an ESD surge.

  Further, in the semiconductor device of the present embodiment, the side surface of the n-type cathode region 107 is larger than the width of the side surface of the active region 140 facing the n-type cathode region 107. As described above, since the n-type cathode region 107 has a sufficient area, the discharge capability of the ESD protection element 100 can be improved.

  In the ESD protection element of the present invention, the first conductivity type is n-type and the second conductivity type is p-type. However, the present invention is not limited to this, and the first conductivity type is p-type and the second conductivity type. May be n-type.

  Hereinafter, first to third modifications of the semiconductor device of this embodiment will be described.

(First modification of the first embodiment)
FIG. 2A is a plan view showing a configuration of a first modification (ESD protection element 200) of the ESD protection element according to the first embodiment, and FIG. 2B is a plan view of FIG. It is sectional drawing in the IIb-IIb line shown. Note that the ESD protection element 200 of the present modification is different from the ESD protection element 100 of the first embodiment only in a part of the configuration, and thus the same configuration will be omitted.

  As shown in FIGS. 2A and 2B, in the ESD protection element 200 of the present modification, the n-type cathode region 107 includes the first n-th region between the active region 140 and the p-type guard ring region 106. It is formed not only in the region located beside the type source region 105a but also in the region located beside the second n-type source region 105b. In other words, the n-type cathode region 107 is formed to extend in the gate width direction at positions facing both side surfaces of the active region 140 located in the gate length direction. Each n-type cathode region 107 formed in the two regions is surrounded by an element isolation region 109.

  In the ESD protection element 200 of the present modification, the n-type cathode region 107 is formed in two regions, so that a parasitic structure composed of the n-type cathode region 107, the p-type well region 101, and the p-type guard ring region 106 is formed. Diodes (first diodes) can be formed on both sides of the active region 140 in the gate length direction. Therefore, for example, when a negative voltage surge enters from the external connection pad 112, the current is a parasitic diode (second diode) composed of the n-type drain region 104, the p-type well region 101, and the p-type guard ring region 106. At the same time, the current flows to the external connection pad 112 via the first diodes formed on both sides of the active region 140. Here, the parasitic resistance R1 of the first diode is smaller than the parasitic resistance R2 of the second diode. Therefore, the parasitic resistance of the entire ESD protection element 200 of the present modification in which the first diode can be formed in two regions is further smaller than the parasitic resistance of the entire ESD protection element 100 of the first embodiment. Therefore, when the ESD protection element 200 of the present modification is provided, the discharge capability can be further improved, so that the internal circuit can be prevented from being damaged by a surge, and a highly reliable semiconductor device is realized. be able to.

(Second modification of the first embodiment)
FIG. 3A is a plan view showing a configuration of a second modified example (ESD protection element 300) of the ESD protection element according to the first embodiment, and FIG. 3B is a plan view of FIG. It is sectional drawing in the IIIb-IIIb line shown. Note that the ESD protection element 300 of the present modification is different from the ESD protection element 100 of the first embodiment only in a part of the configuration, and therefore the same configuration will be omitted and described.

  As shown in FIGS. 3A and 3B, in the ESD protection element 300 of this modification, the n-type cathode region 107 is formed so as to surround the active region 140. According to this configuration, a parasitic diode (first parasitic diode) that includes the n-type cathode region 107, the p-type well region 101, and the p-type guard ring region 106 and has a sufficiently small parasitic resistance R <b> 1 is formed in the active region 140. Therefore, the resistance of the entire ESD protection element 300 can be further reduced. As a result, the semiconductor device including the ESD protection element 300 according to the present modification has sufficient discharge capability even when miniaturized, and can more reliably suppress damage to the internal circuit due to surge. Become.

(Second Embodiment)
FIG. 4A is a plan view showing the configuration of the ESD protection element provided in the semiconductor device according to the second embodiment of the present invention, and FIG. 4B is an IVb− shown in FIG. It is sectional drawing in the IVb line. Note that the ESD protection element 400 according to the present embodiment is different from the ESD protection element 100 of the first embodiment only in a part of the configuration, and thus the same configuration is omitted.

  As shown in FIGS. 4A and 4B, in the ESD protection element 400 according to the present embodiment, the n-type cathode region 107 is formed in the active region 140 as in the ESD protection element 100 of the first embodiment. Among the side surfaces located in the gate length direction, the first n-type source region 105a is provided so as to extend in the gate width direction at a position facing the side surface on the first n-type source region 105a side.

  Here, the ESD protection element 400 according to the present embodiment is characterized in that the n-type cathode region 107 and the p-type guard ring region 106 are not partitioned by the element isolation region 109, and a p-type well region is provided between them. 101 exists. According to this configuration, the n-type cathode region 107 and the p-type guard ring region 106 are compared with the case where the element isolation region 109 is formed between the n-type cathode region 107 and the p-type guard ring region 106. Since the distance is further shortened, the parasitic resistance of the parasitic diode composed of the n-type cathode region 107, the p-type well region 101, and the p-type guard ring region 106 can be further reduced. As a result, even when a surge is applied to the external connection pad 112, the ESD protection element 400 having sufficiently low parasitic resistance and high discharge capability operates, so that the internal circuit can be more reliably protected from the surge. it can.

  In the ESD protection element 400 of the present embodiment, the p-type well region 101 is formed between the n-type cathode region 107 and the p-type guard ring region 106. However, it is not always necessary to interpose the p-type well region 101. Alternatively, the n-type cathode region 107 and the p-type guard ring region 106 may be formed in contact with each other. In this case, for example, when a negative voltage surge enters from the external connection pad 112, most of the current flowing through the p-type guard ring region 106 flows through the n-type cathode region 107 without passing through the p-type well region 101. After that, it flows out to the external connection pad 112. Thereby, since the surge can be released without passing through the parasitic resistance due to the p-type well region 101, the discharge capacity can be further improved.

  Furthermore, in the ESD protection element 400 of the present embodiment, the position of the n-type cathode region 107 is not limited to the position shown in FIG. For example, as in the first and second modifications of the first embodiment, the n-type cathode region 107 is provided at a position facing both side surfaces of the active region 140 positioned in the gate length direction. Alternatively, it may be formed so as to surround the active region 140. Even in these cases, the same effects as those of the first modification and the second modification of the first embodiment can be obtained.

  The semiconductor device of the present invention is useful for miniaturization and high integration of a semiconductor device.

(A) is a top view which shows the structure of the ESD protection element 100 with which the semiconductor device which concerns on the 1st Embodiment of this invention was equipped, (b) is sectional drawing in the Ib-Ib line | wire shown to (a) It is. (A) is a top view which shows the 1st modification of the ESD protection element which concerns on 1st Embodiment, (b) is sectional drawing in the IIb-IIb line | wire shown to (a). (A) is a top view which shows the 2nd modification of the ESD protection element which concerns on 1st Embodiment, (b) is sectional drawing in the IIIb-IIIb line | wire shown to (a). (A) is a top view which shows the structure of the ESD protection element which concerns on the 2nd Embodiment of this invention, (b) is sectional drawing in the IVb-IVb line | wire shown to (a). (A) is a top view which shows the structure of the conventional ESD protection element, (b) is sectional drawing in the Vb-Vb line | wire shown to (a).

Explanation of symbols

100, 200, 300, 400 ESD protection element
101 p-type well region
102a First gate insulating film
102b Second gate insulating film
103a first gate electrode
103b Second gate electrode
104 n-type drain region
105a First n-type source region
105b Second n-type source region
106 p-type guard ring region
107 n-type cathode region
108 Contact plug
109 Element isolation region
110 First metal wiring
111 Second metal wiring
112 Pad for external connection
113 Reference voltage terminal
120 n-type ESD protection transistor
130 substrates
140 Active region
160 p-type guard ring region

Claims (12)

A semiconductor device having an ESD protection element on a substrate,
The ESD protection element is
A first conductivity type well region formed in the substrate;
An element isolation region formed in the well region;
A MIS transistor of a second conductivity type formed in an active region made of the substrate in the well region and surrounded by the element isolation region;
A guard ring region of a first conductivity type formed on the well region of the substrate and surrounding the active region across the element isolation region;
A first impurity of a second conductivity type formed on the well region of the substrate and formed between the active region and the guard ring region with the element isolation region interposed between the active region and the active region; And a semiconductor device.   The semiconductor device according to claim 1, wherein the element isolation region is formed between the first impurity region and the guard ring region.   The semiconductor device according to claim 1, wherein the first impurity region is surrounded by the element isolation region.   The semiconductor device according to claim 1, wherein the well region is formed in contact with the first impurity region and the guard ring region.   The semiconductor device according to claim 1, wherein the first impurity region and the guard ring region are formed in contact with each other.   The semiconductor device according to claim 1, wherein the first impurity region is formed at a position facing at least one side surface of the active region.   The semiconductor according to claim 1, wherein the first impurity region is formed at a position facing at least one side surface of both side surfaces located in the gate length direction in the active region. apparatus.   The semiconductor device according to claim 1, wherein the first impurity region is formed so as to surround the active region.   9. The semiconductor device according to claim 1, wherein the first impurity region is formed such that a width of a side surface facing the first impurity region is larger than that of the active region.   The semiconductor device according to claim 1, wherein an outer surface of the guard ring region is surrounded by the element isolation region. The MIS transistor is
A gate insulating film formed on the active region;
A gate electrode formed on the gate insulating film;
A second impurity region of a second conductivity type formed below one side of the gate electrode in the active region;
The semiconductor device according to claim 1, further comprising: a third impurity region of a second conductivity type formed below the other side of the gate electrode in the active region. The first impurity region and the second impurity region are connected to an input / output terminal,
The semiconductor device according to claim 11, wherein the guard ring region and the third impurity region are connected to a ground terminal or a power supply terminal.

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