JP6941502B2 - Semiconductor devices and semiconductor packages - Google Patents

Description

The present invention relates to semiconductor devices and semiconductor packages.

Conventionally, a JFET (Junction gate Field Effect Transistor) is known as a normalion type semiconductor element. For example, Patent Document 1 discloses a SiC-JFET used in combination with a MOSFET.
Further, Patent Document 2 discloses a semiconductor package including a semiconductor chip, a stage on which the semiconductor chip is mounted, a gate lead, a source lead, a drain lead, a bonding wire, and a sealing resin.

Japanese Unexamined Patent Publication No. 2011-166673 Japanese Unexamined Patent Publication No. 2014-123665

In the normalization type JFET, the current flowing through the semiconductor layer is cut off by the depletion layer that spreads in the semiconductor layer by applying a voltage. Appropriately designing the spread width of the depletion layer ensures a reliable interruption of current. Therefore, in the JFET, the spread width of the depletion layer must be considered preferentially, and as a result of lowering the impurity concentration (channel concentration) of the semiconductor layer, the resistance per unit length is relatively high. Further, there is a depletion type MOSFET as a normalion type semiconductor element, but the same reason that the depletion layer spread width is preferentially considered hinders the reduction of the resistance of the semiconductor layer.

Against this background, in JFETs and depletion-type MOSFETs, it is necessary to secure a large current path in order to reduce the on-resistance. Therefore, it is difficult to reduce the size of the element and use it.
An object of the present invention is to provide a semiconductor device and a semiconductor package which are normalion type and can reduce the size of a device.

Further, as in Patent Document 2, various semiconductor packages have been conventionally proposed, but in the future, with the demand for wearable terminals, smaller transistors will be required.
Another object of the present invention is to provide a semiconductor device that is significantly smaller than the conventional one.

The semiconductor device according to the embodiment of the present invention is common to the enhancement type first p-channel type MISFET, the enhancement type second p-channel type MISFET, the first p-channel type MISFET, and the drain of the second p-channel type MISFET. An electrically connected drain conductor, a first source conductor electrically connected to the source of the first p-channel type MISFET, and a second electrically connected to the source of the second p-channel type MISFET. It includes a source conductor and a gate conductor commonly electrically connected to the gates of the first p-channel MISFET and the second p-channel MISFET.

In this semiconductor device, a voltage is applied between (between S ₁ -S ₂₎ of the first source conductor in a state in which a voltage to the gate conductor G is not applied to S ₁ and the second source conductor S ₂ Then, both MISFETs are turned on via the parasitic diodes (internal diodes) of the first p-channel type MISFET and the second p-channel type MISFET. As a result, a current can flow between _{S 1 and} S _2. On the other hand, when a positive voltage is applied to the gate conductor G, the potential difference VGS _{1 between the gate conductor G and the first source conductor S 1} approaches 0, and finally the first source conductor G. The current between S ₁ and the second source conductor S ₂ is cut off. Thus, while between S ₁ -S ₂ is conductive when a voltage is not applied to the gate conductor G, and between S ₁ -S ₂ enters a cutoff state when a voltage is applied to the gate conductor G. That is, normalion operation is realized. Further, in the first and second p-channel type MISFETs that turn on and off the current in this semiconductor device, unlike the JFET and the depletion type MISFET, the spread of the depletion layer is not used for turning on and off the current. Therefore, it is not necessary to design the impurity concentration of the semiconductor layer in consideration of the depletion layer, so that a low resistance value can be maintained even if the size is reduced.

A semiconductor device according to an embodiment of the present invention includes a semiconductor layer having a common p-type drain region with respect to the first p-channel type MISFET and the second p-channel type MISFET, and the first p-channel type MISFET is the semiconductor layer. A first gate electrode facing the first n-type body region, a first p-type source region formed on the surface of the first n-type body region, and a first gate electrode facing the first n-type body region. The second p-channel type MISFET is formed in a second n-type body region formed on the surface portion of the semiconductor layer, a second p-type source region formed on the surface portion of the second n-type body region, and the second n-type body region. The second gate electrode is included, the drain conductor is formed on the back surface of the semiconductor layer, and the drain electrode is connected to the p-type drain region, and the first source conductor is the first p-type. The second source electrode includes a first source electrode connected to the source region, the second source conductor is disposed separately from the first source electrode, and includes a second source electrode connected to the second p-type source region. The gate conductor may include a gate wiring commonly connected to the first gate electrode and the second gate electrode in the semiconductor layer.

According to this configuration, the first p-channel type MISFET and the second p-channel type MISFET can be integrated into one chip, so that a smaller semiconductor device can be provided.
In the semiconductor device according to the embodiment of the present invention, the semiconductor layer is for the first active region for the first p-channel type MISFET and for the second p-channel type MISFET arranged adjacent to the first active region. The gate wiring may be provided in an area between the first active area and the second active area, including the second active area of the above.

The semiconductor device according to the embodiment of the present invention includes a first gate trench formed directly under the first active region, a second gate trench formed directly under the second active region, and the first gate. The first gate electrode includes a third gate trench formed between the trench and the second gate trench and connecting the first gate trench and the second gate trench in common, and the first gate electrode is the first gate. The second gate electrode may include an electrode embedded in the trench, the second gate electrode may include an electrode embedded in the second gate trench, and the gate wiring may include an electrode embedded in the third gate trench. ..

The semiconductor device according to the embodiment of the present invention includes a first gate trench formed directly under the first active region and a second gate trench formed directly under the second active region, and the first gate trench is included. The 1-gate electrode includes an electrode embedded in the 1st gate trench, the 2nd gate electrode includes an electrode embedded in the 2nd gate trench, and the gate wiring is in a region on the semiconductor layer. An electrode formed, straddling the first gate electrode and the second gate electrode along the surface of the semiconductor layer, and connected from above to each of the first gate electrode and the second gate electrode is included. You may.

In the semiconductor device according to the embodiment of the present invention, in the region between the first active region and the second active region, the region on the back surface side of the semiconductor layer with respect to the front surface portion of the semiconductor layer is common. It may be occupied by the p-type drain region of.
In the semiconductor device according to the embodiment of the present invention, the gate wiring includes one gate pad and a gate finger connected to the gate pad and surrounding the first active region and the second active region. The 1-source electrode and the 2nd source electrode may be arranged in a region separated from each other by the gate finger.

The semiconductor device according to the embodiment of the present invention includes a linear first unit cell sequence composed of a plurality of first unit cells of the first p-channel type MISFET, and a plurality of second units of the second p-channel type MISFET. The first unit cell row and the second unit cell row include a linear second unit cell row composed of unit cells, and the first unit cell row and the second unit cell row are alternately arranged at intervals from each other. The second source electrode is formed in a comb-teeth shape having a base end portion on one end side of the first unit cell row and the second unit cell row and having a tooth portion on each of the first unit cell rows. The first source electrode having a base end portion on the other end side of the first unit cell row and the second unit cell row, having a tooth portion on each of the second unit cell rows, and having a comb-shaped first source electrode. It may be formed in the shape of comb teeth that mesh with each other at intervals.

In the semiconductor device according to the embodiment of the present invention, the plurality of first unit cells of the first p-channel type MISFET and the plurality of second unit cells of the second p-channel type MISFET are arranged in a matrix as a whole. The plurality of first unit cells and the plurality of second unit cells may be arranged alternately in the row direction and the column direction, respectively.
The semiconductor package according to the embodiment of the present invention includes the semiconductor device according to the embodiment of the present invention and a sealing resin that seals all or a part of the semiconductor device.

According to this configuration, since the semiconductor device according to the embodiment of the present invention is provided, it is possible to provide a semiconductor package that is a normalion type and can reduce the size of the device.
A semiconductor device according to an embodiment of the present invention includes a semiconductor substrate having a rectangular shape in a plan view having a front surface, a back surface opposite to the front surface, and a side surface between the front surface and the back surface, and at least the front surface. A surface insulating film formed on the semiconductor substrate so as to cover the semiconductor substrate, and both ends of the first peripheral edge portion at the center of the first peripheral edge portion along the side surface of one of the semiconductor substrates on the surface side of the semiconductor substrate. A first pad arranged at a distance from a corner portion, a second pad arranged at one corner of a second peripheral edge portion facing the first peripheral edge portion of the semiconductor substrate, and the first pad of the semiconductor substrate. 2 Includes a third pad arranged at the other end corner of the peripheral edge.

As a comparative form different from this configuration, if the first pad is arranged at the corner of the first peripheral edge or the first pad is formed in a size extending to both corners, the first pad and the first pad are different. The distance between the two pads and the distance between the first pad and the third pad are substantially the same as the length of the side along the side surface of the semiconductor substrate, respectively. In such a form, if the size of the semiconductor substrate (the length of the side of the semiconductor substrate) becomes smaller as the semiconductor device becomes smaller, the distance between the pads becomes shorter, and there is a possibility of a short circuit after mounting.

On the other hand, in the above configuration, the first pad is arranged at the center of the first peripheral edge of the semiconductor substrate having a rectangular shape in a plan view at intervals from the corners at both ends of the first peripheral edge. Therefore, the distance between the first pad and the second pad and the distance between the first pad and the third pad can be made relatively long. Therefore, the size of the semiconductor substrate can be made smaller than that of the above-mentioned comparative embodiment while avoiding a short circuit at the time of mounting. This makes it possible to provide a miniaturized semiconductor device.

In the semiconductor device according to the embodiment of the present invention, the semiconductor substrate includes a rectangular semiconductor substrate in a plan view, and the first peripheral edge portion and the second peripheral edge portion are peripheral portions along the longitudinal direction of the semiconductor substrate. May include.
According to this configuration, the second pad and the third pad are arranged at one end corner and the other end corner of the second peripheral edge along the longitudinal direction, respectively, so that the distance between the second pad and the third pad is Can also be relatively long.

In the semiconductor device according to the embodiment of the present invention, a first arc centered on the apex of one end corner of the second peripheral edge portion and a radius of the short side of the semiconductor substrate, and the second peripheral edge portion. When a second arc centered on the apex of the other end corner of the semiconductor substrate and a radius of the short side of the semiconductor substrate is drawn on the surface of the semiconductor substrate, the first pad is the first arc. It may be the outer region of the second arc and may be arranged in the outer region of the second arc.

According to this configuration, as the distance between the first pad and the second pad and the distance between the first pad and the third pad, at least the length of the short side of the semiconductor device and the size of the second pad and the third pad ( It is possible to secure a length corresponding to the difference from the width). That is, the semiconductor device can be miniaturized by the size of the first pad while maintaining the distance between the first pad and the second pad and the distance between the first pad and the third pad in the above comparative embodiment. ..

In the semiconductor device according to the embodiment of the present invention, the first arc and the second arc have a size at which the first arc and the second arc intersect each other in a region on the semiconductor substrate, and the first pad is the first arc and the second arc. It may be formed in a triangular shape having a pair of tangents drawn from the intersection with the second arc with respect to each of the first arc and the second arc as two sides.
According to this configuration, the first pad can be formed by making maximum use of the space in the outer region of the first arc and the second arc. As a result, it is possible to secure a sufficient bonding area for the first pad while reducing the size of the semiconductor device.

In the semiconductor device according to the embodiment of the present invention, the second pad may be formed in a fan shape having the same center as the first arc.
According to this configuration, the distance between the first pad and the second pad is the first while ensuring at least a length corresponding to the difference between the length of the short side of the semiconductor device and the size (width) of the second pad. A sufficient joint area can be secured for the two pads.

In the semiconductor device according to the embodiment of the present invention, the third pad may be formed in a fan shape having the same center as the second arc.
According to this configuration, the distance between the first pad and the third pad is the first, while ensuring at least a length corresponding to the difference between the length of the short side of the semiconductor device and the size (width) of the third pad. A sufficient joint area can be secured for the three pads.

The semiconductor device according to an embodiment of the present invention includes a MIS transistor structure formed on the semiconductor substrate, and the first pad includes a drain pad electrically connected to a drain of the MIS transistor structure. The second pad may include a source pad electrically connected to the source of the MIS transistor structure, and the third pad may include a gate pad electrically connected to the gate of the MIS transistor structure. ..

In the semiconductor device according to the embodiment of the present invention, the semiconductor substrate includes an active region in which the MIS transistor structure is formed, and the MIS transistor structure is in a direction from the first peripheral edge portion to the second peripheral edge portion. A first interlayer film formed on the semiconductor substrate so as to cover the source region and the drain region, including a plurality of alternately arranged source regions and drain regions, and the active It is formed on the first interlayer film so as to cover approximately half of the region on the second peripheral edge side, and is electrically connected to the source region at the end of the source region on the second peripheral edge side. The first source wiring layer is formed on the first interlayer film so as to cover substantially half of the active region on the first peripheral edge side, and the end portion of the drain region on the first peripheral edge side. May further include a first drain wiring layer electrically connected to the drain region.

According to this configuration, the first source wiring layer and the first drain wiring layer are each formed in a size that covers substantially half of the active region. As a result, a wide current path between the source and the drain can be secured. Therefore, it is possible to suppress an increase in the on-resistance of the MIS transistor while reducing the size of the semiconductor device.
The semiconductor device according to the embodiment of the present invention includes a second interlayer film formed on the first interlayer film so as to cover the first source wiring layer and the first drain wiring layer, and the active region. It is formed on the second interlayer film so as to cover substantially half of the area on the second peripheral edge side, and is electrically connected to the first source wiring layer, and a part thereof is surface-insulated as the source pad. It is formed on the second interlayer film so as to cover the second source wiring layer exposed from the film and approximately half of the area on the first peripheral edge side of the active region, and is electrically formed on the first drain wiring layer. It is connected, and a part thereof may include a second drain wiring layer exposed from the surface insulating film as the drain pad.

According to this configuration, the second source wiring layer and the second drain wiring layer are each formed in a size that covers substantially half of the active region. As a result, a wide current path between the source and the drain can be secured. Therefore, it is possible to suppress an increase in the on-resistance of the MIS transistor while reducing the size of the semiconductor device.
In the semiconductor device according to the embodiment of the present invention, the semiconductor substrate is formed on the protection diode region outside the active region and the second interlayer film so as to cover the protection diode region, and a part thereof is described. The gate pad may further include a gate wiring layer exposed from the surface insulating film.

In the semiconductor device according to the embodiment of the present invention, the surface insulating film may be further formed so as to cover the side surface of the semiconductor substrate.
According to this configuration, when the semiconductor device is mounted at high density, it is possible to prevent a short circuit between the semiconductor device and the adjacent semiconductor device.
The semiconductor device according to the embodiment of the present invention may have a chip size package structure.

In the semiconductor device according to the embodiment of the present invention, the chip size package structure may include a long side of less than 0.50 mm and a short side of less than 0.40 mm.
With this configuration, it is possible to provide the smallest semiconductor device ever.
In the semiconductor device according to the embodiment of the present invention, the chip size package structure may be formed with a thickness of less than 0.15 mm.

If the thickness of the chip size package structure is within the above range, the amount of protrusion of the side surface of the semiconductor device from the normal position can be reduced even if the semiconductor device is mounted at an angle. As a result, even when the semiconductor device is mounted at high density, contact with the adjacent semiconductor device can be suppressed.
In the semiconductor device according to the embodiment of the present invention, the distance between the first pad, the second pad, and the third pad may be 50% or more of the short side of the semiconductor substrate.

FIG. 1 is a schematic configuration diagram of a semiconductor package according to an embodiment of the present invention. FIG. 2 is a cross-sectional view that appears when the semiconductor chip of FIG. 1 is cut along the II-II cutting line. FIG. 3 is a diagram showing cell layouts of the first transistor and the second transistor. 4A and 4B are diagrams showing the circuit configuration of the semiconductor chip. FIG. 5 is a diagram showing the IV characteristics of the semiconductor chip. FIG. 6 is a schematic cross-sectional view of the semiconductor chip according to another embodiment of the present invention. FIG. 7 is a schematic configuration diagram of a semiconductor package according to another embodiment of the present invention. FIG. 8 is a cross-sectional view that appears when the semiconductor chip of FIG. 7 is cut along the VIII-VIII cutting line. FIG. 9 is a diagram showing cell layouts of the first transistor and the second transistor. 10 is a schematic cross-sectional view of a semiconductor chip according to another embodiment of the present invention. FIG. 11 is a diagram showing cell layouts of the first transistor and the second transistor. FIG. 12 is a schematic configuration diagram of a semiconductor package according to another embodiment of the present invention. FIG. 13 is a schematic perspective view of a semiconductor package according to another embodiment of the present invention. FIG. 14 is a schematic plan view of the semiconductor package of FIG. FIG. 15 is a schematic cross-sectional view of the semiconductor package of FIG. FIG. 16 is a schematic perspective view of the semiconductor device according to the embodiment of the present invention. FIG. 17 is a schematic plan view of the semiconductor device. FIG. 18 is a diagram for comparing the chip sizes of the semiconductor device and the semiconductor device according to the comparative form. FIG. 19 is a diagram showing the internal structure of the semiconductor device, and mainly shows the layout of the active region. FIG. 20 is a diagram showing the internal structure of the semiconductor device, and mainly shows the layout of the first wiring layer. FIG. 21 is a diagram showing the internal structure of the semiconductor device, and mainly shows the layout of the top wiring layer. FIG. 22 is a diagram showing the surface structure of the semiconductor device, and mainly shows the layout of the pad openings. FIG. 23 is a schematic cross-sectional view of the semiconductor device, showing a cross section (source side cross section) of the active region. FIG. 24 is a schematic cross-sectional view of the semiconductor device, showing a cross section (drain side cross section) of the active region. FIG. 25 is a schematic cross-sectional view of the semiconductor device, showing a cross section of the protection diode region. FIG. 26A is a cross-sectional view for explaining an example of the manufacturing process of the semiconductor device of FIG. FIG. 26B is a diagram showing the next manufacturing process of FIG. 26A. FIG. 26C is a diagram showing the next manufacturing process of FIG. 26B. FIG. 26D is a diagram showing the next manufacturing process of FIG. 26C. FIG. 26E is a diagram showing the next manufacturing process of FIG. 26D. FIG. 26F is a diagram showing the next manufacturing process of FIG. 26E.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a schematic configuration diagram of a semiconductor package 1 according to an embodiment of the present invention, and is a diagram showing the internal structure of the semiconductor package 1 in a plane. Note that FIG. 1 shows through the inside of the semiconductor package 1 for convenience.
The semiconductor package 1 is formed in a rectangular parallelepiped shape, and its size is, for example, 1.6 mm × 1.6 mm or less. The semiconductor package 1 includes an island 2, a plurality of terminals 3 to 5, a semiconductor chip 6, and a sealing resin 7.

The island 2 is formed in a rectangular shape in a plan view and is arranged substantially in the center of the semiconductor package 1. In this embodiment, the island 2 is connected to a drain electrode 53, which will be described later. When the semiconductor package 1 is used in the circuit configuration shown in FIG. 4B, the island 2 may also serve as a drain terminal of the semiconductor package 1.
The plurality of terminals 3 to 5 include a first source terminal 3, a second source terminal 4, and a gate terminal 5. The plurality of terminals 3 to 5 are provided unevenly on one side of the thickness direction (direction penetrating the paper surface) of the semiconductor package 1 and the other side. The plurality of terminals 3 to 5 are arranged apart from each other on the one side thereof. In this embodiment, the first source terminal 3 and the second source terminal 4 are arranged at each end (corner portion of the semiconductor package 1) on one side of the pair of opposite sides of the semiconductor package 1, respectively. The gate terminal 5 is arranged at a substantially central portion of the other side of the opposite side.

The semiconductor chip 6 is formed in a rectangular shape in a plan view and is arranged on the island 2. The semiconductor chip 6 has an electrode film 8 formed in a predetermined pattern on a surface opposite to the junction side with the island 2. The electrode film 8 includes a gate wiring 9, a first source wiring 10, and a second source wiring 11.
The gate wiring 9 includes a gate pad 12 and a gate finger 13 extending from the gate pad 12.

The gate pad 12 is arranged at a substantially central portion of the side of the semiconductor chip 6 adjacent to the side of the semiconductor package 1 in which the gate terminal 5 is arranged. Since the distance between the gate pad 12 and the gate terminal 5 is shortened by this arrangement form, the connection by the bonding wire 19 becomes easy.
The gate finger 13 is provided along the peripheral edge portion of the semiconductor chip 6, and the gate pad is provided so as to divide the outer peripheral portion 14 into two, and the outer peripheral portion 14 for partitioning the closed region in the central region of the semiconductor chip 6 inside. Includes a central portion 15 extending from 12 to an outer peripheral portion 14 provided on the opposite side thereof. The closed region in the outer peripheral portion 14 is divided into a first region 16 and a second region 17 by the central portion 15. The first region 16 and the second region 17 are formed on the first source terminal 3 side and the second source terminal 4 side, respectively, with the central portion 15 as a boundary, and the directions along the central portions 15 from the source terminals 3 and 4, respectively. It has a substantially rectangular shape that is long and long.

The first source wiring 10 and the second source wiring 11 are arranged in the first region 16 and the second region 17 partitioned by the gate finger 13, respectively. A gap 18 having a constant width is provided between the first source wiring 10 and the second source wiring 11 and the gate finger 13, and the gap 18 separates the gaps from each other. The first source wiring 10 and the second source wiring 11 have a substantially rectangular shape long in the direction from the source terminals 3 and 4 along the central portion 15, respectively, like the first region 16 and the second region 17. ing. With this shape, a plurality of bonding wires 20 on the first source terminal 3 side and a plurality of bonding wires 21 on the second source terminal 4 side can be connected without interfering with each other.

The sealing resin 7 constitutes the outer shape of the semiconductor package 1, and the semiconductor chip 6 is sealed so that at least a part of the first source terminal 3, the second source terminal 4, and the gate terminal 5 is exposed. There is. When the semiconductor package 1 is used in the circuit configuration shown in FIG. 4B, the island 2 may be exposed as a drain terminal from the back surface of the sealing resin 7.
FIG. 2 is a cross-sectional view that appears when the semiconductor chip 6 of FIG. 1 is cut along the II-II cutting line. FIG. 3 is a diagram showing cell layouts of the first transistor Tr1 and the second transistor Tr2.

The semiconductor chip 6 includes a semiconductor layer 22. The semiconductor layer 22 has a p ⁺ type semiconductor substrate 23 and a p-type epitaxial layer 24 laminated on the substrate 23. The semiconductor layer 22 does not have to have an epitaxial layer, and may be composed of, for example, only a p-type semiconductor substrate.
The region on the semiconductor layer 22 includes a first active region 25 and a second active region 26 adjacent to each other, and a central region 27 is set between these regions 25 and 26.

On the surface portion of the semiconductor layer 22 (p-type epitaxial layer 24), an n-type body region 28 is formed over the entire area of the first active region 25, the second active region 26, and the central region 27. In the p-type epitaxial layer 24, the region on the back surface side of the semiconductor layer 22 with respect to the n-type body region 28 is the p-type drain region 29.
The p-type epitaxial layer 24 is formed with a gate trench 30 that penetrates the n-type body region 28 from its surface and reaches the p-type drain region 29.

As shown in FIG. 3, the gate trench 30 is formed as a whole in a planar grid shape beyond the boundary between the first active region 25, the second active region 26, and the central region 27. As a result, on the surface portion of the p-type epitaxial layer 24, a plurality of unit cells 31 to 33 are partitioned in a plurality of window portions of the lattice-shaped gate trench 30. The unit cells 31 to 33 include a first unit cell 31 for the first transistor Tr1 formed in the first active region 25 and a second unit cell 32 for the second transistor Tr2 formed in the second active region 26. , A third unit cell 33 (dummy cell) formed in the central region 27 and having no function as a transistor is included. That is, in this embodiment, in the semiconductor layer 22, the plurality of first unit cells 31 and the plurality of second unit cells 32 are aggregated in a certain region (first active region 25 and second active region 26), respectively. They are arranged in a matrix in each of the regions 25 and 26.

Further, as shown in FIG. 3, the gate trench 30 includes a first gate trench 34 directly below the first active region 25, a second gate trench 35 directly below the second active region 26, and a second gate trench directly below the central region 27. It can be distinguished from the 3-gate trench 36. The first gate trench 34 and the second gate trench 35 are commonly connected by a third gate trench 36 between these trenches 34 and 35, and are connected to each other via the third gate trench 36.

^{In each first unit cell 31, a p +} type source region 37 is formed on the surface portion of the n-type body region 28. ^{Further, an n +} type body contact region 38 is formed from the surface of the p-type epitaxial layer 24, ^{penetrating the p +} type source region 37 and reaching the n-type body region 28. As a result, the n-type body region 28 can be contacted from the surface side of the p-type epitaxial layer 24.

^{In each second unit cell 32, a p +} type source region 39 is formed on the surface portion of the n-type body region 28. ^{Further, an n +} type body contact region 40 is formed from the surface of the p-type epitaxial layer 24, ^{penetrating the p +} type source region 39 and reaching the n-type body region 28. As a result, the n-type body region 28 can be contacted from the surface side of the p-type epitaxial layer 24.

Each third unit cell 33 does not have a source region or the like on its surface, and is occupied by an n-type body region 28 from the bottom of the gate trench 30 to the open end.
A gate insulating film 41 and a gate electrode 42 are embedded in the gate trench 30. As shown in FIG. 2, the gate electrode 42 is formed in the first gate electrode 43 embedded in the first gate trench 34, the second gate electrode 44 embedded in the second gate trench 35, and the third gate trench 36. It can be distinguished from the embedded third gate electrode 45. The first gate electrode 43 and the second gate electrode 44 are commonly connected by a third gate electrode 45 between these electrodes 43 and 44.

The first gate electrode 43 faces the p ⁺ type source region 37, the n-type body region 28, and the p-type drain region 29 of each first unit cell 31. As a result, in each first unit cell 31, the first transistor Tr1 which is a p-channel type MISFET is configured. Further, the first unit cell 31 is provided with a parasitic diode (first parasitic diode 54) formed by a pn junction between the p-type drain region 29 and the n-type body region 28.

The second gate electrode 44 faces the p ⁺ type source region 39, the n-type body region 28, and the p-type drain region 29 of each second unit cell 32. As a result, the second transistor Tr2, which is a p-channel type MISFET, is configured in each second unit cell 32. Further, the second unit cell 32 is provided with a parasitic diode (first parasitic diode 55) formed by a pn junction between the p-type drain region 29 and the n-type body region 28.

The third gate electrode 45 faces the n-type body region 28 of each third unit cell 33.
An interlayer insulating film 46 is formed on the semiconductor layer 22. A first contact hole 47, a second contact hole 48, and a third contact hole 49 are formed in the interlayer insulating film 46. The first contact hole 47 ^{exposes the p +} type source region 37 and the n ⁺ type body contact region 38 of the first unit cell 31. The second contact hole 48 ^{exposes the p +} type source region 39 and the n ⁺ type body contact region 40 of the second unit cell 32. Further, the third contact hole 49 exposes the third gate electrode 45.

The electrode film 8 shown in FIG. 1 is formed on the interlayer insulating film 46. In the electrode film 8, the first source wiring 10 is ^{connected to the p +} type source region 37 and the n ⁺ type body contact region 38 of the first unit cell 31 via the first contact hole 47. ^{The second source wiring 11 is connected to the p +} type source region 39 and the n ⁺ type body contact region 40 of the second unit cell 32 via the second contact hole 48. Further, the gate finger 13 (central portion 15 in FIG. 2) is connected to the third gate electrode 45 via the third contact hole 49.

A surface protective film 50 is formed on the electrode film 8 so as to cover the electrode film 8. The surface protective film 50 is formed with pad openings 51 and 52 that expose a part of the first source wiring 10 and the second source wiring 11 as pads. On the other hand, the gate finger 13 is covered with the surface protective film 50.
A drain electrode 53 is formed on the entire back surface of the semiconductor layer 22 (p ^{+ type semiconductor substrate 23).} The drain electrode 53 is a common electrode of the first transistor Tr1 and the second transistor Tr2.

The following description will be added with respect to the configuration of the semiconductor chip 6.
The p ⁺ type semiconductor substrate 23 is made of, for example, a p-type silicon substrate. The thickness of the p ⁺ type semiconductor substrate 23 is, for example, 40 μm to 250 μm. The p ⁺ type semiconductor substrate 23 contains, for example, B (boron) as a p-type impurity, and its concentration is about 1 × 10 ²¹ cm ^-3 to 1 × 10 ²² cm ^-3 .

The thickness of the p-type epitaxial layer 24 is, for example, about 3 μm to 8 μm. The p-type epitaxial layer 24 contains, for example, B (boron) as a p-type impurity, and its concentration is about 1 × 10 ¹⁶ cm ^-3 to 1 × 10 ¹⁷ cm ^-3 .
The n-type body region 28 contains, for example, P (phosphorus) and As (arsenic) as n-type impurities, and the concentration thereof is about 2 × 10 ¹⁶ cm ^{-3 to} 3 × 10 ¹⁷ cm ^-3 .

The p-type drain region 29 contains, for example, B (boron) as a p-type impurity, and its concentration is about 1 × 10 ¹⁶ cm ^-3 to 1 × 10 ¹⁷ cm ^-3 .
The p ⁺ type source regions 37 and 39 contain, for example, B (boron) as p-type impurities, and the concentration thereof is about 1 × 10 ²¹ cm ^{-3 to} 5 × 10 ²¹ cm ^-3 .
The n ⁺ type body contact regions 38 and 40 contain, for example, P (phosphorus) and As (arsenic) as n-type impurities, and their concentrations are about 1 × 10 ²¹ cm ^{-3 to} 5 × 10 ²¹ cm ^-3 . be.

The gate insulating film 41 is made of, for example, SiO ₂ (silicon oxide), and the gate electrode 42 is made of, for example, polysilicon (doped polysilicon).
The interlayer insulating film 46 is made of, for example, SiO ₂ (silicon oxide), and the surface protective film 50 is made of, for example, SiN (silicon nitride).
The gate wiring 9, the first source wiring 10, the second source wiring 11, and the drain electrode 53 are made of, for example, Al or an alloy containing Al.

4A and 4B are diagrams showing the circuit configuration of the semiconductor chip 6, in which FIG. 4A is a configuration in which a potential is not applied to the drain (the drain is electrically floated), and FIG. 4B is a drain. It is a configuration in which an electric potential is given. FIG. 5 is a diagram showing the IV characteristics of the semiconductor chip 6.
Next, the operation of the semiconductor chip 6 will be described with reference to FIGS. 2 and 4A and 4B. The correspondence between the alphabetic codes in FIGS. 4A and 4B and the configurations in FIG. 2 is as follows.

1st source S ₁ : 1st source wiring 10 2nd source S ₂ : 2nd source wiring 11
Drain D: Drain electrode 53 Gate G: Gate wiring 9
_{First, a voltage is applied between the first source S 1} and the second source S ₂ (between S _{1 and} S ₂ ) in a state where no voltage is applied to the gate G. More specifically, a positive voltage (+) is applied to _{the first source S 1, and the voltages of the second source S 2} and the gate G are set to 0 V. Further, in the configuration of FIG. 4A, the drain D is electrically floated. On the other hand, as shown in FIG. 4B, the drain D may be used as a terminal. Since the first and second gate electrodes 43 and 44 are commonly connected to the third gate electrode 45, they are held at the same potential with each other.

In the first transistor Tr1, the potential of the n-type body region 28 becomes the same positive potential as the first source wiring 10 (first source S ₁ ^{) via the n + type body contact region 38.} As a result, holes, which are minority carriers in the n-type body region 28, come into contact with the gate insulating film 41 and the n-type body region 28 due to the potential difference between the n-type body region 28 and the first gate electrode 43. Attracted to the surface. Then, a channel by the attracted holes formed, the first transistor Tr1 is turned on, and the p-type drain region 29 from the first source S _1, the current I ₁ flows through the parasitic diode 54.

By turning on the first transistors Tr1, the potential of the drain D is substantially the same potential as the first source S _1, a high potential second for the source S _2. Accordingly, the parasitic diode 55 across the hanging forward voltage of the parasitic diode 55 of the second unit cell 32 is turned on, between the p-type drain region 29 and the second source S ₂ is, via the parasitic diode 55 It becomes a conductive state. _{The current I 1} flowing to the p-type drain region 29 flows from the p-type drain region 29 to the second source S ₂ as the current I ₂ . As a result, a current flows between _{the first source S 1} and the second source S ₂ (between S _{1 and} S _2).

On the other hand, when a positive voltage is applied to the gate G and the potential difference (VGS _{1 ) between the gate G and the first source S 1} approaches 0, it is formed in the n-type body region 28 of the first unit cell 31. The channel disappears and the first transistor Tr1 is turned off. As a result, the _{current between the first source S 1} and the second source S ₂ (between S _{1 and} S ₂ ) is cut off.
Thus, while between S ₁ -S ₂ is conductive when a voltage is not applied to the gate G, and between S ₁ -S ₂ enters a cutoff state when a voltage is applied to the gate G. That is, normalion operation is realized. More specifically, as shown in FIG. 5, in the semiconductor chip 6 having the structure of FIG. 2, a voltage of 5 V is applied between _{the first source S 1} and the second source S ₂ (between S _{1 and} S _2). When no voltage was applied to the gate G, _{a current IS 1} S ₂ of about 2.2 mA flowed _{between S 1 and} S _2. On the other hand, as the voltage applied to the gate G was increased, the current IS ₁ S _{2 decreased, and the current IS 1} S ₂ was cut off when the voltage value of the gate G was around 4.5 V.

Further, unlike the JFET and the depletion type MISFET, the first transistor Tr1 and the second transistor Tr2 that turn on / off the current in the semiconductor chip 6 do not use the spread of the depletion layer for turning the current on / off. Therefore, it is not necessary to design the impurity concentration of each impurity region (28, 29, 37, 39, etc.) of the semiconductor layer 22 in consideration of the depletion layer, so that a low resistance value can be maintained even if the size is reduced. can. Moreover, in the semiconductor chip 6, since the first transistor Tr1 and the second transistor Tr2 are integrated into one chip, further miniaturization can be achieved.

Further, between the first active region 25 and the second active region 26, the entire region on the back surface side of the front surface portion of the semiconductor layer 22 (in this embodiment, the region below the bottom portion of the gate trench 30) is formed. It is occupied by the p-type drain region 29. Therefore, since there is no structure (for example, an element separation structure by an insulating film) that interferes with the current flowing between the first active region 25 and the second active region 26, the current is present in a wide range in the thickness direction of the semiconductor layer 22. A route can be secured. As a result, the low resistance value in the semiconductor layer 22 can be well maintained.
<Other embodiments>
Hereinafter, other embodiments of the semiconductor package 1 and the semiconductor chip 6 described with reference to FIGS. 1 to 5 will be described.

FIG. 6 is a schematic cross-sectional view of the semiconductor chip 6 according to another embodiment of the present invention.
In the semiconductor chip 6 shown in FIG. 2, a third gate electrode 45 embedded in the gate trench 30 was used as an electrode for connecting the first gate electrode 43 and the second gate electrode 44 in common. The 3-gate electrode 45 may be omitted.
In this case, the first gate electrode 43 and the second gate electrode 44 are formed along the surface of the semiconductor layer 22 (p-type epitaxial layer 24) in the central region 27, as shown in FIG. May be connected to each other by. The third gate electrode 56 straddles the first gate electrode 43 and the second gate electrode 44, and is connected to each of the first gate electrode 43 and the second gate electrode 44 from above.

Further, as shown in FIG. 6, the n-type body region 28 in the central region 27 may be omitted, and the omitted portion may be occupied by a part of the p-type drain region 29. This configuration may be applied to the configuration of FIG. 2 described above.
FIG. 7 is a schematic configuration diagram of a semiconductor package 1 according to another embodiment of the present invention. FIG. 8 is a cross-sectional view that appears when the semiconductor chip 6 of FIG. 7 is cut along the VIII-VIII cutting line. FIG. 9 is a diagram showing cell layouts of the first transistor Tr1 and the second transistor Tr2. In FIG. 7, the gate finger 13 is omitted.

In the semiconductor chip 6 of FIG. 2, the region on the semiconductor layer 22 is divided into two, and a first active region 25 is formed on one side and a second active region 26 is formed on the other side. The first source wiring 10 and the second source wiring 11 were formed in a plane so as to cover the first active region 25 and the second active region 26, respectively.
On the other hand, in the semiconductor chip 6 of FIG. 7, the first source wiring 10 and the second source wiring 11 are formed in a comb-teeth shape in which they mesh with each other at intervals. In this case, as shown in FIGS. 8 and 9, the semiconductor layer 22 is composed of a linear first unit cell row 57 composed of a plurality of first unit cells 31 and a plurality of second unit cells 32. The linear second unit cell rows 58 may be alternately arranged at intervals from each other.

As shown in FIG. 9, the tooth portions 59 and 60 of the comb-shaped first source wiring 10 and the second source wiring 11 are placed above the first unit cell row 57 and the second unit cell row 58, respectively. By providing the first source wiring 10, the contact between the first source wiring 10 and the first transistor Tr1 (p ⁺ type source region 37) and the contact between the second source wiring 11 and the second transistor Tr2 (p ⁺ type source region 39) can be facilitated. Can be taken to.

With the configurations of FIGS. 7 to 9, the distance from the first transistor Tr1 to the second transistor Tr2 can be made uniform over the entire semiconductor layer 22 regardless of the position of the first transistor Tr1, so that current variation between cells can be suppressed. can do.
FIG. 10 is a schematic cross-sectional view of the semiconductor chip 6 according to another embodiment of the present invention.
In the semiconductor chip 6 of FIG. 2, a MISFET having a trench gate structure is adopted as the first transistor Tr1 and the second transistor Tr2, but as shown in FIG. 10, a MISFET having a planar gate structure may be adopted.

In the first and second transistors Tr1 and Tr2 having a planar gate structure, a gate insulating film 41 is formed on the surface of the semiconductor layer 22, and a gate electrode 42 is formed on the gate insulating film 41. The first gate electrode 43 and the second gate electrode 44 face each other of the n-type body region 28 exposed on the surface of the semiconductor layer 22.
FIG. 11 is a diagram showing cell layouts of the first transistor Tr1 and the second transistor Tr2.

In the semiconductor chip 6 of FIG. 2, the plurality of first unit cells 31 (first transistor Tr1) and the plurality of second unit cells 32 (second transistor Tr2) are in a certain region (first active region 25 and second transistor Tr2), respectively. 2 It was aggregated and arranged in the active area 26).
On the other hand, the plurality of first unit cells 31 and the plurality of second unit cells 32 arranged in a matrix may be alternately arranged in the row direction and the column direction, respectively, as shown in FIG. With this configuration as well, similarly to the configurations shown in FIGS. 7 to 9, the distance from the first transistor Tr1 to the second transistor Tr2 can be made uniform over the entire semiconductor layer 22, so that current variation between cells can be suppressed. be able to.

FIG. 12 is a schematic configuration diagram of a semiconductor package 1 according to another embodiment of the present invention.
In the semiconductor package 1 of FIG. 1, the first transistor Tr1 and the second transistor Tr2 are integrated into one semiconductor chip 6 into one chip, but any semiconductor device satisfying the circuit configuration diagrams shown in FIGS. 4A and 4B. For example, the form as shown in FIG. 12 may be used.
The semiconductor package 1 of FIG. 12 includes an island 68, a plurality of terminals 62 to 64, a first semiconductor chip 65, a second semiconductor chip 66, and a sealing resin 7.

Both the first semiconductor chip 65 and the second semiconductor chip 66 are provided on the island 68. That is, the island 68 may be a common electrode for the drains of the first semiconductor chip 65 (first transistor Tr1) and the second semiconductor chip 66 (second transistor Tr2).
The plurality of terminals 62 to 64 include a first source terminal 62, a second source terminal 63, and a gate terminal 64.

The first source terminal 62 is connected to the source pad 70 of the first semiconductor chip 65 via a bonding wire 69. On the other hand, the second source terminal 63 is connected to the source pad 72 of the second semiconductor chip 66 via the bonding wire 71.
The gate terminal 64 is connected to the gate pad 75 of the first semiconductor chip 65 and the gate pad 76 of the second semiconductor chip 66 via the bonding wires 73 and 74. That is, the gate terminal 64 is a common electrode for the gate of the first semiconductor chip 65 (first transistor Tr1) and the second semiconductor chip 66 (second transistor Tr2).

FIG. 13 is a schematic perspective view of the semiconductor package 1 according to another embodiment of the present invention. FIG. 14 is a schematic plan view of the semiconductor package 1 of FIG. FIG. 15 is a schematic cross-sectional view of the semiconductor package 1 of FIG. Note that FIG. 15 does not show a cross section of a specific portion of FIGS. 13 and 14, but selectively shows components necessary for explaining the internal structure of the semiconductor package 1.

The semiconductor package 1 of FIGS. 13 and 14 has a package structure of WL-CSP (Wafer Level-Chip Size Package). That is, in the semiconductor package 1, the above-mentioned semiconductor chip 6 has a semiconductor layer 22 (semiconductor substrate) having a rectangular shape in a plan view, and is configured to have a size substantially the same as the outer size of the semiconductor layer 22. For example, the length L of the semiconductor package 1 is less than 0.50 mm (preferably 0.40 mm or more), the width W is less than 0.40 mm (preferably 0.30 mm or more), and the thickness D is 0. It is less than .15 mm (preferably 0.10 mm or more). That is, the semiconductor package 1 has a very small package structure of 0403 size. Further, since the thickness of the semiconductor package 1 is less than 0.15 mm, even if the semiconductor package 1 is mounted at an angle, the amount of protrusion of the side surface of the semiconductor package 1 from the normal position can be reduced. As a result, even when the semiconductor package 1 is mounted at high density, contact with the adjacent semiconductor package can be suppressed.

Since the semiconductor package 1 has a WL-CSP package structure, when the shapes and sizes of the semiconductor package 1 and the semiconductor layer 22 and the arrangement positions of other components are described below, the subject of the description is It may be replaced with the other. For example, the plane-viewing quadrangular semiconductor layer 22 may be replaced with the plan-viewing quadrangular semiconductor package 1, and the explanation that the pad is arranged on the peripheral edge of the semiconductor layer 22 is the peripheral portion of the semiconductor package 1. It may be replaced with the explanation that the pad is arranged in.

The rectangular parallelepiped semiconductor layer 22 has a front surface 22A, a back surface 22B opposite the front surface 22A, and four side surfaces 22C, 22D, 22E, 22F between the front surface 22A and the back surface 22B, and the front surface 22A and the side surface 22A. 22C to 22F are covered with the surface protective film 50 (see FIG. 15). Of the four side surfaces 22C to 22F of the semiconductor layer 22, the side surfaces 22C and 22E are side surfaces along the long side 77 of the semiconductor layer 22, and the side surfaces 22D and 22F are side surfaces along the short side 78 of the semiconductor layer 22. Corner portions 80CD, 80DE, 80EF, 80FC of the semiconductor layer 22 are formed at the intersections of the adjacent side surfaces 22C to 22F.

On the surface 22A of the semiconductor layer 22, the first source pad 83 is arranged on the first peripheral edge portion 81 along one side surface 22C on the long side 77 side. As shown in FIG. 15, the first source pad 83 is a portion of the first source wiring 10 exposed from the pad opening 51. The first source pad 83 is formed at a central portion spaced from both end corner portions 80CD and 80FC of the first peripheral edge portion 81, and is formed between the first source pad 83 and each corner portion 80CD and 80FC. Regions at regular intervals (for example, about 0.1 mm to 0.15 mm) covered with the surface protective film 50 are provided.

On the other hand, the second source pad 84 is arranged at one end corner portion 80EF of the second peripheral edge portion 82 of the semiconductor layer 22 facing the first peripheral edge portion 81, and the other end corner portion 80DE of the second peripheral edge portion 82 is provided. The gate pad 85 is arranged. As shown in FIG. 15, the second source pad 84 is a portion of the second source wiring 11 exposed from the pad opening 52. On the other hand, the gate pad 85 is a portion where a part of the gate wiring 9 is exposed from the pad opening 79 (see FIGS. 13 and 14) at a position not shown in FIG.

In the semiconductor package 1 of FIGS. 13 to 15, the layout of the gate wiring 9, the first source wiring 10 and the second source wiring 11 is the layout shown in FIG. 1 (arranged at the corner 80DE of the gate pad 85). By forming the structure on the semiconductor layer 22 into a multi-layer wiring structure, the gate wiring 9, the first source wiring 10 and the second source wiring 11 may have an appropriate shape and size so as not to interfere with each other. You may route with.

Next, the layout and shape of the first source pad 83, the second source pad 84, and the gate pad 85 will be described.
As shown in FIG. 14, the first source pad 83 has a radius of the length of the short side 78 of the semiconductor layer 22 (width W in FIG. 13) centered on the apex V1 of one end corner portion 80EF of the second peripheral edge portion 82. The second arc is centered on the first arc 86 and the apex V2 of the other end corner 80DE of the second peripheral edge 82, and the radius is the length of the short side 78 of the semiconductor layer 22 (width W in FIG. 13). When 87 is drawn on the surface 22A of the semiconductor layer 22, it is arranged in the outer region of the first arc 86 and in the outer region of the second arc 87. Then, the first source pad 83 has two sides of a pair of tangents drawn from the intersection 88 of the first arc 86 and the second arc 87 with respect to each of the first arc 86 and the second arc 87 in the outer region. It is formed in a triangular shape.

On the other hand, the second source pad 84 is formed in a fan shape having the same center as the first arc 86. The radius R1 of the second source pad 84 is, for example, 0.1 mm to 0.13 mm. Further, the gate pad 85 is formed in a fan shape having the same center as the second arc 87. The radius R2 of the gate pad 85 is, for example, 0.1 mm to 0.13 mm.
According to the semiconductor package 1 of FIGS. 13 to 15, since the package structure is the WL-CSP, all the electrical connections inside the package are wireless structures that do not use bonding wires. As a result, the wire resistance can also be reduced, so that the on-resistance per package size can be significantly reduced.

Further, although the semiconductor package 1 has a package structure of WL-CSP, the side surfaces 22C to 22F of the semiconductor layer 22 are covered with the surface protective film 50. Therefore, when the semiconductor package 1 is mounted at a high density, it is possible to prevent a short circuit between the semiconductor packages 1 and the adjacent semiconductor packages.
Although one embodiment of the present invention has been described above with reference to FIGS. 1 to 15, the configurations of the semiconductor package 1 and the semiconductor chip 6 are not limited to those described above, and the matters described in the claims. It is possible to make various design changes within the range.

For example, in the above-described embodiment, only the vertical structure element is shown as the structure of the first transistor Tr1 and the second transistor Tr2, but a horizontal structure element can also be applied.
FIG. 16 is a schematic perspective view of the semiconductor device 101 according to the embodiment of the present invention. FIG. 17 is a schematic plan view of the semiconductor device 101 according to the embodiment of the present invention.

The semiconductor device 101 has a WL-CSP (Wafer Level-Chip Size Package) package structure. That is, the semiconductor device 101 has a semiconductor substrate 102 having a rectangular shape in a plan view, and is configured to have a size substantially the same as the outer size of the semiconductor substrate 102. For example, the length L of the semiconductor device 101 is less than 0.50 mm (preferably 0.40 mm or more), the width W is less than 0.40 mm (preferably 0.30 mm or more), and the thickness D is 0. It is less than .15 mm (preferably 0.10 mm or more). For example, when the length L of the semiconductor device 101 is 0.50 mm and the width W is 0.40 mm, the plane area of the semiconductor device 101 is 0.20 mm ² . Further, when the length L of the semiconductor device 101 is 0.40 mm and the width W is 0.30 mm, the plane area of the semiconductor device 101 is 0.12 mm ² . That is, the semiconductor device 101 has a very small package structure of 0403 size. Further, since the thickness of the semiconductor device 101 is less than 0.15 mm, even if the semiconductor device 101 is mounted at an angle, the amount of protrusion of the side surface of the semiconductor device 101 from the normal position can be reduced. As a result, even when the semiconductor device 101 is mounted at high density, contact with the adjacent semiconductor device can be suppressed.

Since the semiconductor device 101 has a WL-CSP package structure, when the shapes and sizes of the semiconductor device 101 and the semiconductor substrate 102, the arrangement positions of other components, and the like are described below, the subject of the description is. It may be replaced with the other. For example, the plane-viewing quadrangular semiconductor substrate 102 may be replaced with the plan-viewing quadrangular semiconductor device 101, and the description that the pad is arranged on the peripheral edge of the semiconductor substrate 102 is described in the peripheral portion of the semiconductor device 101. It may be replaced with the explanation that the pad is arranged in.

The rectangular parallelepiped semiconductor substrate 102 has a front surface 102A, a back surface 102B on the opposite side of the front surface 102A, and four side surfaces 102C, 102D, 102E, 102F between the front surface 102A and the back surface 102B. 102C to 102F are covered with the surface insulating film 103. Of the four side surfaces 102C to 102F of the semiconductor substrate 102, the side surfaces 102C and 102E are side surfaces along the long side 121 of the semiconductor substrate 102, and the side surfaces 102D and 102F are side surfaces along the short side 122 of the semiconductor substrate 102. Corner portions 104CD, 104DE, 104EF, 104FC of the semiconductor substrate 102 are formed at each intersection of the adjacent side surfaces 102C to 102F.

On the surface 102A of the semiconductor substrate 102, a drain pad 107 (first pad) is arranged on the first peripheral edge portion 105 along one side surface 102C on the long side 121 side. The drain pad 107 is formed at a central portion spaced from both end corner portions 104CD and 104FC of the first peripheral edge portion 105, and a surface insulating film 103 is formed between the drain pad 107 and each corner portion 104CD and 104FC. Regions at regular intervals (for example, about 0.1 mm to 0.15 mm) covered with are provided.

On the other hand, a source pad 108 (second pad) is arranged at one end corner portion 104EF of the second peripheral edge portion 106 of the semiconductor substrate 102 facing the first peripheral edge portion 105, and the other end corner portion 104DE of the second peripheral edge portion 106 is arranged. A gate pad 109 (third pad) is arranged in the.
Next, the layout and shape of the drain pad 107, the source pad 108, and the gate pad 109 will be described.

As shown in FIG. 17, the drain pad 107 is centered on the apex V1 of one end corner portion 104EF of the second peripheral edge portion 106, and the length of the short side 122 of the semiconductor substrate 102 (width W in FIG. 16) is the radius. The first arc 110 and the second arc 111 centered on the apex V2 of the other end corner 104DE of the second peripheral edge 106 and having the length of the short side 122 of the semiconductor substrate 102 (width W in FIG. 16) as the radius. Is drawn on the surface 102A of the semiconductor substrate 102, it is located in the outer region of the first arc 110 and in the outer region of the second arc 111. The drain pad 107 has a pair of tangents drawn from the intersection 112 of the first arc 110 and the second arc 111 with respect to each of the first arc 110 and the second arc 111 as two sides in the outer region. It is formed in a triangular shape.

On the other hand, the source pad 108 is formed in a fan shape having the same center as the first arc 110. The radius R1 of the source pad 108 is, for example, 0.07 mm to 0.13 mm (preferably 0.10 mm or more). For example, when the radius R1 is 0.07 mm, the area of the source pad 108 is 3.85 × 10 ^-3 mm ² , and when the radius R1 is 0.10 mm, the area of the source pad 108 is 7.85 ×. It is 10 ^-3 mm ² . Further, the gate pad 109 is formed in a fan shape having the same center as the second arc 111. The radius R2 of the gate pad 109 is, for example, 0.07 mm to 0.13 mm (preferably 0.10 mm or more). For example, when the radius R2 is 0.07 mm, the area of the gate pad 109 is 3.85 × 10 ^-3 mm ² , and when the radius R2 is 0.10 mm, the area of the gate pad 109 is 7.85 ×. It is 10 ^-3 mm ² .

Next, how much the mounting area of the semiconductor device 101 can be reduced by the layout and shape of the drain pad 107, the source pad 108, and the gate pad 109 described above will be described with reference to FIG.
FIG. 18 is a diagram for comparing the chip sizes of the semiconductor device 101 and the semiconductor device 200 according to the comparative form. In FIG. 18, among the reference codes shown in FIGS. 16 and 17, only the reference codes necessary for comparison are shown, and the other reference codes are omitted for the sake of clarity.

First, when the source pad 108 and the gate pad 109 are arranged next to each other on the short side 122 of the semiconductor substrate 102 as in the semiconductor device 200 of the comparative form, the package size of the semiconductor device 200 is, for example, the length L. = 0.6 mm, width W = 0.4 mm. This is to secure at least a pitch P = 0.2 mm as the distance between the source pad 108 and the gate pad 109 in order to avoid a short circuit between the source and the gate in the short side direction. Further, the drain pad 107 is formed in a shape extending from one end corner portion to the other end corner portion of the short side 122. Therefore, if the package size is reduced without changing the pad layout, the pitch P between the source and the gate is less than 0.2 mm, which causes a problem of a short circuit between the source and the gate at the time of mounting. On the other hand, even if the source pad 108 and the gate pad 109 are arranged so as to be adjacent to each other on the long side 121, it is difficult to solve the problem of short circuit between the pads. This is because, in this pad layout, the drain pad 107 has a shape extending from one end corner to the other end corner of the long side 121 as shown by the reference code “107 ′” and the broken line. Therefore, as the package size decreases, the problem of short circuit between the source and the drain or between the gate and the drain arises.

On the other hand, in the configuration of the semiconductor device 101 described above, the source pad 108 and the gate pad 109 are arranged so as to be adjacent to each other on the long side 121. Further, the drain pad 107 is arranged at the center of the long side 121 of the semiconductor substrate 102, and is covered with a surface insulating film 103 between the drain pad 107 and both end corners 104CD and 104FC of the long side 121. Areas at regular intervals are provided. As a result, the distance between the drain pad 107 and the source pad 108 (pitch P1) and the distance between the drain pad 107 and the gate pad 109 (pitch P2) can be made longer than those of the semiconductor device 200 of the comparative form. Therefore, even if the package size of the semiconductor device 101 is reduced to, for example, a length L = 0.44 mm and a width W = 0.32 mm, the pitch P1 and the pitch P2 are the pitch P between the source and the gate in the semiconductor device 200. Can be maintained at 0.2 mm, which is equivalent to. That is, the distance secured between the pads is 0.20 / 0.32 = 62.5% or more of the short side 122 of the package of the semiconductor device 101. At least, when the short side 122 of the package is 0.40 mm, the distance secured between the pads is 0.20 / 0.40 = 50% or more of the short side 122 of the package of the semiconductor device 101. Further, when the package size of the semiconductor device 101 is 1.41 × 10 ^-1 mm ² and the pad radiuses R1 and R2 are 0.10 mm ^{, the pad area is 7.85 × 10 -3 mm 2} , so that the source The area (pad area) of the pad 108 and the gate pad 109 is 5% or more of the package size. Therefore, the size of the semiconductor substrate can be made smaller than that of the semiconductor device 200 while avoiding a short circuit at the time of mounting. This makes it possible to provide a miniaturized semiconductor device.

Further, in the semiconductor device 101, as shown in FIG. 17, drain pads 107 are arranged in outer regions of the first arc 110 and the second arc 111 having the length of the short side 122 as the radius, respectively. Therefore, as the pitch P1 and the pitch P2, it is possible to secure at least a length corresponding to the difference between the length of the short side 122 of the semiconductor device 101 and the size (width) of the source pad 108 and the gate pad 109. Further, the drain pad 107 is formed in a triangular shape having a pair of tangents drawn from the intersection 112 of the first arc 110 and the second arc 111 with respect to each of the first arc 110 and the second arc 111 as two sides. ing. As a result, it is possible to secure a sufficient bonding area for the drain pad 107 while reducing the size of the semiconductor device 101. Therefore, it is possible to suppress a decrease in the fixing strength at the time of mounting the semiconductor device 101.

Regarding ensuring the fixing strength at the time of mounting the semiconductor device 101, the source pad 108 and the gate pad 109 are further formed in a fan shape having the same center as the first arc 110 and the second arc 111, respectively. As a result, it is possible to secure a sufficient joining area for the source pad 108 and the gate pad 109 while ensuring a length of 0.2 mm as the pitch P1 and the pitch P2.

As described above, according to the semiconductor device 101, the mounting area can be reduced by about 40% as compared with the semiconductor device 200 of the comparative form while sufficiently securing the pitch between adjacent pads and the bonding area of the pads.
Next, the internal structure of the semiconductor device 101 will be described with reference to FIGS. 19 to 25.
19 to 21 are views showing the internal structure of the semiconductor device 101. FIG. 19 mainly shows the layout of the active region 113, FIG. 20 mainly shows the layout of the first wiring layer 144, and FIG. 21 mainly shows the layout of the top wiring layer 154. FIG. 22 is a diagram showing the surface structure of the semiconductor device 101, and mainly shows the layout of the pad openings 160 to 162. 23 and 24 are schematic cross-sectional views of the semiconductor device 101. FIG. 23 shows a cross section on the source side of the active region 113, and FIG. 24 shows a cross section on the drain side of the active region 113. FIG. 25 is a schematic cross-sectional view of the semiconductor device 101, showing a cross section of the protection diode region 114. Note that FIGS. 23 to 25 do not show a cross section of a specific portion of the plan view of FIGS. 19 to 21, but selectively show components necessary for explaining the internal structure of the semiconductor device 101. ..

As described above, the semiconductor device 101 has a semiconductor substrate 102. An active region 113 and a protection diode region 114 are set on the semiconductor substrate 102. In this embodiment, as shown in FIG. 19, for example, a protection diode region 114 having a rectangular shape in a plan view is formed on one corner portion 104DE of the semiconductor substrate 102. The active region 113 is formed in substantially the entire surface region of the semiconductor substrate 102 except for the corner portion 104DE at regular intervals from the protection diode region 114.

As shown in FIGS. 23 and 24, the semiconductor substrate 102 includes, on its surface, a separation well 115 that separates a portion of the active region 113 from the other portion as an electrically floating region. More specifically, the semiconductor substrate 102 includes a p-type silicon substrate 116 and an n ^- type epitaxial layer 117 formed on the p-type silicon substrate 116. The p-type separation well 115 is formed in a strip shape that draws a closed curve in a plan view, and reaches the p-type silicon substrate 116 from the surface 102A of ^{the n−-type epitaxial layer 117.} thickness of the n ^- -type epitaxial layer 117 is, for example, 5.0Myuemu～10myuemu.

Further, the separation well 115 has ^{a two-layer structure consisting of a p + type well region 118 arranged on the upper side and a p −} type low isolation (L / I) region 119 arranged on the lower side, and these regions. boundaries 118, 119 the n ^- is set to the thickness direction the middle section of the type epitaxial layer 117. For example, the boundary regions 118 and 119, n ^- is set from the surface 102A of the type epitaxial layer 117 to a depth position of 1.0Myuemu～2.0Myuemu.

As a result, the semiconductor substrate 102 is partitioned on the p-type silicon substrate 116 with an element region 120 composed of a part of ^{the n-type epitaxial layer 117 surrounded by the separation well 115.
An n +} type embedded layer (B / L) 123 is selectively formed in the element region 120. n ⁺ -type buried layer 123, the semiconductor substrate 102, p-type silicon substrate 116 and the n ^- are formed so as to straddle the boundary between -type epitaxial layer 117. The film thickness of the n ⁺ type embedded layer 123 is, for example, 2.0 μm to 3.0 μm.

A field insulating film 124 is formed on the surface of the separation well 115. Field insulating film 124, for example, n ^- a LOCOS film formed by selectively oxidizing the surface of the type epitaxial layer 117.
A DMOSFET (Double-Diffused MOSFET) 125 is formed in the element region 120. DMOSFET125 is, n ^- and a type well region 127 ^- -type well region 126 and p ^- on the surface of the type epitaxial layer 117, n formed at intervals from each other. The n ^- type well region 126 and the p ^- type well region 127 are stripes extending in the short side direction from the first peripheral edge portion 105 to the second peripheral edge portion 106 of the semiconductor substrate 102, as shown in the planes of FIGS. 19 to 22. It is formed in a shape and is arranged alternately. In FIGS. 19 to 22, in addition to the n ^- type well region 126 and the p ^- type well region 127, a striped n ⁺ type drain region 128 (described later) formed in these inner regions is used for clarification. ), N ⁺ type source region 129 (described later) and n ⁻ type impurity region 130 (described later) are shown together.

^{An n +} type drain region 128 having a higher impurity concentration than the n ⁻ type well region 126 is formed on the surface of the n ^{− type well region 126. Further, an n +} type source region 129 is formed on the surface of the p ⁻ type well region 127, ^{and an n −} type impurity region 130 is formed so as to surround the n + type source region 129.
The outer peripheral edge of the n ⁺ type source region 129 is arranged at a position at a certain distance inward from the outer ^{peripheral edge of the p − type well region 127.}

On the surface of the ^n- type epitaxial layer 117, a field insulating film 131 is formed in a portion between the ^n- type well region 126 and the p ^{-type well region 127.} The field insulating film 131 is a LOCOS film formed in the same process as the above-mentioned field insulating film 124.
One peripheral edge of the field insulating film 131 ^{is arranged on the peripheral edge of the n +} type drain region 128, and the other peripheral edge of the field insulating film 131 is n with a certain distance inward from the outer peripheral edge ^{of the n − type well region 126.} It is located on the ^{− type well region 126.} The n ⁺ type drain region 128 is formed in a region sandwiched between the peripheral edge of the field insulating film 131 and the field insulating film 124.

Further, n ^- the surface of the type epitaxial layer 117, n ^- -type epitaxial layer 117 and p ^- gate insulating film 132 so as to straddle between the type well region 127 is formed. Then, the gate electrode 133 is formed via the gate insulating film 132. The gate electrode 133 is formed so as to selectively cover a part of the gate insulating film 132 and a part of the field insulating film 131.

The gate electrode 133 may be composed of, for example, a lower layer film 134 containing Poly-Si (polysilicon) and an upper layer film 135 containing WSi / Si (tungsten silicide / silicon). The gate insulating film 132, for example, n ^- may be a type epitaxial layer 117 of silicon oxide surface was formed by oxidation of (SiO _2).
^{The region where the gate electrode 133 faces the p-} type well region 127 via the gate insulating film 132 is the channel region 136 of the DMOSFET 125. The formation of channels in the channel region 136 is controlled by the gate electrode 133.

On the other hand, in the protection diode region 114, as shown in FIG. 25, the protection diode 137 is formed on the gate insulating film 132. The protection diode 137 includes a p-type portion 138 and an n-type portion 139. As shown in the planes of FIGS. 19 to 22, the p-type portion 138 and the n-type portion 139 are formed in a striped shape extending in the short side direction from the first peripheral edge portion 105 to the second peripheral edge portion 106 of the semiconductor substrate 102. , Are arranged alternately. The p-shaped portions 138 are arranged at both ends of the stripe pattern. The protection diode 137 is composed of a pair of p-type portions 138 and n-type portions 139 that are adjacent to each other. Further, the protection diode 137 may have a two-layer structure of the lower layer film 134 and the upper layer film 135, similarly to the gate electrode 133.

Then, the first interlayer film 140 and the second interlayer film 141 are formed so as to cover the entire surface region of the semiconductor substrate 102. The first interlayer film 140 and the second interlayer film 141 are formed of, for example, an insulating material such as _{silicon oxide (SiO 2).} In this embodiment, the first interlayer film 140 and the second interlayer film 141 are formed, but a third, fourth or higher interlayer film is further formed as an upper layer film of the second interlayer film 141. It may have a different configuration. Further, between the first interlayer film 140 and the semiconductor substrate 102, and between the second interlayer film 141 and the first interlayer film 140, etching stop films 142 and 143 made of, for example, silicon nitride (SiN) are formed, respectively. It may be sandwiched. The etching stop film 142 may be formed on the field insulating films 124 and 131.

A first wiring layer 144 is formed on the first interlayer film 140. The first wiring layer 144 includes a source first metal 145, a drain first metal 146, and a gate first metal 147. These are made of, for example, a metal layer such as AlCu, and a barrier layer (for example, Ti, TiN, etc.) may be formed on the front and back surfaces thereof, if necessary.
As shown in FIG. 20, the source first metal 145 is formed so as to cover substantially half of the active region 113 on the second peripheral edge 106 side. Specifically, it is formed on the side surface 102F side in the longitudinal direction and on the side surface 102C side in the width direction with respect to the protection diode region 114 so as to avoid the protection diode region 114. Therefore, in a plan view, the substantially square protection diode region 114 has two inner sides adjacent to the source first metal 145. The source first metal 145 is formed ^{via a plug (for example, a tungsten plug) 149 in the striped n +} type drain region 128 and the source side end region 148 on the second peripheral edge 106 side of the ^{n + type source region 129.} , N ⁺ type source area 129. Further, as shown in FIG. 25, the source first metal 145 is connected to a p-shaped portion 138 arranged at one end of the protection diode 137 via a plug (for example, a tungsten plug) 150.

As shown in FIG. 20, the drain first metal 146 is formed so as to cover substantially half of the active region 113 on the first peripheral edge portion 105 side. The drain first metal 146 is ^{provided via a plug (for example, a tungsten plug) 152 in the striped n +} type drain region 128 and the drain side end region 151 on the first peripheral edge portion 105 side of the ^{n + type source region 129.} , N ⁺ type drain area 128 is connected.

As shown in FIG. 25, the gate first metal 147 is connected to a p-shaped portion 138 arranged at the other end of the protection diode 137 via a plug (for example, a tungsten plug) 153. Further, the gate first metal 147 is connected to the gate electrode 133 at a position (not shown).
A top wiring layer 154 is formed on the second interlayer film 141. In this embodiment, since the second interlayer film 141 is the uppermost interlayer film, it is referred to as the top wiring layer 154. However, when a third interlayer film or the like is further formed on the second interlayer film 141, the third interlayer film or the like is said. The wiring layer of the bilayer film 141 may be referred to as a second wiring layer.

The top wiring layer 154 includes a source top metal 155, a drain top metal 156 and a gate top metal 157. These are made of, for example, a metal layer such as AlCu, and a barrier layer (for example, Ti, TiN, etc.) may be formed on the front and back surfaces thereof, if necessary.
As shown in FIG. 21, the gate top metal 157 is formed in a similar plan view fan shape larger than the gate pad 109, and a part thereof is on the side surface 102C side with respect to the protection diode 137 and the protection diode region 114. It overlaps the source side edge region 148. Further, the gate top metal 157 is connected to the gate first metal 147 at a position (not shown).

As shown in FIG. 21, the source top metal 155 is formed so as to cover substantially half of the active region 113 on the second peripheral edge 106 side. Specifically, it is formed on the side surface 102F side in the longitudinal direction and on the side surface 102C side in the width direction with respect to the gate top metal 157 so as to avoid the gate top metal 157. Therefore, the arc portion of the plan view fan-shaped gate top metal 157 is adjacent to the source top metal 155. As shown in FIG. 23, the source top metal 155 is connected to the source first metal 145 via a plug (for example, a tungsten plug) 158.

As shown in FIG. 21, the drain top metal 156 is formed so as to cover substantially half of the active region 113 on the first peripheral edge portion 105 side. As shown in FIG. 24, the drain top metal 156 is connected to the drain first metal 146 via a plug (for example, a tungsten plug) 159.
A surface insulating film 103 is formed on the second interlayer film 141 so as to cover the top wiring layer 154. The surface insulating film 103 covers the surface 102A side of the semiconductor substrate 102 and also covers the side surfaces 102C to 102F of the semiconductor substrate 102 (see FIG. 23). The surface insulating film 103 may be made of, for example, silicon nitride (SiN).

The surface insulating film 103 is formed with pad openings 160 to 162 that expose a part of the source top metal 155, the drain top metal 156, and the gate top metal 157 as the source pad 108, the drain pad 107, and the gate pad 109, respectively. ing.
As shown in FIG. 23, the source pad 108 is formed with a source terminal 163 (bump). As shown in FIG. 24, the drain terminal 107 is formed with a drain terminal 164 (bump). Further, although not shown, a gate terminal (bump) is also formed on the gate pad 109. These terminals may have, for example, a laminated structure of a Ni layer 165, a Pd layer 166, and an Au layer 167 laminated by a plating method. By having the Au layer 167 on the outermost surface, it is possible to provide terminals (electrodes) having excellent corrosion resistance and solder wettability and having high reliability.

As described above, according to the semiconductor device 101, the source first metal 145, the source top metal 155, the drain first metal 146, and the drain top metal 156 are each formed so as to cover approximately half of the active region 113. Has been done. As a result, a wide current path between the source and the drain can be secured. Therefore, it is possible to suppress an increase in the on-resistance of the MIS transistor while reducing the size of the semiconductor device 101. Further, since the semiconductor device 101 has a WL-CSP package structure, all the electrical connections inside the package have a wireless structure that does not use bonding wires. As a result, the wire resistance can also be reduced, so that the on-resistance per package size can be significantly reduced.

Further, although the semiconductor device 101 has a package structure of WL-CSP, the side surfaces 102C to 102F of the semiconductor substrate 102 are covered with the surface insulating film 103. Therefore, when the semiconductor device 101 is mounted at high density, it is possible to prevent a short circuit between the semiconductor device 101 and the adjacent semiconductor device.
Next, the manufacturing process of the semiconductor device 101 will be described with reference to FIGS. 26A to 26F. 26A to 26F are cross-sectional views for explaining an example of a manufacturing process of the semiconductor device 101. 26A to 26F correspond to FIG. 23, respectively.

In order to manufacture the semiconductor device 101, a p-type silicon substrate 116 in a wafer state is prepared. Next, the n-type impurities and the p-type impurities are selectively injected onto the surface of the p-type silicon substrate 116. Then, for example, at a temperature of 1100 ° C. or higher, the silicon of the p-type silicon substrate 116 is epitaxially grown while adding n-type impurities. As a result, as shown in FIG. 26A, the semiconductor substrate 102 (wafer) including ^{the p-type silicon substrate 116 and the n-type epitaxial layer 117 is formed.}

During the epitaxial growth of the p-type silicon substrate 116, the n-type impurities and the p-type impurities injected into the p-type silicon substrate 116 diffuse in the growth direction of ^{the n−-type epitaxial layer 117.} Thus, p-type silicon substrate 116 and the n ^{- n +} -type cross a boundary between -type epitaxial layer 117 buried layer 123 and p ^- -type low isolation region 119 is formed. Examples of the p-type impurity include B (boron) and Al (aluminum), and examples of the n-type impurity include P (phosphorus) and As (arsenic). can.

Next, an ion implantation mask (not shown) having an opening selectively in the region where ^{the p + type well region 118 should be formed is formed on the n −} type epitaxial layer 117. Then, the p-type impurity is implanted into the n ^- type epitaxial layer 117 through the ion implantation mask. As a result, a separation well 115 having a two-layer structure consisting ^{of a p +} type well region 118 and a p ^{− type low isolation region 119 is formed.} After the separation well 115 is formed, the ion implantation mask is removed.

Next, (not shown) the hard mask having a selectively opening in a region for forming the field insulating film 124, and 131 the n ^- is formed on the type epitaxial layer 117. Then, through the hard mask n ^- field insulating film 124, and 131 made of LOCOS film thermal oxidation treatment on the surface of the type epitaxial layer 117 is applied is formed. After that, the hard mask is removed.

Then, n ^- thermal oxidation treatment on the surface of the type epitaxial layer 117 is subjected is in the gate insulating film 132 is formed. At this time, the gate insulating film 132 is formed so as to be connected to the field insulating films 124 and 131. Next, the material for the gate electrode 133 ^{is selectively formed on the n-} type epitaxial layer 117, and the gate electrode 133 and the protection diode 137 (not shown) are formed.

Next, an n ^- type well region 126 and a p ^- type well region 127 are formed. To form the n ^- type well region 126, first, an ion implantation mask (not shown) having an opening selectively in the region where ^{the n-type well region 126 should be formed is formed.} Then, n-type impurities are implanted into the n ^- type epitaxial layer 117 through the ion implantation mask. Thus, n ^- -type well region 126 is formed. After the n ^- type well region 126 is formed, the ion implantation mask is removed. Further, in the same procedure, an ion implantation mask (not shown) having an opening selectively in the region ^{where the p-type well region 127 should be formed is formed.} Then, the p-type impurity is implanted into the n ^- type epitaxial layer 117 through the ion implantation mask. As a result, the p ^- type well region 127 is formed. After the p ^- type well region 127 is formed, the ion implantation mask is removed.

Next, an ^n- type impurity region 130 is formed in the inner region of ^{the p-type well region 127.} In order ^{to form the n-} type impurity region 130, first, an ion implantation mask (not shown) having an opening selectively in the region where ^{the n-type impurity region 130 should be formed is formed.} Then, n-type impurities are ^{injected into the p-} type well region 127 through the ion implantation mask. As a result, the ^n- type impurity region 130 is formed in ^{the inner region of the p-} type well region 127. After the n ^- type impurity region 130 is formed, the ion implantation mask is removed.

Next, an n ⁺ type drain region 128 and an n ⁺ type source region 129 are selectively formed in ^{each inner region of the n −} type well region 126 and the p ⁻ type well region 127, respectively. To form the n ⁺ type drain region 128 and the n ⁺ type source region 129, first, an ion implantation mask having an opening selectively in the region where ^{the n +} type drain region 128 and the n ^{+ type source region 129 should be formed (} (Not shown) is formed. Then, n-type impurities are implanted into the n ^- type well region 126 and the p ^- type well region 127 through the ion implantation mask. As a result, the n ⁺ type drain region 128 and the n ⁺ type source region 129 are formed. After the n ⁺ type drain region 128 and the n ⁺ type source region 129 are formed, the ion implantation mask is removed.

Next, as shown in FIG. 26B, an insulating material is deposited so as to cover the gate electrode 133 to form the first interlayer film 140. Next, plugs 149, 150, 152, and 153 are formed so as to penetrate the first interlayer film 140. Next, after the etching stop film 143 is formed on the first interlayer film 140, the source first metal 145, the drain first metal 146, and the gate first metal 147 are selectively formed.

Next, as shown in FIG. 26C, an insulating material is deposited so as to cover the source first metal 145, the drain first metal 146, and the gate first metal 147 to form the second interlayer film 141. Next, the plugs 158 and 159 are formed so as to penetrate the second interlayer film 141. Next, the source top metal 155, the drain top metal 156, and the gate top metal 157 are selectively formed on the second interlayer film 141.

Next, an insulating material is deposited so as to cover the source top metal 155, the drain top metal 156, and the gate top metal 157 to form the surface insulating film 103. After that, the pad openings 160 to 162 are formed by selectively removing the surface insulating film 103.
Next, as shown in FIG. 26D, the semiconductor substrate 102 is selectively removed along a preset element boundary line, for example, by plasma etching. As a result, a groove 168 having a predetermined depth reaching from the surface 102A of the semiconductor substrate 102 to the middle of the thickness of the semiconductor substrate 102 is formed between the adjacent transistor regions. The groove 168 is partitioned by a pair of side walls 168A facing each other and a bottom wall 168B connecting the lower ends of the pair of side walls 168A (the ends of the semiconductor substrate 102 on the back surface 102B side).

Next, as shown in FIG. 26E, an insulating film made of SiN is formed over the entire region on the surface 102A side of the semiconductor substrate 102 by the CVD method. At this time, the insulating film is also formed on the entire inner peripheral surface of the groove 168 (the side wall 168A and the bottom wall 168B described above). As a result, a portion covering the side surfaces 102C to 102F of the surface insulating film 103 is formed.
Next, Ni, Pd and Au are sequentially plated and grown from the source pad 108, the drain pad 107 and the gate pad 109 exposed from the pad openings 160 to 162 by electroless plating. As a result, as shown in FIG. 26E, a source terminal 163, a drain terminal 164 (not shown) and a gate terminal (not shown) made of a laminated film of Ni layer 165 / Pd layer 166 / Au layer 167 are formed. ..

Next, a support tape (not shown) is attached to the front surface 102A side of the semiconductor substrate 102 in the wafer state, and in that state, the semiconductor substrate 102 is ground from the back surface 102B side. When the semiconductor substrate 102 is thinned until it reaches the upper surface of the bottom wall 168B of the groove 168 by grinding, there is nothing connecting adjacent semi-finished products, so that the semiconductor substrate 102 is divided with the groove 168 as a boundary. Through the above steps, as shown in FIG. 26F, individual pieces of the semiconductor device 101 are obtained.

Although one embodiment of the present invention has been described above with reference to FIGS. 16 to 26F, the present invention can also be implemented in other embodiments.
For example, the semiconductor substrate 102 does not have to have a rectangular shape in a plan view, and may be another quadrangle such as a square shape in a plan view.
Further, the drain pad 107 may be circular, semi-circular or the like in a plan view, and the source pad 108 and the gate pad 109 may be circular, triangular or the like in a plan view, for example.

Further, in the above-described embodiment, only the structure of the MOSFET is shown as an example of the structure of the semiconductor device 101 element, but the element built in the semiconductor device 101 is, for example, another element such as an IGBT or a bay polar transistor. You may.
The semiconductor device of the present invention can be suitably used for wearable devices (for example, smartphones, tablet PCs, etc.), which are applications for which miniaturization is particularly required.

In addition, various design changes can be made within the scope of the matters described in the claims.

1 Semiconductor package 6 Semiconductor chip 7 Encapsulating resin 9 Gate wiring 10 1st source wiring 11 2nd source wiring 12 Gate pad 13 Gate finger 16 1st area 17 2nd area 22 Semiconductor layer 23p ⁺ type semiconductor substrate 24p type epitaxial Layer 25 1st active region 26 2nd active region 27 Central region 28 n-type body region 29 p-type drain region 30 Gate trench 31 1st unit cell 32 2nd unit cell 33 3rd unit cell 34 1st gate trench 35 2nd Gate trench 36 3rd gate trench 37 p ⁺ type source area 39 p ⁺ type source area 41 Gate insulation film 42 Gate electrode 43 1st gate electrode 44 2nd gate electrode 45 3rd gate electrode 53 Drain electrode 54 1st parasitic diode 55 2nd parasitic diode 56 3rd gate electrode 57 1st unit cell row 58 2nd unit cell row 59 Tooth part 60 Tooth part 61 Drain terminal 62 1st source terminal 63 2nd source terminal 64 Gate terminal 65 1st semiconductor chip 66th 2 Semiconductor chip 67 Encapsulating resin Tr1 1st transistor Tr2 2nd transistor

Claims (7)

Enhancement type 1p channel type MISFET and
Enhancement type 2p channel type MISFET and
A drain conductor commonly electrically connected to the drain of the first p-channel type MISFET and the second p-channel type MISFET,
The first source conductor electrically connected to the source of the first p-channel type MISFET and
A second source conductor electrically connected to the source of the second p-channel MOSFET,
Look including a gate conductor that is electrically connected in common to gates of said first 1p channel type MISFET and the first 2p-channel type MISFET,
A semiconductor layer having a common p-type drain region with respect to the first p-channel type MISFET and the second p-channel type MISFET is included.
The first p-channel type MISFET has a first n-type body region formed on the surface portion of the semiconductor layer, a first p-type source region formed on the surface portion of the first n-type body region, and the first n-type body region. Includes a first gate electrode facing the
The second p-channel type MISFET has a second n-type body region formed on the surface portion of the semiconductor layer, a second p-type source region formed on the surface portion of the second n-type body region, and the second n-type body region. Includes a second gate electrode facing
The drain conductor includes a drain electrode formed on the back surface of the semiconductor layer and connected to the p-type drain region.
The first source conductor includes a first source electrode connected to the first p-type source region.
The second source conductor includes a second source electrode that is disposed separately from the first source electrode and is connected to the second p-type source region.
The gate conductor includes a gate wiring commonly connected to the first gate electrode and the second gate electrode in the semiconductor layer.
A linear first unit cell sequence composed of a plurality of first unit cells of the first p-channel type MISFET, and
The second p-channel type MISFET includes a linear second unit cell sequence composed of a plurality of second unit cells.
The first unit cell row and the second unit cell row are arranged alternately at intervals from each other.
The first source electrode is formed in a comb-like shape having a base end portion on one end side of the first unit cell row and the second unit cell row and having a tooth portion on each of the first unit cell rows.
The second source electrode has a base end portion on the other end side of the first unit cell row and the second unit cell row, and has a tooth portion on each of the second unit cell rows, and has a comb-like shape. A semiconductor device formed in a comb-teeth shape that meshes with the first source electrode at intervals. Enhancement type 1p channel type MISFET and
Enhancement type 2p channel type MISFET and
It has a common p-type drain region for the first p-channel type MISFET and the second p-channel type MISFET, and is arranged adjacent to the first active region for the first p-channel type MISFET and the first active region. The second active region for the second p-channel MOSFET and the semiconductor layer formed in a rectangular shape in a plan view are included.
The first p-channel type MISFET has a first n-type body region formed on the surface portion of the semiconductor layer, a first p-type source region formed on the surface portion of the first n-type body region, and the first n-type body region. Includes a first gate electrode facing the
The second p-channel type MISFET has a second n-type body region formed on the surface portion of the semiconductor layer, a second p-type source region formed on the surface portion of the second n-type body region, and the second n-type body region. Includes a second gate electrode facing
Is formed on the rear surface of the front Symbol semiconductor layer, a drain electrode connected to the p-type drain region,
A first source electrode connected to the front Symbol the 1p-type source region,
Is arranged separately from the previous SL first source electrode, a second source electrode connected to the first 2p-type source region,
One gate pad arranged at the center of at least one side of the pair of semiconductor layers facing each other in a plan view, and the other of the pair of sides connected to the gate pad. Includes a gate wiring that includes a gate finger that extends an area between the first active region and the second active region towards one side.
A semiconductor device in which the gate finger is commonly electrically connected to the first gate electrode and the second gate electrode in a region between the first active region and the second active region . A first gate trench formed directly below the first active region,
A second gate trench formed directly below the second active region, and
A third gate trench formed between the first gate trench and the second gate trench and commonly connecting the first gate trench and the second gate trench is included.
The first gate electrode includes an electrode embedded in the first gate trench.
The second gate electrode includes an electrode embedded in the second gate trench.
The semiconductor device according to claim 2 , wherein the gate wiring includes an electrode embedded in the third gate trench. A first gate trench formed directly below the first active region,
Includes a second gate trench formed directly below the second active region.
The first gate electrode includes an electrode embedded in the first gate trench.
The second gate electrode includes an electrode embedded in the second gate trench.
The gate wiring is formed in a region on the semiconductor layer, straddles the first gate electrode and the second gate electrode along the surface of the semiconductor layer, and the first gate electrode and the second gate electrode, respectively. The semiconductor device according to claim 2 , further comprising an electrode connected from above. A claim that, in the region between the first active region and the second active region, a region on the back surface side of the semiconductor layer with respect to the front surface portion of the semiconductor layer is occupied by the common p-type drain region. Item 2. The semiconductor device according to any one of Items 2 to 4. The semiconductor device according to any one of claims 2 to 5 , wherein the first source electrode and the second source electrode are arranged in a region separated from each other by the gate finger. The semiconductor device according to any one of claims 1 to 6.
A semiconductor package including a sealing resin that seals all or a part of the semiconductor device.

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