WO2024018715A1 - Semiconductor device - Google Patents

Abstract

A semiconductor device (1) comprises: a semiconductor layer (40) that is rectangular in a plan view; a first vertical MOS transistor (10) formed in a first region (A1) of the semiconductor layer (40); and a second vertical MOS transistor (20) that is formed in a second region (A2) adjacent to the first region (A1) in a plan view. In a plan view, the first and second regions (A1, A2) are the one and the other that divide the area of the semiconductor layer (40) into two equal parts. The shape formed by a first gate wiring (114) and a first gate electrode (19) provided in the first region (A1) and the shape formed by a second gate wiring (124) and a second gate electrode (29) provided in the second region (A2) are not line-symmetrical to each other if the boundary line between the first region (A1) and the second region (A2) is the symmetry axis, and are not point-symmetrical to each other if the center of the semiconductor layer (40) is the symmetry center.

Description

semiconductor equipment

The present disclosure relates to a semiconductor device, and particularly relates to a chip size package type semiconductor device.

In order to protect lithium ion batteries from overcharging and/or overdischarging, dual-configuration vertical MOS transistors that can control bidirectional conduction with one chip are used. Patent Document 1 and Patent Document 2 disclose the structure of a dual-configuration vertical MOS transistor, in which each of the two vertical MOS transistors included in one chip is arranged in a line-symmetrical or point-symmetrical arrangement in a plan view. The structure is shown.

Japanese Patent Application Publication No. 2002-368217 Japanese Patent Application Publication No. 2002-368219

Dual-configuration vertical MOS transistors that can control bidirectional conduction and are used to protect lithium-ion batteries from overcharging and/or overdischarging have high switching responsiveness while maintaining ESD (Electro Static Discharge) resistance. In some cases, it may be necessary to increase the

In order to solve the above problems, a semiconductor device according to the present disclosure is a chip size package type semiconductor device that can be mounted face-down, and includes a semiconductor substrate, a semiconductor layer formed on the semiconductor substrate, a first vertical MOS transistor having a plurality of first gate trenches formed in a first region of the semiconductor layer; and a second vertical MOS transistor adjacent to the first region in a plan view of the semiconductor layer. a second vertical MOS transistor having a plurality of second gate trenches formed in a region; and a metal layer formed in contact with a back surface of the semiconductor substrate, the semiconductor substrate The semiconductor layer is a common drain region of the first vertical MOS transistor and the second vertical MOS transistor, and in the plan view, the semiconductor layer has a rectangular shape, and the length of the long side of the semiconductor layer is the same as the first vertical MOS transistor. The first region and the second region bisect the semiconductor layer in area so that the length of the longest side of the sides forming the outer periphery of the region coincides with the length of the longest side, and The first region includes a first gate electrode that controls conduction of the first vertical MOS transistor, and a first gate wiring connected to the first gate electrode, and the second region includes a first gate electrode that controls conduction of the first vertical MOS transistor; is provided with a second gate electrode that controls conduction of the second vertical MOS transistor, and a second gate wiring connected to the second gate electrode, and in the plan view, the first The shape formed by the gate electrode and the first gate wiring and the shape formed by the second gate electrode and the second gate wiring are the boundary line between the first region and the second region. The shape formed by the first gate electrode and the first gate wiring, and the shape formed by the second gate electrode and the second gate wiring in the plan view are not in a relationship of line symmetry with the axis of symmetry being The shape formed by is characterized in that the semiconductor device is not in a point-symmetrical relationship with the center of the semiconductor layer as the center of symmetry.

According to the above configuration, in a dual-configuration vertical MOS transistor that can control bidirectional conduction, one vertical MOS transistor has improved switching response, the other vertical MOS transistor has improved ESD resistance, and the surface The first vertical MOS transistor and the second vertical MOS transistor can be distinguished relatively easily from the side (pad surface side).

Further, a semiconductor device according to the present disclosure is a chip size package type semiconductor device that can be mounted face-down, and includes a semiconductor substrate, a semiconductor layer formed on the semiconductor substrate, and a first region of the semiconductor layer. a first vertical MOS transistor having a plurality of first gate trenches formed in the semiconductor layer; a second vertical MOS transistor having a second gate trench; and a metal layer formed in contact with the back surface of the semiconductor substrate, and the semiconductor substrate is connected to the first vertical MOS transistor and the metal layer formed in contact with the back surface of the semiconductor substrate. A common drain region of the second vertical MOS transistor, and in the planar view, the first region and the second region are one and the other dividing the semiconductor layer into two in terms of area, In the plan view, the first region is adjacent to a first active region in which a conduction channel of the first vertical MOS transistor is formed, and is adjacent to the first active region. and a first peripheral region surrounding the second vertical MOS transistor, and in the plan view, the second region includes a second active region in which a conduction channel of the second vertical MOS transistor is formed, and a first peripheral region surrounding the second vertical MOS transistor. and a second peripheral region adjacent to the active region and surrounding the second active region, and in the plan view, the shape of the first structure provided in the first active region is the same as that of the first structure. a second structure having the same function in the second vertical MOS transistor as the structure has in the first vertical MOS transistor, the second structure provided in the second active region; Compared to the shape of the body, there is no line symmetry with the boundary line between the first region and the second region as the axis of symmetry, and there is point symmetry with the center of the semiconductor layer as the center of symmetry. The shape of the first structure has an unrelated portion, and in the plan view, the portion that has the shape of the first structure is at a position opposite to the side of the first structure facing the second active region. The invention is characterized in that it is a semiconductor device included in a computer.

According to the above configuration, in a dual-configuration vertical MOS transistor that can control bidirectional conduction, the first vertical MOS transistor is and the second vertical MOS transistor can be distinguished relatively easily.

According to the present disclosure, in a dual-configuration vertical MOS and transistor that can control bidirectional conduction, a first vertical MOS and transistor and a second vertical MOS transistor are compared from the front surface side (pad surface side). can be easily distinguished.

FIG. 1 is a schematic cross-sectional view showing an example of the structure of a semiconductor device according to the first embodiment. FIG. 2A is a schematic plan view showing an example of the structure of a semiconductor device according to a typical example of the first embodiment. FIG. 2B is a schematic cross-sectional diagram showing the main current flowing through the semiconductor device according to the first embodiment. FIG. 3A is a schematic plan view showing an example of the structure of a semiconductor device according to a typical example of the first embodiment. FIG. 3B is a schematic plan view showing an example of the structure of a semiconductor device according to a typical example of the first embodiment. FIG. 4A is a schematic plan view of a substantially unit configuration of the first transistor according to the first embodiment. FIG. 4B is a schematic perspective view of a substantially unit configuration of the first transistor according to the first embodiment. FIG. 5A is a schematic plan view showing an example of the structure of a semiconductor device according to Modification 1 of Embodiment 1. FIG. 5B is a schematic plan view showing an example of the structure of a semiconductor device according to Modification 1 of Embodiment 1. FIG. 6 is a schematic plan view showing an example of the structure of a semiconductor device according to Modification 2 of Embodiment 1. FIG. 7A is a schematic plan view showing an example of the structure of a semiconductor device according to Modification 3 of Embodiment 1. FIG. 7B is a schematic plan view showing an example of the structure of a semiconductor device according to Modification 3 of Embodiment 1. FIG. 8 is a schematic plan view showing an example of the structure of the semiconductor device according to the second embodiment. FIG. 9A is a schematic plan view showing an example of the structure of a semiconductor device according to Embodiment 3. FIG. 9B is a schematic plan view showing an example of the structure of the semiconductor device according to the third embodiment. FIG. 9C is a schematic plan view showing an example of the structure of the semiconductor device according to the third embodiment. FIG. 9D is a schematic plan view showing the structure of a comparative example semiconductor device according to the third embodiment. FIG. 9E is a schematic plan view showing an example of the structure of the semiconductor device according to the third embodiment. FIG. 9F is a schematic plan view showing an example of the structure of the semiconductor device according to the third embodiment. FIG. 9G is a schematic plan view showing an example of the structure of the semiconductor device according to the third embodiment. FIG. 9H is a schematic plan view showing an example of the structure of the semiconductor device according to the third embodiment.

Hereinafter, a specific example of a semiconductor device according to one embodiment of the present disclosure will be described with reference to the drawings. The embodiments shown here are all specific examples of the present disclosure. Therefore, the numerical values, shapes, components, arrangement of components, and connection forms shown in the following embodiments are merely examples, and are not intended to limit the present disclosure. Furthermore, each figure is a schematic diagram and is not necessarily strictly illustrated. In each figure, substantially the same configurations are denoted by the same reference numerals, and overlapping explanations will be omitted or simplified.

(Embodiment 1)
[1. Structure of semiconductor device]
FIG. 1 is a cross-sectional view showing an example of the structure of a semiconductor device. FIG. 2A is a plan view of a typical example, and the size and shape of the semiconductor device are only an example, except that the semiconductor device is rectangular. The size, shape, and arrangement of the pads are also examples. FIG. 2B is a cross-sectional view schematically showing the main current flowing through the semiconductor device. 1 and 2B are cross-sections taken along line II in FIG. 2A. By the way, in the present disclosure, the term rectangle is defined as not including square. In cases where the shape may be rectangular or square, the term "rectangle" shall be used to distinguish between the shapes.

As shown in FIGS. 1 and 2A, the semiconductor device 1 includes a semiconductor substrate 32, a metal layer 30, and a first region A1 formed in a low concentration impurity layer 33 formed on the semiconductor substrate 32. 1 vertical MOS transistor 10 (hereinafter also referred to as "transistor 10") and a second vertical MOS transistor 20 (hereinafter referred to as "transistor 20") formed in the second region A2 in the low concentration impurity layer 33. ).

Here, as shown in FIG. 2A, the first region A1 and the second region A2 are adjacent to each other in a plan view of the semiconductor layer 40 and bisect the semiconductor layer 40 in area. . In FIG. 2A, a virtual boundary line 90 between the first area A1 and the second area A2 is shown as a dotted line (for clarity, the dotted line indicating the boundary line 90 extends to the outside of the semiconductor layer 40). (shown). In the first embodiment, the boundary line 90 is a straight line in a direction parallel to the long sides of the semiconductor layer 40 in plan view. In addition, in FIG. 2A and FIG. 5A, which will be described later, the broken lines indicating the first area A1 and the second area A2 are not exactly aligned with the semiconductor layer 40 and the boundary line 90 for ease of understanding, but with a slight margin. Although shown on the inside, the outer periphery of the first region A1 and the outer periphery of the second region A2 substantially coincide with the outer periphery of the semiconductor layer 40 and the boundary line 90.

In the present disclosure, the semiconductor substrate 32 and the low concentration impurity layer 33 are collectively referred to as a semiconductor layer 40. The semiconductor substrate 32 is disposed on the back side of the semiconductor layer 40 and is made of first conductivity type silicon containing first conductivity type impurities. The low concentration impurity layer 33 is disposed on the surface side of the semiconductor layer 40 , is formed in contact with the semiconductor substrate 32 , and contains impurities of a first conductivity type at a concentration lower than the concentration of impurities of the first conductivity type of the semiconductor substrate 32 . and is of the first conductivity type.

The low concentration impurity layer 33 may be formed on the semiconductor substrate 32 by epitaxial growth, for example. Note that the low concentration impurity layer 33 is also a drift layer common to the transistor 10 and the transistor 20, and is sometimes referred to as a drift layer in this specification.

The metal layer 30 is formed in contact with the back side of the semiconductor layer 40 (semiconductor substrate 32), and is made of silver (Ag) or copper (Cu). Note that the metal layer 30 may contain a trace amount of an element other than metal that is mixed as an impurity in the manufacturing process of the metal material. Moreover, the metal layer 30 may or may not be formed on the entire back surface side of the semiconductor layer 40 (semiconductor substrate 32).

As shown in FIGS. 1 and 2A, a first body region 18 containing an impurity of a second conductivity type different from the first conductivity type is formed in the first region A1 of the low concentration impurity layer 33. A first source region 14 containing impurities of a first conductivity type, a first gate conductor 15, and a first gate insulating film 16 are formed in the first body region 18. The first gate insulating film 16 includes a plurality of layers formed at a depth from the upper surface of the semiconductor layer 40 to a part of the low concentration impurity layer 33 through the first source region 14 and the first body region 18. The first gate conductor 15 is formed inside the first gate trench 17 and on the first gate insulating film 16 .

The first source electrode 11 consists of a portion 12 and a portion 13, and the portion 12 is connected to the first source region 14 and the first body region 18 via the portion 13. The first gate conductor 15 is a buried gate electrode buried inside the semiconductor layer 40 and is electrically connected to the first gate pad 119 .

The portion 12 of the first source electrode 11 is a layer that is bonded with solder during reflow in face-down mounting, and is made of a metal material containing one or more of nickel, titanium, tungsten, and palladium, as a non-limiting example. It may be composed of. The surface of the portion 12 may be plated with gold or the like.

The portion 13 of the first source electrode 11 is a layer that connects the portion 12 and the semiconductor layer 40, and is made of a metal material containing one or more of aluminum, copper, gold, and silver, as a non-limiting example. may be configured.

A second body region 28 containing a second conductivity type impurity is formed in the second region A2 of the low concentration impurity layer 33. In the second body region 28, a second source region 24 containing impurities of a first conductivity type, a second gate conductor 25, and a second gate insulating film 26 are formed. The second gate insulating film 26 includes a plurality of layers formed at a depth from the upper surface of the semiconductor layer 40 to a part of the low concentration impurity layer 33, penetrating the second source region 24 and the second body region 28. The second gate conductor 25 is formed inside the second gate trench 27 and on the second gate insulating film 26 .

The second source electrode 21 consists of a portion 22 and a portion 23, and the portion 22 is connected to the second source region 24 and the second body region 28 via the portion 23. The second gate conductor 25 is a buried gate electrode buried inside the semiconductor layer 40 and is electrically connected to the second gate pad 129 .

The portion 22 of the second source electrode 21 is a layer that is bonded with solder during reflow in face-down mounting, and is made of a metal material containing one or more of nickel, titanium, tungsten, and palladium, for example and without limitation. It may be composed of. The surface of the portion 22 may be plated with gold or the like.

The portion 23 of the second source electrode 21 is a layer that connects the portion 22 and the semiconductor layer 40, and is made of a metal material containing one or more of aluminum, copper, gold, and silver, as a non-limiting example. may be configured.

Due to the above configuration of the transistor 10 and the transistor 20, the semiconductor substrate 32 functions as a common drain region in which the first drain region of the transistor 10 and the second drain region of the transistor 20 are shared. A part of the low concentration impurity layer 33 on the side that is in contact with the semiconductor substrate 32 may also function as a common drain region. Further, the metal layer 30 functions as a common drain electrode in which the drain electrode of the transistor 10 and the drain electrode of the transistor 20 are shared.

As shown in FIG. 1, the first body region 18 is covered with an interlayer insulating layer 34 having an opening, and the first source electrode 11 is connected to the first source region 14 through the opening of the interlayer insulating layer 34. A portion 13 is provided. The interlayer insulating layer 34 and the first source electrode portion 13 are covered with a passivation layer 35 having an opening, and a portion 12 is provided that is connected to the first source electrode portion 13 through the opening of the passivation layer 35. .

The second body region 28 is covered with an interlayer insulating layer 34 having an opening, and a portion 23 of the second source electrode 21 is provided to be connected to the second source region 24 through the opening of the interlayer insulating layer 34. There is. The interlayer insulating layer 34 and the second source electrode portion 23 are covered with a passivation layer 35 having an opening, and a portion 22 is provided that is connected to the second source electrode portion 23 through the opening of the passivation layer 35. .

Therefore, the plurality of first source pads 111 and the plurality of second source pads 121 are regions where the first source electrode 11 and the second source electrode 21 are partially exposed on the surface of the semiconductor device 1, so-called terminals. refers to the part. Similarly, the one or more first gate pads 119 and the one or more second gate pads 129 are connected to the first gate electrode 19 (not shown in FIGS. 1, 2A, and 2B) and the second gate pad 129, respectively. This refers to a region where the gate electrode 29 (not shown in FIGS. 1, 2A, and 2B) is partially exposed on the surface of the semiconductor device 1, that is, a so-called terminal portion.

In the semiconductor device 1, for example, the first conductivity type is N type and the second conductivity type is P type, and the first source region 14, second source region 24, semiconductor substrate 32, and low concentration impurity layer 33 are The first body region 18 and the second body region 28 may be an N-type semiconductor, and the first body region 18 and the second body region 28 may be a P-type semiconductor.

Further, in the semiconductor device 1, for example, the first conductivity type is P type, the second conductivity type is N type, and the first source region 14, the second source region 24, the semiconductor substrate 32, and the low concentration impurity layer. 33 is a P-type semiconductor, and the first body region 18 and the second body region 28 may be N-type semiconductors.

FIG. 3A shows the semiconductor layer 40 (with low concentration impurity) in the first body region 18, the second body region 28, the first active region 112, and the second active region 122 among the components of the semiconductor device 1. FIG. 7 is a plan view showing a typical example of the shape of layer 33) in plan view. In FIG. 3A and FIGS. 3B, 5B, 6, and 7B, which will be described later, the structure of the passivation layer 35, the first source The electrode 11, the second source electrode 21, and the interlayer insulating layer 34 are omitted so that they appear to be transparent. Further, illustration of the first source region 14 and the second source region 24 is also omitted.

The first active region 112 is a minimum area that includes all parts where a conduction channel is formed when a voltage equal to or higher than a threshold voltage is applied to the first gate electrode 19 (first gate conductor 15) of the transistor 10. refers to The portion where the conduction channel is formed is a portion where each of the plurality of first gate trenches 17 is adjacent to the first source region 14. In a plan view of the semiconductor layer 40, the first active region 112 is included in the first body region 18.

The second active region 122 is the minimum area that includes all the parts where a conduction channel is formed when a voltage equal to or higher than the threshold voltage is applied to the second gate electrode 29 (second gate conductor 25) of the transistor 20. Point. The portion where the conduction channel is formed is a portion where each of the plurality of second gate trenches 27 is adjacent to the second source region 24 . In a plan view of the semiconductor layer 40 , the second active region 122 is included in the second body region 28 .

A region of the first region A1 that is outside the first active region 112 and surrounds the first active region 112 is called a first peripheral region 113, and a region of the second region A2 that is outside the first active region 112 and surrounds the first active region 112 is called a first peripheral region 113. A region outside the active region 122 and surrounding the second active region 122 is referred to as a second peripheral region 123. As shown in FIG. 3B, the first peripheral region 113 includes a first gate electrode 19 and a first gate wiring ( A first gate runner) 114 is provided. The second peripheral region 123 has a second gate electrode 29 connected to the second gate electrode 29 via a second gate resistance element 125 in series, and a second gate electrode 29 surrounding the second active region 122 . A gate wiring (second gate runner) 124 is provided.

Note that, as shown in FIG. 3B, a first gate resistance element 115 may be installed at a position between the first gate electrode 19 and the first gate wiring (first gate runner) 114. However, it should be noted that the first gate electrode 19 and the first gate wiring (first gate runner) 114 are directly connected without electrically intervening the first gate resistance element 115. be. Therefore, the first gate wiring (first gate runner) 114 and the second gate wiring (second gate runner) 124 are not symmetrical in shape or arranged symmetrically in plan view.

The gate resistance element is installed with the expectation that it will have a protective function that will prevent the transistor from being destroyed when excessive voltage is applied to the gate electrode. That is, it is installed to increase ESD resistance. As in the first embodiment, even if the first gate resistance element 115 is installed, it is electrically connected between the first gate electrode 19 and the first gate wiring (first gate runner) 114. Otherwise, no protection function is performed in transistor 10. Note that the first gate resistance element 115 and the second gate resistance element 125 are made of polysilicon injected with a dopant, and may be formed simultaneously with the first gate conductor 15 and the second gate conductor 25. .

The first gate wiring (first gate runner) 114 and the second gate wiring (second gate runner) 124 are made of dopant-injected polysilicon or the first gate electrode 19 and the second gate electrode 29. The gate conductor 15 is made of the same metal as the gate conductor 15 and the gate conductor 25 is connected to the first gate conductor 15 and the second gate conductor 25, respectively.

In the first peripheral region 113, a first EQR (EQUI Potential Ring) 116 is located further on the outer peripheral side of the first gate wiring (first gate runner) 114, and similarly, in the second peripheral region 123, A second EQR 126 may be provided further on the outer peripheral side of the second gate wiring (second gate runner) 124.

The first EQR 116 is installed at the outermost periphery of the first area A1, and the second EQR 126 is installed at the outermost periphery of the second area A2 so as to surround the first active area 112 and the second active area 122, respectively. Ru. The first EQR 116 and the second EQR 126 are each formed of a metal species, and are connected to the first gate electrode 19 and the second gate electrode 29 or the first source electrode 11 and the second source electrode 21. It is formed so that it has the same potential as the drain region 32. At the boundary between the first area A1 and the second area A2, the first EQR 116 and the second EQR 126 may be common.

The first EQR 116 is installed with the expectation that it will have a function of stopping leakage current from flowing between the outside and the first active region 112 with respect to the transistor 10 . Further, the second EQR 126 is installed with the expectation that it will have a function of stopping leakage current from flowing between the outside and the second active region 122 with respect to the transistor 20 .

FIG. 3B schematically shows the first gate trench 17 (first gate conductor 15) and the second gate trench 27 (second gate conductor 25). In the first embodiment, both the first gate trench 17 (first gate conductor 15) and the second gate trench 27 (second gate conductor 25) are parallel to the short side of the semiconductor device 1 in plan view. It extends in the direction of

In FIG. 3B, the circles at both ends of the black line indicating the first gate trench 17 (first gate conductor 15) indicate that the first gate trench 17 (first gate conductor 15) It is schematically shown that it is connected to the wiring 114. Similarly, the circles at both ends of the black line indicating the second gate trench 27 (second gate conductor 25) indicate that the second gate trench 27 (second gate conductor 25) is connected to the second gate wiring. 124 is schematically shown.

For simplicity, in FIG. 3B and FIGS. 5B, 6, and 7B described later, the first gate trench 17 (first gate conductor 15) and the second gate trench 27 (second gate conductor 25) are the same. Only parts are shown. In reality, both the first gate trench 17 (first gate conductor 15) and the second gate trench 27 (second gate conductor 25) are located inside the first active region 112 and the second active region 122, respectively. It is repeatedly formed over the entire surface.

[2. Operation of vertical MOS transistor with dual configuration]
In the following description, the conduction operation of the semiconductor device 1 will be described assuming that the transistor 10 and the transistor 20 are so-called N-channel transistors in which the first conductivity type is N type and the second conductivity type is P type.

FIGS. 4A and 4B are a plan view and a perspective view, respectively, of a substantially unit configuration of transistors 10 (or transistors 20) that are repeatedly formed in the X direction and Y direction of the semiconductor device 1. 4A and 4B, the semiconductor substrate 32, the metal layer 30, the passivation layer 35, the first source electrode 11 (or the second source electrode 21), and the interlayer insulating layer 34 are not shown for clarity. do not have.

Note that the Y direction is a direction parallel to the upper surface of the semiconductor layer 40 and in which the first gate trench 17 extends. Further, the X direction refers to a direction parallel to the upper surface of the semiconductor layer 40 and perpendicular to the Y direction. The Z direction refers to a direction that is perpendicular to both the X direction and the Y direction and indicates the height direction of the semiconductor device. In this disclosure, the Y direction may be referred to as a first direction, the X direction as a second direction, and the Z direction as a third direction.

As shown in FIGS. 4A and 4B, the transistor 10 includes a first connection portion 18a that electrically connects the first body region 18 and the first source electrode 11. The first connection portion 18a is a region of the first body region 18 where the first source region 14 is not formed, and contains the same second conductivity type impurity as the first body region 18. The first source regions 14 and the first connection portions 18a are alternately and periodically repeatedly arranged along the Y direction. The same applies to the transistor 20.

In the semiconductor device 1 , a high voltage is applied to the first source electrode 11 and a low voltage is applied to the second source electrode 21 , and the second gate electrode 29 (second gate conductor 25 ), a conduction channel is formed near the second gate insulating film 26 in the second body region 28. As a result, first source electrode 11 - first connection part 18a - first body region 18 - low concentration impurity layer 33 - semiconductor substrate 32 - metal layer 30 - semiconductor substrate 32 - low concentration impurity layer 33 - second A main current flows through the path of the conduction channel formed in the body region 28 - the second source region 24 - the second source electrode 21, and the semiconductor device 1 becomes conductive. Note that there is a PN junction at the contact surface between the second body region 28 and the low concentration impurity layer 33 in this conduction path, and it functions as a body diode. Furthermore, since this main current flows through the metal layer 30, by increasing the thickness of the metal layer 30, the cross-sectional area of the main current path can be expanded, and the on-resistance of the semiconductor device 1 can be reduced.

Similarly, in the semiconductor device 1, a high voltage is applied to the second source electrode 21 and a low voltage is applied to the first source electrode 11. When a voltage equal to or higher than the threshold voltage is applied to the gate conductor 15), a conduction channel is formed near the first gate insulating film 16 in the first body region 18. As a result, second source electrode 21 - second connection part 28a - second body region 28 - low concentration impurity layer 33 - semiconductor substrate 32 - metal layer 30 - semiconductor substrate 32 - low concentration impurity layer 33 - first A main current flows through the path of the conduction channel formed in the body region 18 - the first source region 14 - the first source electrode 11, and the semiconductor device 1 becomes conductive. Note that in this conduction path, there is a PN junction at the contact surface between the first body region 18 and the low concentration impurity layer 33, which functions as a body diode.

[3. Effects of semiconductor device in Embodiment 1]
In the following description, effects produced by the semiconductor device 1 in the first embodiment will be described.

As shown in FIG. 2A, the semiconductor device 1 shown as a typical example of the first embodiment has a rectangular shape in plan view, and the transistor 10 and the transistor 20 each have a rectangular shape. Furthermore, the transistor 10 is arranged so that the length of the long side of the semiconductor layer 40 matches the length of the longest side among the sides forming the outer periphery of the first region A1 in plan view. Similarly, the transistor 20 is arranged so that the length of the long side of the semiconductor layer 40 matches the length of the longest side among the sides forming the outer periphery of the second region A2 in plan view.

Further, as shown in FIG. 3B, the first gate trench 17 (first gate conductor 15) and the second gate trench 27 (second gate conductor 25) are parallel to the short side of the semiconductor layer 40 in plan view. extends in the direction of That is, both the transistor 10 and the transistor 20 are formed so that the finger length is as short as possible, and the gate resistance of each of the transistor 10 and the transistor 20 can be reduced.

Further, in the transistor 10, the first gate electrode 19 and the first gate wiring 114 are directly connected without using the first gate resistance element 115, so that the gate resistance can be further lowered. Therefore, the structure is such that the switching response of the transistor 10 can be improved.

In the transistor 20, the second gate electrode 29 and the second gate wiring 124 are connected through the second gate resistance element 125 in series, so the resistivity of the second gate resistance element 125 can be set appropriately. By doing so, the structure is such that the transistor 20 can be prevented from being destroyed by excessively applied voltage. In other words, it has a structure that can improve ESD resistance.

In a dual-configuration vertical MOS transistor used to protect a lithium-ion battery from overcharging and/or overdischarging, transistor 10 controls overcharging, transistor 20 controls overdischarge, and so on. The roles played by the transistors are different. Depending on how the battery protection circuit is designed, it may be necessary to improve the switching response of only one of the dual vertical MOS transistors. At this time, if the transistor 10 of the semiconductor device 1 in the first embodiment is used for this purpose, the demand for improved switching responsiveness can be met. At the same time, in the case of the transistor 20 that does not particularly need to improve the switching response, by interposing the second gate resistance element 125 between the second gate electrode 29 and the second gate wiring 124, excessive It is possible to prevent the transistor 20 from being destroyed by the applied voltage.

In a dual-configuration vertical MOS transistor, considering the respective uses of the transistor 10 and the transistor 20, the structure is created separately for one transistor 10 and the other transistor 20, and the switching response, which is originally in a trade-off relationship, is improved. The semiconductor device 1 is capable of achieving both ESD resistance and ESD resistance. Creating different structures means intentionally forming an asymmetric structure between the transistor 10 and the transistor 20.

However, in a dual-configuration vertical MOS transistor that is required to control bidirectional conduction, it is not preferable that the total gate widths of one transistor 10 and the other transistor 20 differ. Therefore, the asymmetric structure provided by transistor 10 and transistor 20 is preferably formed only in first peripheral region 113 and second peripheral region 123. Further, the structures of the first active region 112 and the second active region 122 are preferably symmetrical.

That is, the semiconductor device 1 according to the present disclosure is a chip size package type semiconductor device 1 that can be mounted face-down, and includes a semiconductor substrate 32, a low concentration impurity layer 33 formed on the semiconductor substrate 32, and a semiconductor substrate 32. 32 and the low concentration impurity layer 33 are collectively referred to as a semiconductor layer 40, a first vertical MOS transistor 10 having a plurality of first gate trenches 17 formed in a first region A1 of the semiconductor layer 40. In a plan view of the semiconductor layer 40, a second vertical MOS transistor 20 having a plurality of second gate trenches 27 formed in a second region A2 adjacent to the first region A1, and a semiconductor substrate. The semiconductor substrate 32 is a common drain region of the first vertical MOS transistor 10 and the second vertical MOS transistor 20, and the semiconductor substrate 32 is a common drain region of the first vertical MOS transistor 10 and the second vertical MOS transistor 20. , the semiconductor layer 40 has a rectangular shape, and the first region A1 and the first region The second region A2 is one half and the other half of the semiconductor layer 40, and the first region A1 has a first gate electrode 19 for controlling conduction of the first vertical MOS transistor 10, and a first gate electrode 19 for controlling conduction of the first vertical MOS transistor 10. , a first gate wiring 114 connected to the first gate electrode 19, and a second gate electrode 29 for controlling conduction of the second vertical MOS transistor 20, and a second gate wiring 114 connected to the first gate electrode 19. A second gate wiring 124 connected to the second gate electrode 29 is provided, and in a plan view, the shape formed by the first gate electrode 19 and the first gate wiring 114 is different from the shape formed by the second gate electrode 29 and the second gate wiring 124. The shape formed by the second gate wiring 124 is not in a line symmetrical relationship with the boundary line 90 between the first region A1 and the second region A2 as the axis of symmetry, and in plan view, the first gate electrode 19 The shape formed by the first gate wiring 114 and the shape formed by the second gate electrode 29 and the second gate wiring 124 are semiconductors that do not have a point-symmetric relationship with the center of the semiconductor layer 40 as the center of symmetry. The device is characterized by being device 1.

The boundary line 90 between the transistor 10 and the transistor 20 is an imaginary line that traces the center position of the distance between the portion 13 of the first source electrode 11 and the portion 23 of the second source electrode 21 in a plan view of the semiconductor layer 40. It may be regarded as a line, or it may be regarded as an EQR (the common part of the first EQR 116 and the second EQR 126) that may be provided at the central position, or it may be a finite width. It may be regarded as the interval itself. Even in the case of this interval, it can be recognized as a line when viewed with the naked eye or at low magnification.

Further, the center of the semiconductor layer 40 refers to the intersection of two diagonals of the semiconductor layer 40, which is rectangular in plan view.

In the first embodiment, in plan view, the shape is composed of the first gate electrode 19 and the first gate wiring 114, and the shape is composed of the second gate electrode 29 and the second gate wiring 124. The shape is an asymmetrical structure because one side is directly connected while the other is not. Asymmetrical means that the first region A1 and the second region A2 do not have a symmetrical relationship with the boundary line 90 as the axis of symmetry in plan view, and the center of the semiconductor layer 40 is the symmetrical axis. This means that they are not symmetrical about the center.

The configuration of Embodiment 1 has two advantages in addition to being able to improve the switching response of one transistor 10 and the ESD resistance of the other transistor 20. One is that the asymmetric structure is the structure provided in the first peripheral region 113 and the second peripheral region 123, so that one transistor 10 and the other transistor 20 can have the same total gate width. . Alternatively, the structures provided in the first active region 112 and the second active region 122 can be symmetrical. Therefore, in the bidirectional conduction of the dual-configuration vertical MOS transistor, it is possible to prevent bias from occurring depending on the direction of conduction.

Another advantage is that one transistor 10 can be distinguished from the other transistor 20 with the naked eye or by microscopic observation at low magnification. In a conventional dual-configuration vertical MOS transistor, one transistor 10 and the other transistor 20 usually have a symmetrical structure, and in an emergency such as when a malfunction occurs, one transistor 10 and the other transistor 20 It was difficult to distinguish from the surface side (pad surface side). In the present disclosure, since there is some difference in distinguishing one transistor 10 from the other transistor 20, it becomes easy to distinguish them from the pad surface side.

FIGS. 5A and 5B show a semiconductor device 1 in a first modification of the first embodiment. In the first modification shown in FIGS. 5A and 5B, the shapes of the first region A1 and the second region A2 are different in plan view compared to the typical example of the first embodiment shown in FIGS. 3A and 3B. A characteristic feature is that the boundary line 90 between the first area A1 and the second area A2 is not a straight line, but has a shape that has a cranking point.

As shown in FIG. 5A, in Modification 1 of Embodiment 1, the first area A1 and the second area A2 have polygonal shapes. Therefore, the shape of the transistor 10 and the shape of the transistor 20 are also polygonal in plan view. However, in Modification 1 as well, the semiconductor layer 40 has a rectangular shape in plan view, and the length of the long side of the semiconductor layer 40 matches the length of the longest side among the sides forming the outer periphery of the first region A1. As such, the first region A1 and the second region A2 are one and the other half of which the semiconductor layer 40 is divided into two in terms of area. Therefore, even with a configuration like Modification 1, the effects of the present disclosure can be achieved.

Note that the cut surface when cut along II in FIG. 5A is the same as that in FIG. 1.

In the semiconductor device 1 shown in the typical example of the first embodiment (FIGS. 3A and 3B), the first region A1 and the second region A2 each have a rectangular shape in plan view. Further, in a plan view, the direction in which the plurality of first gate trenches 17 (first gate conductors 15) extend is parallel to the short side direction of the semiconductor layer 40, and at the same time, the direction in which the plurality of first gate trenches 17 (first gate conductors 15) extend is parallel to the short side direction of the semiconductor layer 40, and at the same time 10) is also parallel to the short sides. Therefore, at least in the transistor 10, the finger length is shortened as much as possible, which is convenient for reducing the gate resistance as much as possible.

Note that when the semiconductor layer 40 has a square shape, there is no distinction between long sides and short sides of the semiconductor layer 40, so any side can be regarded as a long side. In this case as well, if the transistors 10 and 20 are arranged so that the boundary line 90 between the transistors 10 and 20 is in a straight line as shown in FIG. 3A, the transistors 10 and 20 will have a rectangular shape in plan view. Therefore, the effects of the present disclosure can be achieved.

Furthermore, in order to reduce the gate resistance in the transistor 10, it is desirable that the first gate trench 17 (first gate conductor 15) be connected to the first gate wiring 114 at both ends thereof. Therefore, in plan view, whether the semiconductor layer 40 is rectangular or square, the first area A1 and the second area A2 each have a rectangular shape and form the outer periphery of the first area A1. Among the four sides, the side that overlaps with the boundary line 90 is defined as a first side 301, the side opposite to the first side 301 is defined as a second side 302, and the side that is perpendicular to the first side 301 and the second side 302 However, if one side facing each other is the third side 303 and the other side is the fourth side 304 (see FIG. 2A), the first gate wiring 114 has at least the first side 301, the second side 302, and the fourth side 304. The plurality of first gate trenches 17 (first gate conductors 15) are connected to the first gate wiring 114 and the first side 301. It is desirable that the number of connections is maximized in the portion along the second side 302 and the portion along the second side 302.

Incidentally, when the first gate wiring 114 has a structure such as the first EQR 116 on the outer periphery, the approximate total length of each side forming the outer periphery of the first region A1 is the approximate total length of each side forming the outer periphery of the first region A1. The width for installing the structure, the installation margin required between the first gate wiring 114 and the structure, and the space required between the structure and each side forming the outer periphery of the first area A1. This refers to the length obtained by subtracting the installation margin etc. from the length of each side forming the outer periphery of the first area A1.

FIG. 6 shows a semiconductor device 1 in a second modification of the first embodiment. In Modification 2 shown in FIG. 6, compared to the typical example of Embodiment 1 shown in FIG. 3B, the direction in which the second gate trench 27 (second gate conductor 25) extends in plan view is different. A characteristic feature is that in plan view, the plurality of first gate trenches 17 (first gate conductors 15) extend in a direction parallel to the short side of the first region A1, while the plurality of first gate trenches 17 (first gate conductors 15) extend in a direction parallel to the short side of the first region A1. The second gate trench 27 (second gate conductor 25) extends in a direction parallel to the long side of the second region A2. That is, compared to the typical example of the first embodiment (FIG. 3B), the finger length of the transistor 20 is longer than that of the transistor 10, and the gate resistance of the transistor 20 is further increased compared to the gate resistance of the transistor 10. .

In the first embodiment, the purpose is to increase the switching response of the transistor 10 while increasing the ESD resistance of the transistor 20. Therefore, the structure of the second modification (FIG. 6) of the first embodiment has this purpose. It is more suitable for Note that in the second modification, it may not be possible to make the total gate widths of the transistor 10 and the transistor 20 the same. Further, the cut surface when cut along II in FIG. 6 is the same as that in FIG. 1.

As shown in the typical example of Embodiment 1 (FIG. 3B), the first gate wiring 114 may be connected to the first gate electrode 19 at a portion along the third side 303 in plan view. desirable. In such a structure, the potential of the first gate electrode 19 is uniformly transmitted to each of the portions along the first side 301 and the second side 302, and in each of the first gate conductors 15, It is possible to prevent uneven transmission of potential from both ends.

In contrast, FIGS. 7A and 7B show a semiconductor device 1 in a third modification of the first embodiment. As shown in FIGS. 7A and 7B, the first gate electrode 19 connects to the first gate wiring 114 either along the first side 301 or along the second side 302. You can. In such a structure, the potential of the first gate electrode 19 is applied to each first gate conductor 15 along the first side 301 or along the second side 302 where both ends thereof are connected. The gate resistance can be further reduced by being transmitted fastest from any of the two parts.

Note that the cut surface when cut along II in FIG. 7A is the same as that in FIG. 1.

In the semiconductor device 1 shown in the typical example (FIG. 3B), modification example 1 (FIG. 5B), modification example 2 (FIG. 6), and modification example 3 (FIG. 7B) of the present embodiment 1 described so far, in plan view In , the first gate electrode 19 and the first gate wiring 114 are continuous, the second gate electrode 29 and the second gate wiring 124 are not continuous, and the second gate electrode 29 is continuous. A second gate wiring 124 and a second gate resistance element 125 are connected in series. With such a structure, it is possible to improve the switching response of one transistor 10 and the ESD resistance of the other transistor 20.

(Embodiment 2)
Hereinafter, a semiconductor device 1A according to a second embodiment, which is configured by partially changing the semiconductor device 1 according to the first embodiment, will be described. Regarding the semiconductor device 1A according to the second embodiment, the same components as those of the semiconductor device 1 have already been explained and are given the same reference numerals, and detailed explanation thereof will be omitted, and we will focus on the differences from the semiconductor device 1. Explain.

FIG. 8 shows a semiconductor device 1A according to the second embodiment in a plan view. The cross section taken along line II in FIG. 8 is the same as that in FIG. 1. 8, the passivation layer 35, the first source electrode 11, the second source electrode 21, and the interlayer insulation Layer 34 is omitted to appear as if it were transparent. Further, illustration of the first source region 14 and the second source region 24 is also omitted. Further, for simplicity, only a portion of the first gate trench 17 (first gate conductor 15) and second gate trench 27 (second gate conductor 25) are shown in FIG. In reality, both the first gate trench 17 (first gate conductor 15) and the second gate trench 27 (second gate conductor 25) are located inside the first active region 112A and the second active region 122, respectively. It is repeatedly formed over the entire surface.

Compared to the first vertical MOS transistor 10 as a typical example according to the first embodiment shown in FIG. 3B, the first vertical MOS transistor 10A (also simply referred to as a transistor 10A) according to the second embodiment is As shown in , the first gate electrode 19A is connected to the first gate wiring 114A via the first gate resistance element 115 in series. Therefore, in the second embodiment, the first vertical MOS transistor 10A has a structure in which the ESD resistance can be increased to a level similar to that of the second vertical MOS transistor 20.

In addition, when the first transistor 10A is viewed from above, the first gate wiring 114A is located on the first side 301, the second side 302, and the third side 303 among the four sides forming the outer periphery of the first region A1. , but not along the fourth side 304 . In addition, in plan view, the first gate wiring 114A connects a portion along the first side 301 and a portion along the second side 302 at the shortest possible distance, in addition to the portion along the third side 303. (hereinafter referred to as a connecting portion 114b). Therefore, compared to the first active region 112 in the first embodiment, the first active region 112A has a shape divided by the connecting portion 114b.

The structure of the second embodiment shown in FIG. 8 has a shape composed of a first gate electrode 19A and a first gate wiring 114A, a second gate electrode 29 and a second gate wiring 124, in a plan view. The shape is such that only the first gate wiring 114A does not have a portion along the fourth side 304 in the first region A1, or only the first gate wiring 114A has a connecting portion 114b. It is neither symmetrically shaped nor symmetrically arranged.

Note that in the first region A1, the region other than the first active region 112A is divided into the first peripheral region 113A, so the connecting portion 114b is installed in the first peripheral region 113A. Furthermore, although FIG. 8 shows an example in which the connecting portion 114b is installed at only one location, the connecting portion 114b may be installed at multiple locations in the transistor 10A.

When the connecting portion 114b is provided, the voltage applied to the first gate electrode 19A of the first vertical MOS transistor 10A is reduced compared to the structure shown in the typical example of the first embodiment (FIG. 3B) in which the connecting portion 114b is not provided. The voltage can be quickly transmitted to the entire first gate wiring 114A. Therefore, the gate resistance of the first vertical MOS transistor 10A can be lowered. Therefore, a structure can be provided in which the switching response of the transistor 10A can be improved.

Furthermore, in plan view, in the first transistor 10A, the first EQR 116A is the first side 301, the second side 302, and the third side 303 of the four sides forming the outer periphery of the first region A1. Although they are installed continuously along substantially the entire length, they are not installed along the fourth side 304. Therefore, in the first transistor 10A, neither the first gate wiring 114A nor the first EQR 116A is installed in the portion along the fourth side 304 in the first region A1. Therefore, the first active region 112A has expanded to a portion along the fourth side 304 of the first region A1.

Since the first active region 112A has expanded toward the fourth side 304, in plan view, in the transistor 10A, among the plurality of first gate trenches 17, the first active region 112A is the one closest to the fourth side 304. The arrangement is such that the distance between the fourth side 304 and the third side 303 is smaller than the distance between the third side 303 and the one closest to the third side 303 among the plurality of first gate trenches 17 . ing.

With such a structure, the first active region 112A is expanded toward the fourth side 304 by reducing the first active region 112A in order to install the connecting portion 114b in the first region A1. You can compensate by doing this. Although the shapes are different, it is desirable that the first active region 112A and the second active region 122 have the same area. Furthermore, it is desirable that the total gate width of the first vertical MOS transistor 10A and the total gate width of the second vertical MOS transistor 20 be equal. In the case of such a structure, bidirectional conduction of the semiconductor device 1A, which is a dual-configuration vertical MOS transistor, is prevented from being biased depending on the direction of conduction between one transistor 10A and the other transistor 20. be able to.

Therefore, in the structure of the second embodiment, it is possible to increase the ESD resistance of the other transistor 20 while increasing the switching response of one transistor 10A without causing bias in bidirectional conduction. However, in the structure of the second embodiment (FIG. 8), the difference in switching response and ESD resistance between the transistor 10A and the transistor 20 is smaller than in the structure of the typical example of the first embodiment (FIG. 3B).

(Embodiment 3)
In Embodiment 1, in a dual-configuration vertical MOS transistor that can control bidirectional conduction, one vertical MOS transistor can be distinguished from the other vertical MOS transistor from the surface side (pad surface side). mentioned the benefits. In the third embodiment, structural features specializing in the above-mentioned advantages will be described.

That is, in the third embodiment, increasing the switching response with the first vertical MOS transistor and increasing the ESD resistance with the second vertical MOS transistor are not considered. Therefore, there is no need to pay attention to shortening the finger length as in the transistor 10 (transistor 10A) in the first and second embodiments. Therefore, in the semiconductor device 1B according to the third embodiment, the first vertical MOS transistor 10B and the second vertical MOS transistor 20B may be one and the other that divide the semiconductor layer 40 into two in terms of area.

Hereinafter, a semiconductor device 1B according to a third embodiment, which is configured by partially changing the semiconductor device 1 according to the first embodiment, will be described. Regarding the semiconductor device 1B according to the third embodiment, the same components as those of the semiconductor device 1 are given the same reference numerals as they have already been explained, and a detailed explanation thereof will be omitted, and we will focus on the differences from the semiconductor device 1. Explain.

An example of the semiconductor device 1B according to the third embodiment in plan view is shown in FIGS. 9A to 9C and 9E to 9H. As will be described later, FIG. 9D shows a comparative example of the third embodiment.

In FIGS. 9B and 9C, illustrations of the interlayer insulating layer 34 and passivation layer 35, which are originally provided, are omitted in order to make the top structure of the semiconductor device 1B easier to understand. Further, in FIG. 9B, illustrations of the first source electrode 11B, the second source electrode 21B, the first gate electrode 19B, the first gate wiring 114B, the second gate electrode 29B, the second gate wiring 124B, etc. are also omitted. are doing.

9D to 9H, the passivation layer 35 and the interlayer insulating layer 34 are shown as if they were transparent, so that the structure of the upper surface of the semiconductor layer 40 can be clearly illustrated, and the first source electrode 11B and the second source electrode 11B are shown as if they were transparent. The shape of the source electrode 21B is clearly visible.

As shown in FIG. 9A, the semiconductor device 1B (semiconductor layer 40) has a rectangular shape, but compared to the semiconductor device 1 of Embodiment 1 (FIG. 2A), the boundary line 90B between the transistors 10B and 20B is It is straight in a direction parallel to the short side of the layer 40. Further, the first region A1B and the second region A2B are one half and the other half of the semiconductor layer 40, and each has a rectangular shape in a plan view.

In addition, in FIG. 9A, the broken lines indicating the first region A1B and the second region A2B are not exactly aligned with the semiconductor layer 40 and the boundary line 90B for the sake of clarity, but are drawn inside with a slight margin. As shown, the outer periphery of the first region A1B and the outer periphery of the second region A2B substantially coincide with the outer periphery of the semiconductor layer 40 and the boundary line 90B.

FIG. 9B illustrates the arrangement of the first active region 112B and the first peripheral region 113B, and the second active region 122B and the second peripheral region 123B in the semiconductor device 1B (semiconductor layer 40). Furthermore, with respect to the arrangement of FIG. 9B, FIG. 9C shows a first gate electrode 19B and a first gate wiring 114B, and a second gate electrode 29B and a second gate wiring 124B in the semiconductor device 1B (semiconductor layer 40). The following is an example of the arrangement of FIG. 9C also illustrates the arrangement of the first source electrode 11B (portion 13B) and the second source electrode 21B (portion 23B). As shown in FIGS. 9B and 9C, in plan view, the first active region 112B and the first source electrode 11B are arranged so as to almost coincide and overlap, and the second active region 122B and the second The source electrodes 21B are arranged so as to almost coincide and overlap.

Although not shown in FIGS. 9A, 9B, and 9C, the first gate trench 17 (first gate conductor 15) extends in a direction parallel to the short side of the semiconductor layer 40 in plan view. , this direction is taken as the Y direction. In the example shown in FIGS. 9A to 9C, the first area A1B and the second area A2B are each rectangular in shape with their long sides parallel to the boundary line 90B in plan view. Trench 17 (first gate conductor 15) extends in a direction parallel to the long side of transistor 10B. Therefore, in the examples shown in FIGS. 9A to 9C, the finger length of transistor 10B is not necessarily arranged to be the shortest.

However, the first gate trench 17 (first gate conductor 15) may extend in a direction parallel to the long side of the semiconductor layer 40, that is, in a direction parallel to the short side of the transistor 10B in plan view. do not have. In the third embodiment, the direction in which the first gate trench 17 (first gate conductor 15) extends does not matter.

Now, FIG. 9D shows a comparative example of the third embodiment. FIG. 9D illustrates the arrangement of the first gate pad 119B and the second gate pad 129B and the first source pad 111B and the second source pad 121B with respect to the arrangement of FIG. 9C. In FIG. 9D, in plan view, all the illustrated components are arranged line-symmetrically with respect to the boundary line 90B as the axis of symmetry, and the transistors 10B and 20B are arranged from the front side (pad side). It is difficult to distinguish between

On the other hand, an example of the semiconductor device 1B according to the third embodiment is shown in FIGS. 9E and 9F. Note that the examples of the semiconductor device 1B shown in FIGS. 9E and 9F are based on the arrangement of the semiconductor device 1B shown in FIG. 9C. Its characteristics will be explained below.

In order to distinguish between the transistor 10B and the transistor 20B from the front surface side (pad surface side), it is desirable that some kind of difference be physically provided as a mark in plan view. In the example of the semiconductor device 1B shown in FIGS. 9E and 9F, locations X serving as landmarks are provided, and for ease of understanding, each location X where the landmark is provided is surrounded by a broken line in the figure. .

The landmark point X is provided on the first structure provided in the first area A1B so that the first area A1B and the second area A2B can be instantly determined by comparing the first area A1B and the second area A2B in plan view. In area A2B of No. 2, it is desirable that the shape is not provided in the second structure that corresponds to the first structure.

The correspondence here means that the function that the first structure performs in the first vertical MOS transistor 10B and the function that the second structure performs in the second vertical MOS transistor 20B are the same. Refers to relationships. For example, if the first structure is a first source electrode, the second structure is a second source electrode. When the first structure is the first gate wiring, the second structure is the second gate wiring.

If the landmark point X is too small or placed in a place that is difficult to find, it will not be easy to distinguish it. It is preferable to install the Therefore, it is assumed that the target point X in the third embodiment can be found by comparing the first active region 112B and the second active region 122B. That is, the structures installed in the first peripheral area 113B and the second peripheral area 123B may be symmetrical.

However, when installing the landmark point X inside the active region, the first structure provided in the first active region 112B and the second structure provided in the second active region 122B are intentionally disposed in a plan view. Since the shape is not symmetrical, this becomes a factor that causes bias in bidirectional conduction in the dual configuration vertical MOS transistor. In order to reduce the bias in bidirectional conduction as much as possible, it is desirable that the point X serving as a landmark has the following two features.

The first point is that due to the difference in the shape of the landmark point X, there will be a difference in the area of the first structure and the second structure in plan view, but this difference in area should be kept to less than 5%. It is. If the difference in area due to the difference in shape is less than 5%, it is possible to prevent the bias in bidirectional conduction from having any adverse effects.

The second point is to provide the mark point X so as not to be close to the boundary line 90B between the transistors 10B and 20B. In other words, in a plan view, the mark X provided on the first structure is provided at a position opposite to the side facing the second active region 122B in the first structure. This is desirable. Being provided in the first structure at a position opposite to the side facing the second active region 122B means that the center or This means that it is provided in a range farther from the second active region 122B than the center line.

When the landmark point X is provided on the side facing the second active region 122B, there is a possibility that the difference in shape at the landmark point X is placed in a region close to the boundary line 90B in plan view. . The area close to the boundary line 90B is the area where the current density is highest due to bidirectional conduction, so if a difference in shape is provided at the landmark point X, there is a risk that the bias in bidirectional conduction will become large. There is.

Therefore, in the third embodiment, a semiconductor device 1B of a chip size package type capable of face-down mounting is provided, in which a semiconductor substrate 32, a low concentration impurity layer 33 formed on the semiconductor substrate 32, and a semiconductor substrate 32 are provided. When the low concentration impurity layer 33 is collectively referred to as a semiconductor layer 40, a first vertical MOS transistor 10B having a plurality of first gate trenches 17 formed in a first region A1B of the semiconductor layer 40; In a plan view of the semiconductor layer 40, a second vertical MOS transistor 20B having a plurality of second gate trenches 27 formed in a second region A2B adjacent to the first region A1B and a second vertical MOS transistor 20B formed in a second region A2B adjacent to the first region A1B and A metal layer 30 formed in contact with the back surface, the semiconductor substrate 32 is a common drain region of the first vertical MOS transistor 10B and the second vertical MOS transistor 20B, and the semiconductor substrate 32 is a common drain region of the first vertical MOS transistor 10B and the second vertical MOS transistor 20B. The first area A1B and the second area A2B are one area and the other area that divide the semiconductor layer 40 into two halves, and in plan view, the first area A1B is the first area A1B of the first vertical MOS transistor 10B. It consists of a first active region 112B in which a conduction channel is formed, and a first peripheral region 113B adjacent to and surrounding the first active region 112B. The region A2B includes a second active region 122B in which a conduction channel of the second vertical MOS transistor 20B is formed, and a second peripheral region adjacent to and surrounding the second active region 122B. region 123B, and in plan view, the shape of the first structure provided in the first active region 112B has the same function as that of the first vertical MOS transistor 10B. The shape of the second structure in the vertical MOS transistor 20B of the first region A1B and the second region A2B is larger than that of the second structure in the second active region 122B. It has a location X that is not in a linear symmetrical relationship with the boundary line 90B as the axis of symmetry and is not in a point symmetrical relationship with the center of the semiconductor layer 40 as the center of symmetry, and in a plan view, the first structure It is desirable that the portion X of the shape is located in the semiconductor device 1B in the first structure at a position opposite to the side facing the second active region 122B.

Compared to the comparative example (FIG. 9D) in which the landmark location X is not provided, FIG. 9E shows that one of the plurality of first source pads 111B has a different end shape in plan view. A location X is provided. On the other hand, the second source pad 121B is not provided with such a location.

Further, in FIG. 9F, when viewed from above, one of the plurality of first source pads 111B is provided with an inward cut portion X. On the other hand, the second source pad 121B is not provided with such a location.

That is, in plan view, the first structure is the first source pad 111B of the first vertical MOS transistor 10B, and the second structure is the second source pad 121B of the second vertical MOS transistor 20B. In plan view, the total number of corners provided on the outer periphery of the first source pad 111B of the first vertical MOS transistor 10B and the second source pad 121B of the second vertical MOS transistor 20B are The total number of corners provided on the outer periphery is different.

Also, in plan view, the first structure is the first source pad 111B of the first vertical MOS transistor 10B, and the second structure is the second source pad 121B of the second vertical MOS transistor 20B. In a plan view, the total area of the first source pad 111B of the first vertical MOS transistor 10B is different from the total area of the second source pad 121B of the second vertical MOS transistor 20B.

In both FIGS. 9E and 9F, the location X serving as a landmark is located on the side close to the long side end of the semiconductor layer 40 in plan view, and is not provided on the side close to the boundary line 90B. Furthermore, there is a difference between the total area of the first source pads 111B and the total area of the second source pads 121B due to the provision of the location X that serves as a landmark. Even when compared with the total area of the second source pad 121B, the size is less than 5%.

Therefore, as shown in FIGS. 9E and 9F, by providing the mark X, it becomes possible and easy to distinguish between the transistor 10B and the transistor 20B from the front surface side (pad surface side), and the dual Bidirectional conduction in the semiconductor device 1B, which is a vertical MOS transistor, can be prevented from being biased due to a difference in direction.

FIGS. 9G and 9H are shown as another example of the semiconductor device 1B of the third embodiment. The examples of the semiconductor device 1B shown in FIGS. 9G and 9H are based on the arrangement of the semiconductor device 1B shown in FIG. 9B.

In FIGS. 9G and 9H, only the first source electrode 11B is provided with a chamfered portion X at one corner in plan view. On the other hand, the second source electrode 21B is not provided with such a location. That is, in plan view, the first structure is the first source electrode 11B of the first vertical MOS transistor 10B, and the second structure is the second source electrode 21B of the second vertical MOS transistor 20B. and the number of corners provided on the outer periphery of the first source electrode 11B of the first vertical MOS transistor 10B, and the number of corners provided on the outer periphery of the second source electrode 21B of the second vertical MOS transistor 20B. The numbers are different.

Further, the first structure is the first source electrode 11B of the first vertical MOS transistor 10B, the second structure is the second source electrode 21B of the second vertical MOS transistor 20B, In plan view, the area of the first source electrode 11B of the first vertical MOS transistor 10B is different from the area of the second source electrode 21B of the second vertical MOS transistor 20B.

In both FIGS. 9G and 9H, the chamfered portion X is located on the side close to the long side end of the semiconductor layer 40 in plan view, and is not provided on the side close to the boundary line 90B. Further, the area of the first source electrode 11B removed at the chamfered portion X is less than 5% of the area of the second source electrode 21B. Furthermore, as shown in FIG. 9B, the chamfered portion X of the first source electrode 11B is originally within the range of the first active region 112B, only the first source electrode 11B is not provided.

Therefore, as shown in FIGS. 9G and 9H, by providing the landmark X, it becomes possible and easy to distinguish between the transistors 10B and 20B from the front surface side (pad surface side), and the dual Bidirectional conduction in the semiconductor device 1B, which is a vertical MOS transistor, can be prevented from being biased due to a difference in direction.

By the way, in the examples shown in FIGS. 9E to 9G, the first gate pad 119B and the second gate pad 129B are installed at positions close to one long side end and the other long side end of the semiconductor layer 40, respectively, in plan view. ing. Further, in plan view, the plurality of first source pads 111B and the plurality of second source pads 121B each have a substantially rectangular shape with semicircular ends, and all of them extend in a direction parallel to the long side of the semiconductor layer 40. They are arranged in stripes at equal intervals in the longitudinal direction. However, in the third embodiment (this disclosure), the number, shape, size, and arrangement of the first gate pad 119B, the second gate pad 129B, the first source pad 111B, and the second source pad 121B are There are no restrictions placed on these, and those shown in FIGS. 9E to 9H are merely examples thereof.

A semiconductor device including a vertical MOS transistor according to the present invention can be widely used as a device for controlling the conduction state of a current path.

1, 1A, 1B semiconductor device 10, 10A, 10B, transistor (first vertical MOS transistor)
11, 11B First source electrode 12, 13, 13B Portion 14 First source region 15 First gate conductor 16 First gate insulating film 17 First gate trench 18 First body region 18a First connection Part 19, 19A, 19B First gate electrode 20, 20B Transistor (second vertical MOS transistor)
21, 21B Second source electrode 22, 23, 23B Portion 24 Second source region 25 Second gate conductor 26 Second gate insulating film 27 Second gate trench 28 Second body region 28a Second connection Part 29, 29B Second gate electrode 30 Metal layer 32 Semiconductor substrate 33 Low concentration impurity layer or drift layer 34 Interlayer insulating layer 35 Passivation layer 40 Semiconductor layer 90, 90B Boundary line 111, 111B First source pad 112, 112A, 112B First active region 113, 113A, 113B First peripheral region 114, 114A, 114B First gate wiring (first gate runner)
114b Connection portion 115 First gate resistance element 116, 116A First EQR
119, 119B First gate pad 121, 121B Second source pad 122, 122B Second active region 123, 123B Second peripheral region 124, 124B Second gate wiring (second gate runner)
125 Second gate resistance element 126 Second EQR
129, 129B Second gate pad 301 First side 302 Second side 303 Third side 304 Fourth side A1, A1B First area A2, A2B Second area

Claims (18)

1. A chip-sized package type semiconductor device that can be mounted face-down,
   a semiconductor substrate;
   a semiconductor layer formed on the semiconductor substrate;
   a first vertical MOS transistor formed in a first region of the semiconductor layer and having a plurality of first gate trenches;
   a second vertical MOS transistor having a plurality of second gate trenches formed in a second region adjacent to the first region in a plan view of the semiconductor layer;
   a metal layer formed in contact with the back surface of the semiconductor substrate,
   The semiconductor substrate is a common drain region of the first vertical MOS transistor and the second vertical MOS transistor,
   In the planar view, the semiconductor layer has a rectangular shape, and the semiconductor layer is arranged so that the length of the long side of the semiconductor layer matches the length of the longest side among the sides forming the outer periphery of the first region. The region and the second region are one and the other that divide the semiconductor layer into two in terms of area,
   The first region includes a first gate electrode that controls conduction of the first vertical MOS transistor, and a first gate wiring connected to the first gate electrode,
   The second region includes a second gate electrode that controls conduction of the second vertical MOS transistor, and a second gate wiring connected to the second gate electrode,
   In the plan view, the shape formed by the first gate electrode and the first gate wiring and the shape formed by the second gate electrode and the second gate wiring are different from each other in the first region. There is no linear symmetry relationship with the boundary line with the second region as the axis of symmetry,
   In the plan view, the shape formed by the first gate electrode and the first gate wiring and the shape formed by the second gate electrode and the second gate wiring are such that the center of the semiconductor layer is A semiconductor device that does not have a point-symmetric relationship with respect to the center of symmetry.
2. In the plan view, the first region and the second region each have a rectangular shape,
   The semiconductor device according to claim 1 , wherein in the plan view, the direction in which the plurality of first gate trenches extend is a direction parallel to the short side of the first region.
3. In the plan view, among the four sides forming the outer periphery of the first region, the side overlapping with the boundary line is defined as a first side, the side opposite to the first side is defined as a second side, and If one side that is perpendicular to the first side and the second side and faces each other is the third side, and the other side is the fourth side,
   The first gate wiring is installed continuously along substantially the entire length of at least the first side, the second side, and the third side,
   The plurality of first gate trenches are connected to the first gate wiring at both a portion of the first gate wiring along the first side and a portion along the second side. The semiconductor device according to claim 2, wherein the semiconductor device has the largest number of semiconductor devices.
4. 4. The semiconductor device according to claim 3, wherein the first gate wiring is connected to the first gate electrode at a portion along the third side in the plan view.
5. 3. The semiconductor device according to claim 2, wherein the direction in which the plurality of second gate trenches extend in the plan view is a direction parallel to the long side of the second region.
6. The first gate electrode and the first gate wiring are continuous,
   The second gate electrode and the second gate wiring are not continuous, and the second gate electrode is connected to the second gate wiring through a gate resistance element in series. Or the semiconductor device according to 2.
7. The semiconductor device according to claim 3, wherein the first gate wiring is not installed along the fourth side.
8. Furthermore, the first region is provided with a first EQR,
   The first EQR is installed continuously along substantially the entire length of the first side, the second side, and the third side, and is not installed along the fourth side. 3. The semiconductor device according to 3.
9. In the plan view, among the plurality of first gate trenches, the distance between the one closest to the fourth side and the fourth side is, among the plurality of first gate trenches, The semiconductor device according to claim 7 or 8, wherein the distance is smaller than the distance between the third side and the one closest to the third side.
10. In the plan view, the first gate wiring includes a portion along the first side and a portion along the second side, in addition to a portion along the third side or the fourth side. The semiconductor device according to claim 9, further comprising a portion that connects the portion along the side at the shortest possible distance.
11. 11. The semiconductor device according to claim 10, wherein a total gate width of the first vertical MOS transistor and a total gate width of the second vertical MOS transistor are equal.
12. A chip-sized package type semiconductor device that can be mounted face-down,
    a semiconductor substrate;
    a semiconductor layer formed on the semiconductor substrate;
    a first vertical MOS transistor formed in a first region of the semiconductor layer and having a plurality of first gate trenches;
    a second vertical MOS transistor having a plurality of second gate trenches formed in a second region adjacent to the first region in a plan view of the semiconductor layer;
    a metal layer formed in contact with the back surface of the semiconductor substrate,
    The semiconductor substrate is a common drain region of the first vertical MOS transistor and the second vertical MOS transistor,
    In the plan view, the first region and the second region are one and the other dividing the semiconductor layer into two in terms of area,
    In the plan view, the first region is adjacent to a first active region in which a conduction channel of the first vertical MOS transistor is formed, and is adjacent to the first active region. a first peripheral area surrounding the
    In the plan view, the second region is adjacent to a second active region in which a conduction channel of the second vertical MOS transistor is formed, and is adjacent to the second active region. and a second peripheral area surrounding the
    In the plan view, the shape of the first structure provided in the first active region is such that the first structure has the same function as the first vertical MOS transistor in the second vertical MOS transistor. A second structure included in a MOS transistor, the boundary line between the first region and the second region being symmetrical with respect to the shape of the second structure provided in the second active region. having a location that is not in a line-symmetrical relationship with respect to the axis of and not in a point-symmetrical relationship with the center of the semiconductor layer as the center of symmetry,
    In the planar view, the portion of the shape of the first structure is provided at a position opposite to the side of the first structure facing the second active region.
13. The first structure is a source electrode of the first vertical MOS transistor, the second structure is a source electrode of the second vertical MOS transistor,
    In the planar view, the number of corners provided on the outer periphery of the source electrode of the first vertical MOS transistor is different from the number of corners provided on the outer periphery of the source electrode of the second vertical MOS transistor. The semiconductor device described in .
14. The first structure is a source electrode of the first vertical MOS transistor, the second structure is a source electrode of the second vertical MOS transistor,
    13. The semiconductor device according to claim 12, wherein the area of the source electrode of the first vertical MOS transistor and the area of the source electrode of the second vertical MOS transistor are different in the planar view.
15. In the plan view, the area of the source electrode of the first vertical MOS transistor is larger than the area of the source electrode of the second vertical MOS transistor,
    In the plan view, the difference between the area of the source electrode of the first vertical MOS transistor and the area of the source electrode of the second vertical MOS transistor is equal to the area of the source electrode of the first vertical MOS transistor. 15. The semiconductor device according to claim 14, wherein the semiconductor device is less than 5% of .
16. The first structure is a source pad of the first vertical MOS transistor, the second structure is a source pad of the second vertical MOS transistor,
    In the plan view, the total number of corners provided on the outer periphery of the source pad of the first vertical MOS transistor and the total number of corners provided on the outer periphery of the source pad of the second vertical MOS transistor are The semiconductor device according to claim 12.
17. The first structure is a source pad of the first vertical MOS transistor, the second structure is a source pad of the second vertical MOS transistor,
    13. The semiconductor device according to claim 12, wherein the total area of the source pads of the first vertical MOS transistor is different from the total area of the source pads of the second vertical MOS transistor in the plan view.
18. In the plan view, the total area of the source pads of the first vertical MOS transistor is larger than the total area of the source pads of the second vertical MOS transistor,
    In the plan view, the difference between the total area of the source pads of the first vertical MOS transistor and the total area of the source pads of the second vertical MOS transistor is equal to The semiconductor device according to claim 17, wherein the area is less than 5% of the total area of the source pads.

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