JP2018061009A - Semiconductor device and semiconductor package - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device that is a normally-on type and that can miniaturize an element, and to provide a semiconductor package.SOLUTION: Provided is a semiconductor chip 6 including: a first transistor Tr1 and a second transistor Tr2; a drain electrode 53 electrically connected with drains of the first transistor Tr1 and the second transistor Tr2 commonly; first source wiring 10 electrically connected with a source of the first transistor Tr1; second source wiring 11 electrically connected with a source of the second transistor Tr2; and gate wiring 9 electrically connected with gates of the first transistor Tr1 and the second transistor Tr2 commonly.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a semiconductor device and a semiconductor package.

Conventionally, a JFET (Junction Gate Field Effect Transistor) is known as a normally-on type semiconductor element. For example, Patent Document 1 discloses a SiC-JFET used in a form combined with a MOSFET.
Patent Document 2 discloses a semiconductor package including a semiconductor chip, a stage on which the semiconductor chip is mounted, a gate lead, a source lead, a drain lead, a bonding wire, and a sealing resin.

JP 2011-166673 A JP 2014-123665 A

  In a normally-on JFET, a current flowing through the semiconductor layer is blocked by a depletion layer that spreads in the semiconductor layer when a voltage is applied. Appropriate design of the depletion layer spread width ensures reliable interruption of current. For this reason, in the JFET, the spreading width of the depletion layer must be preferentially considered, and as a result of lowering the impurity concentration (channel concentration) of the semiconductor layer, the resistance per unit length is relatively high. In addition, although a depletion type MOSFET exists as a normally-on type semiconductor element, the same reason for preferentially considering the spread width of the depletion layer prevents the resistance of the semiconductor layer from being reduced.

From such a background, in JFET and depletion type MOSFET, it is necessary to secure a large current path in order to reduce on-resistance. Therefore, it is difficult to use the device with a reduced size.
An object of the present invention is to provide a semiconductor device and a semiconductor package that are of a normally-on type and that can be miniaturized.

In addition, various semiconductor packages have been conventionally proposed as in Patent Document 2, but in the future, with the demand for wearable terminals, more compact transistors will be required.
Another object of the present invention is to provide a semiconductor device that is remarkably miniaturized as compared with the prior art.

  A semiconductor device according to an embodiment of the present invention is commonly used for an enhancement type first p-channel MISFET, an enhancement type second p-channel MISFET, and drains of the first p-channel MISFET and the second p-channel MISFET. An electrically connected drain conductor, a first source conductor electrically connected to a source of the first p-channel MISFET, and a second electrically connected to a source of the second p-channel MISFET. A source conductor; and a gate conductor electrically connected in common to the gates of the first p-channel MISFET and the second p-channel MISFET.

In this semiconductor device, a voltage is applied between the first source conductor S ₁ and the second source conductor S ₂ (between S _{1 and} S ₂ ) in a state where no voltage is applied to the gate conductor G. Both MISFETs are turned on via the parasitic diodes (internal diodes) of the first p-channel type MISFET and the second p-channel type MISFET. _Thus, current can flow between S 1 -S _2. On the other hand, when a positive voltage is applied to the gate conductor G, the potential difference VGS ₁ between the gate conductor G and the first source conductor S ₁ approaches 0, and finally the first source conductor current is cut off between the S ₁ and the second source conductor S _2. Thus, S ₁ -S ₂ conducts when no voltage is applied to the gate conductor G, while S ₁ -S ₂ is cut off when a voltage is applied to the gate conductor G. That is, a normally-on operation is realized. Further, in the first and second p-channel MISFETs for turning on / off the current in this semiconductor device, unlike the JFET and the depletion type MISFET, the spread of the depletion layer is not used for turning on / off the current. Therefore, it is not necessary to design the impurity concentration of the semiconductor layer in consideration of the depletion layer, so that a low resistance value can be maintained even if the semiconductor device is downsized.

  A semiconductor device according to an embodiment of the present invention includes a semiconductor layer having a common p-type drain region for the first p-channel type MISFET and the second p-channel type MISFET, and the first p-channel type MISFET includes the semiconductor layer. A first n-type body region formed on the surface portion of the first n-type body region, a first p-type source region formed on the surface portion of the first n-type body region, and a first gate electrode facing the first n-type body region, The second p-channel type MISFET includes a second n-type body region formed on the surface portion of the semiconductor layer, a second p-type source region formed on the surface portion of the second n-type body region, and the second n-type body region. The drain conductor is formed on the back surface of the semiconductor layer and connected to the p-type drain region. The first source conductor includes a first source electrode connected to the first p-type source region, and the second source conductor is disposed separately from the first source electrode. A second source electrode connected to the second p-type source region; and the gate conductor includes a gate wiring commonly connected to the first gate electrode and the second gate electrode in the semiconductor layer. May be.

According to this configuration, the first p-channel type MISFET and the second p-channel type MISFET can be integrated into one chip, so that a smaller semiconductor device can be provided.
In the semiconductor device according to an embodiment of the present invention, the semiconductor layer includes a first active region for the first p-channel type MISFET and the second p-channel type MISFET disposed adjacent to the first active region. And the second active region, and the gate wiring may be provided in a region between the first active region and the second active region.

  The semiconductor device according to an embodiment of the present invention includes a first gate trench formed immediately below the first active region, a second gate trench formed immediately below the second active region, and the first gate. A third gate trench formed between the trench and the second gate trench and commonly connecting the first gate trench and the second gate trench, wherein the first gate electrode is the first gate electrode; An electrode embedded in the trench may be included, the second gate electrode may include an electrode embedded in the second gate trench, and the gate wiring may include an electrode embedded in the third gate trench. .

  A semiconductor device according to an embodiment of the present invention includes a first gate trench formed immediately below the first active region and a second gate trench formed immediately below the second active region, One gate electrode includes an electrode embedded in the first gate trench, the second gate electrode includes an electrode embedded in the second gate trench, and the gate wiring is formed in a region on the semiconductor layer. An electrode formed over the surface of the semiconductor layer, straddling the first gate electrode and the second gate electrode, and connected to each of the first gate electrode and the second gate electrode from above. May be.

In the semiconductor device according to an embodiment of the present invention, in the region between the first active region and the second active region, the region on the back surface side of the semiconductor layer with respect to the surface portion of the semiconductor layer is the common region. May be occupied by the p-type drain region.
In the semiconductor device according to an embodiment of the present invention, the gate wiring includes a gate pad and a gate finger connected to the gate pad and surrounding the first active region and the second active region, The one source electrode and the second source electrode may be disposed in a region separated from each other by the gate finger.

  A semiconductor device according to an embodiment of the present invention includes a linear first unit cell array configured by a plurality of first unit cells of the first p-channel type MISFET, and a plurality of second units of the second p-channel type MISFET. A linear second unit cell column composed of unit cells, wherein the first unit cell column and the second unit cell column are alternately arranged with a space therebetween, and the first source electrode is The first unit cell row and the second unit cell row have a base end portion on one end side, and are formed in a comb shape having a tooth portion on each first unit cell, and the second source electrode is The first unit cell row and the second unit cell row have base ends on the other end sides, teeth on each of the second unit cells, and the comb-like first source electrode It may be formed in a comb-teeth shape that meshes with an interval.

In the semiconductor device according to an embodiment of the present invention, the plurality of first unit cells of the first p-channel type MISFET and the plurality of second unit cells of the second p-channel type MISFET are arranged in a matrix as a whole, The plurality of first unit cells and the plurality of second unit cells may be alternately arranged in each of a row direction and a column direction.
A semiconductor package according to an embodiment of the present invention includes a semiconductor device according to an embodiment of the present invention and a sealing resin that seals all or part of the semiconductor device.

According to this configuration, since the semiconductor device according to an embodiment of the present invention is provided, it is possible to provide a semiconductor package that is a normally-on type and that can be reduced in size.
A semiconductor device according to an embodiment of the present invention includes a front surface, a back surface opposite to the front surface, a semiconductor substrate having a quadrangular shape in plan view, and a side surface between the front surface and the back surface, and at least the front surface. A surface insulating film formed on the semiconductor substrate so as to cover the both ends of the first peripheral edge at the center of the first peripheral edge along one side surface of the semiconductor substrate on the front surface side of the semiconductor substrate A first pad disposed at a distance from a corner; a second pad disposed at one corner of a second peripheral edge opposite to the first peripheral edge of the semiconductor substrate; and the first pad of the semiconductor substrate. 2 and a third pad arranged at the other end corner of the peripheral edge.

  As a comparative form different from this configuration, if the first pad is arranged at the corner of the first peripheral edge, or if the first pad is formed to a size that reaches both corners, the first pad and the first pad The distance between the two pads and the distance between the first pad and the third pad are substantially equal to the length of the side along the side surface of the semiconductor substrate. In such a form, when the size of the semiconductor substrate (the length of the side of the semiconductor substrate) is reduced with the miniaturization of the semiconductor device, the distance between the pads described above is shortened, and there is a possibility of short circuit after mounting.

  On the other hand, in the above configuration, the first pad is arranged at the center of the first peripheral portion of the semiconductor substrate having a quadrangular shape in plan view, spaced from both corners of the first peripheral portion. Therefore, the distance between the first pad and the second pad and the distance between the first pad and the third pad can be made relatively long. Therefore, the size of the semiconductor substrate can be made smaller than that of the comparative embodiment while avoiding a short circuit during mounting. Thereby, a miniaturized semiconductor device can be provided.

In the semiconductor device according to one embodiment of the present invention, the semiconductor substrate includes a semiconductor substrate having a rectangular shape in plan view, and the first peripheral edge and the second peripheral edge are peripheral edges along the longitudinal direction of the semiconductor substrate. May be included.
According to this configuration, since the second pad and the third pad are respectively disposed at the one end corner and the other end corner of the second peripheral edge along the longitudinal direction, the distance between the second pad and the third pad. Can also be relatively long.

  In the semiconductor device according to an embodiment of the present invention, a first arc having a radius at a short side length of the semiconductor substrate centered on a vertex of one end corner of the second peripheral edge, and the second peripheral edge When the second arc having the radius of the short side length of the semiconductor substrate is drawn on the surface of the semiconductor substrate, the first pad is the first arc. And may be disposed in the outer region of the second arc.

  According to this configuration, as the distance between the first pad and the second pad and the distance between the first pad and the third pad, at least the length of the short side of the semiconductor device and the size of the second pad and the third pad ( The length corresponding to the difference with the (width) can be secured. That is, the semiconductor device can be reduced in size by the size of the first pad while maintaining the distance between the first pad and the second pad and the distance between the first pad and the third pad in the comparative embodiment. .

In the semiconductor device according to an embodiment of the present invention, the first arc and the second arc have a size that intersects each other in a region on the semiconductor substrate, and the first pad has the first arc and the A pair of tangent lines drawn from the intersection with the second arc with respect to each of the first arc and the second arc may be formed in a triangular shape having two sides.
According to this configuration, the first pad can be formed using the space in the outer region of the first arc and the second arc to the maximum. Thereby, it is possible to secure a sufficient bonding area for the first pad while downsizing the semiconductor device.

In the semiconductor device according to an embodiment of the present invention, the second pad may be formed in a fan shape having the same center as the first arc.
According to this configuration, as the distance between the first pad and the second pad, at least a length corresponding to the difference between the length of the short side of the semiconductor device and the size (width) of the second pad is secured. A sufficient bonding area can be secured for two pads.

In the semiconductor device according to an embodiment of the present invention, the third pad may be formed in a fan shape having the same center as the second arc.
According to this configuration, as the distance between the first pad and the third pad, at least a length corresponding to the difference between the length of the short side of the semiconductor device and the size (width) of the third pad is secured. A sufficient bonding area can be secured for the three pads.

  A semiconductor device according to an embodiment of the present invention includes a MIS transistor structure formed on the semiconductor substrate, and the first pad includes a drain pad electrically connected to a drain of the MIS transistor structure, The second pad may include a source pad electrically connected to the source of the MIS transistor structure, and the third pad may include a gate pad electrically connected to the gate of the MIS transistor structure. .

  In the semiconductor device according to an embodiment of the present invention, the semiconductor substrate includes an active region in which the MIS transistor structure is formed, and the MIS transistor structure is directed from the first peripheral edge toward the second peripheral edge. A first interlayer film formed on the semiconductor substrate so as to cover the source region and the drain region, and includes a plurality of source regions and drain regions alternately arranged in a stripe shape extending to A region is formed on the first interlayer film so as to cover a substantially half region on the second peripheral edge side of the region, and is electrically connected to the source region at an end of the source region on the second peripheral edge side. Formed on the first interlayer film so as to cover the first source wiring layer and a substantially half region on the first peripheral edge side of the active region, and the drain region A first drain wiring layer may further comprise electrically connected to the drain region in the end of the first peripheral portion.

According to this configuration, the first source wiring layer and the first drain wiring layer are each formed to have a size that covers approximately half of the active region. Thereby, a wide current path between the source and the drain can be secured. Therefore, an increase in on-resistance of the MIS transistor can be suppressed while downsizing the semiconductor device.
A semiconductor device according to an embodiment of the present invention includes a second interlayer film formed on the first interlayer film so as to cover the first source wiring layer and the first drain wiring layer, and the active region. It is formed on the second interlayer film so as to cover a substantially half region on the second peripheral edge side, and is electrically connected to the first source wiring layer, a part of which is the surface insulation as the source pad A second source wiring layer exposed from the film and a second half of the active region on the first peripheral edge side are formed on the second interlayer film so as to cover the first drain wiring layer electrically. A second drain wiring layer that is connected and a part of which is exposed from the surface insulating film as the drain pad may be included.

According to this configuration, each of the second source wiring layer and the second drain wiring layer is formed in a size that covers a substantially half of the active region. Thereby, a wide current path between the source and the drain can be secured. Therefore, an increase in on-resistance of the MIS transistor can be suppressed while downsizing the semiconductor device.
In the semiconductor device according to an embodiment of the present invention, the semiconductor substrate is formed on the second interlayer film so as to cover the protection diode region outside the active region and the protection diode region, and a part of the semiconductor substrate is formed on the second interlayer film. A gate wiring layer exposed from the surface insulating film may be further included as a gate pad.

In the semiconductor device according to an embodiment of the present invention, the surface insulating film may be formed so as to further cover the side surface of the semiconductor substrate.
According to this configuration, when the semiconductor device is mounted with high density, it is possible to prevent a short circuit between adjacent semiconductor devices.
The semiconductor device according to an embodiment of the present invention may have a chip size package structure.

In the semiconductor device according to an embodiment of the present invention, the chip size package structure may include a long side of less than 0.50 mm and a short side of less than 0.40 mm.
With this configuration, an unprecedented minimum semiconductor device can be provided.
In the semiconductor device according to an embodiment of the present invention, the chip size package structure may be formed with a thickness of less than 0.15 mm.

If the thickness of the chip size package structure is within the above range, the amount of protrusion from the normal position of the side surface of the semiconductor device can be reduced even if the semiconductor device is mounted with an inclination. Thereby, even when a semiconductor device is mounted with high density, contact with an adjacent semiconductor device can be suppressed.
In the semiconductor device according to an embodiment of the present invention, a distance between each of the first pad, the second pad, and the third pad may be 50% or more of a short side of the semiconductor substrate.

FIG. 1 is a schematic configuration diagram of a semiconductor package according to an embodiment of the present invention. FIG. 2 is a cross-sectional view that appears when the semiconductor chip of FIG. 1 is cut along the line II-II. FIG. 3 is a diagram showing a cell layout of the first transistor and the second transistor. 4A and 4B are diagrams showing a circuit configuration of the semiconductor chip. FIG. 5 is a diagram showing IV characteristics of the semiconductor chip. FIG. 6 is a schematic cross-sectional view of a semiconductor chip according to another embodiment of the present invention. FIG. 7 is a schematic configuration diagram of a semiconductor package according to another embodiment of the present invention. FIG. 8 is a cross-sectional view that appears when the semiconductor chip of FIG. 7 is cut along the line VIII-VIII. FIG. 9 is a diagram showing a cell layout of the first transistor and the second transistor. 10 is a schematic cross-sectional view of a semiconductor chip according to another embodiment of the present invention. FIG. 11 is a diagram showing a cell layout of the first transistor and the second transistor. FIG. 12 is a schematic configuration diagram of a semiconductor package according to another embodiment of the present invention. FIG. 13 is a schematic perspective view of a semiconductor package according to another embodiment of the present invention. FIG. 14 is a schematic plan view of the semiconductor package of FIG. FIG. 15 is a schematic cross-sectional view of the semiconductor package of FIG. FIG. 16 is a schematic perspective view of a semiconductor device according to an embodiment of the present invention. FIG. 17 is a schematic plan view of the semiconductor device. FIG. 18 is a diagram for comparing chip sizes of the semiconductor device and the semiconductor device according to the comparative embodiment. FIG. 19 is a diagram showing the internal structure of the semiconductor device, and mainly shows the layout of the active region. FIG. 20 is a diagram showing the internal structure of the semiconductor device, and mainly shows the layout of the first wiring layer. FIG. 21 is a diagram showing the internal structure of the semiconductor device, and mainly shows the layout of the top wiring layer. FIG. 22 is a diagram showing a surface structure of the semiconductor device, and mainly shows a layout of pad openings. FIG. 23 is a schematic cross-sectional view of the semiconductor device, showing a cross-section (source-side cross-section) of the active region. FIG. 24 is a schematic cross-sectional view of the semiconductor device, showing a cross-section (drain side cross-section) of the active region. FIG. 25 is a schematic cross-sectional view of the semiconductor device, showing a cross-section of the protection diode region. FIG. 26A is a cross-sectional view for explaining an example of the manufacturing process of the semiconductor device of FIG. FIG. 26B is a diagram showing the next manufacturing step after FIG. 26A. FIG. 26C is a diagram showing the next manufacturing step after FIG. 26B. FIG. 26D is a diagram showing the next manufacturing step after FIG. 26C. FIG. 26E is a diagram showing the next manufacturing step after FIG. 26D. FIG. 26F is a view showing the next manufacturing step after FIG. 26E.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a schematic configuration diagram of a semiconductor package 1 according to an embodiment of the present invention, and is a diagram illustrating a plan view of an internal structure of the semiconductor package 1. For the sake of convenience, FIG. 1 shows the inside of the semiconductor package 1 seen through.
The semiconductor package 1 is formed in a rectangular parallelepiped shape, and its size is, for example, 1.6 mm × 1.6 mm or less. The semiconductor package 1 includes an island 2, a plurality of terminals 3 to 5, a semiconductor chip 6, and a sealing resin 7.

The island 2 is formed in a quadrangular shape in plan view, and is disposed at the approximate center of the semiconductor package 1. In this embodiment, the island 2 is connected to a drain electrode 53 described later. The island 2 may also serve as the drain terminal of the semiconductor package 1 when the semiconductor package 1 is used in the circuit configuration shown in FIG. 4B.
The plurality of terminals 3 to 5 include a first source terminal 3, a second source terminal 4, and a gate terminal 5. The plurality of terminals 3 to 5 are provided so as to be biased to one surface among the one surface and the other surface in the thickness direction of the semiconductor package 1 (the direction penetrating the paper surface). The plurality of terminals 3 to 5 are arranged away from each other on the one surface side. In this embodiment, the first source terminal 3 and the second source terminal 4 are respectively disposed at each end portion (corner portion of the semiconductor package 1) of one of the pair of opposite sides of the semiconductor package 1. The gate terminal 5 is disposed at substantially the center of the other side of the opposite side.

The semiconductor chip 6 is formed in a square shape in plan view and is disposed on the island 2. The semiconductor chip 6 has an electrode film 8 formed in a predetermined pattern on the surface opposite to the joining side with the island 2. The electrode film 8 includes a gate line 9, a first source line 10, and a second source line 11.
The gate wiring 9 includes a gate pad 12 and a gate finger 13 extending from the gate pad 12.

The gate pad 12 is disposed at a substantially central portion of the side of the semiconductor chip 6 adjacent to the side of the semiconductor package 1 where the gate terminal 5 is disposed. With this arrangement, the distance between the gate pad 12 and the gate terminal 5 is reduced, so that the connection by the bonding wire 19 is facilitated.
The gate finger 13 is provided along the peripheral edge of the semiconductor chip 6, and the gate pad 13 divides the outer peripheral part 14 into the outer peripheral part 14 that divides the outer peripheral part 14 into the central area of the inner semiconductor chip 6. 12 and a central portion 15 extending to the outer peripheral portion 14 provided on the opposite side. The central portion 15 divides the closed region in the outer peripheral portion 14 into a first region 16 and a second region 17. The first region 16 and the second region 17 are formed on the first source terminal 3 side and the second source terminal 4 side, respectively, with the central portion 15 as a boundary, and the direction along the central portion 15 from each source terminal 3, 4. And has a substantially rectangular shape.

  The first source line 10 and the second source line 11 are respectively disposed in the first region 16 and the second region 17 defined by the gate fingers 13. A gap 18 having a constant width is provided between the first source line 10 and the second source line 11 and the gate finger 13, and the gaps 18 are insulated and separated from each other. Similar to the first region 16 and the second region 17, the first source wire 10 and the second source wire 11 have a substantially rectangular shape that is long in the direction along the central portion 15 from the source terminals 3 and 4, respectively. ing. With this shape, a plurality of bonding wires 20 on the first source terminal 3 side and bonding wires 21 on the second source terminal 4 side can be connected without interfering with each other.

The sealing resin 7 constitutes the outer shape of the semiconductor package 1 and seals the semiconductor chip 6 so that at least a part of the first source terminal 3, the second source terminal 4, and the gate terminal 5 is exposed. Yes. The island 2 may be exposed as a drain terminal from the back surface of the sealing resin 7 when the semiconductor package 1 is used in the circuit configuration shown in FIG. 4B.
FIG. 2 is a cross-sectional view that appears when the semiconductor chip 6 of FIG. 1 is cut along the II-II cutting line. FIG. 3 is a diagram showing a cell layout of the first transistor Tr1 and the second transistor Tr2.

The semiconductor chip 6 includes a semiconductor layer 22. The semiconductor layer 22 includes a p ⁺ type semiconductor substrate 23 and a p type epitaxial layer 24 stacked on the substrate 23. In addition, the semiconductor layer 22 does not need to have an epitaxial layer, for example, may consist only of a p-type semiconductor substrate.
The region on the semiconductor layer 22 includes a first active region 25 and a second active region 26 adjacent to each other, and a central region 27 is set between these regions 25 and 26.

On the surface portion of the semiconductor layer 22 (p-type epitaxial layer 24), an n-type body region 28 is formed over the entire area of the first active region 25, the second active region 26, and the central region 27. In the p-type epitaxial layer 24, the region on the back side of the semiconductor layer 22 with respect to the n-type body region 28 is a p-type drain region 29.
The p-type epitaxial layer 24 is formed with a gate trench 30 that penetrates the n-type body region 28 from the surface and reaches the p-type drain region 29.

  As shown in FIG. 3, the gate trench 30 is formed in a lattice shape in plan view across the boundaries of the first active region 25, the second active region 26, and the central region 27. Thereby, on the surface portion of the p-type epitaxial layer 24, a plurality of unit cells 31 to 33 are partitioned in a plurality of window portions of the lattice-like gate trench 30. The unit cells 31 to 33 include a first unit cell 31 for the first transistor Tr1 formed in the first active region 25, and a second unit cell 32 for the second transistor Tr2 formed in the second active region 26. And a third unit cell 33 (dummy cell) which is formed in the central region 27 and does not function as a transistor. That is, in this embodiment, in the semiconductor layer 22, the plurality of first unit cells 31 and the plurality of second unit cells 32 are aggregated into certain regions (first active region 25 and second active region 26), respectively. The regions 25 and 26 are arranged in a matrix.

  In addition, as shown in FIG. 3, the gate trench 30 includes a first gate trench 34 immediately below the first active region 25, a second gate trench 35 directly below the second active region 26, and a second gate trench 30 immediately below the central region 27. A three-gate trench 36 can be distinguished. The first gate trench 34 and the second gate trench 35 are commonly connected by a third gate trench 36 between the trenches 34, 35, and are connected to each other through the third gate trench 36.

In each first unit cell 31, ap ⁺ type source region 37 is formed on the surface portion of the n type body region 28. In addition, an n ⁺ type body contact region 38 that penetrates the p ⁺ type source region 37 from the surface of the p type epitaxial layer 24 and reaches the n type body region 28 is formed. As a result, the n-type body region 28 can be contacted from the surface side of the p-type epitaxial layer 24.

In each second unit cell 32, ap ⁺ type source region 39 is formed on the surface portion of the n type body region 28. In addition, an n ⁺ type body contact region 40 that penetrates the p ⁺ type source region 39 from the surface of the p type epitaxial layer 24 and reaches the n type body region 28 is formed. As a result, the n-type body region 28 can be contacted from the surface side of the p-type epitaxial layer 24.

Each third unit cell 33 does not have a source region or the like on the surface thereof, and is occupied by the n-type body region 28 from the bottom of the gate trench 30 to the open end.
A gate insulating film 41 and a gate electrode 42 are embedded in the gate trench 30. As shown in FIG. 2, the gate electrode 42 includes a first gate electrode 43 embedded in the first gate trench 34, a second gate electrode 44 embedded in the second gate trench 35, and a third gate trench 36. It can be distinguished from the embedded third gate electrode 45. The first gate electrode 43 and the second gate electrode 44 are commonly connected by a third gate electrode 45 between the electrodes 43 and 44.

The first gate electrode 43 faces the p ⁺ type source region 37, the n type body region 28, and the p type drain region 29 of each first unit cell 31. Thus, in each first unit cell 31, a first transistor Tr1 that is a p-channel MISFET is configured. Further, the first unit cell 31 is provided with a parasitic diode (first parasitic diode 54) configured by a pn junction between the p-type drain region 29 and the n-type body region 28.

The second gate electrode 44 faces the p ⁺ type source region 39, the n type body region 28, and the p type drain region 29 of each second unit cell 32. Thereby, in each second unit cell 32, a second transistor Tr2 which is a p-channel MISFET is configured. Further, the second unit cell 32 is provided with a parasitic diode (first parasitic diode 55) formed by a pn junction between the p-type drain region 29 and the n-type body region 28.

The third gate electrode 45 faces the n-type body region 28 of each third unit cell 33.
An interlayer insulating film 46 is formed on the semiconductor layer 22. In the interlayer insulating film 46, a first contact hole 47, a second contact hole 48, and a third contact hole 49 are formed. The first contact hole 47 exposes the p ⁺ type source region 37 and the n ⁺ type body contact region 38 of the first unit cell 31. The second contact hole 48 exposes the p ⁺ type source region 39 and the n ⁺ type body contact region 40 of the second unit cell 32. The third contact hole 49 exposes the third gate electrode 45.

On the interlayer insulating film 46, the electrode film 8 shown in FIG. 1 is formed. In the electrode film 8, the first source wiring 10 is connected to the p ⁺ type source region 37 and the n ⁺ type body contact region 38 of the first unit cell 31 through the first contact hole 47. The second source line 11 is connected to the p ⁺ type source region 39 and the n ⁺ type body contact region 40 of the second unit cell 32 through the second contact hole 48. Further, the gate finger 13 (the central portion 15 in FIG. 2) is connected to the third gate electrode 45 through the third contact hole 49.

A surface protective film 50 is formed on the electrode film 8 so as to cover the electrode film 8. The surface protective film 50 is formed with pad openings 51 and 52 that expose portions of the first source wiring 10 and the second source wiring 11 as pads. On the other hand, the gate finger 13 is covered with the surface protective film 50.
A drain electrode 53 is formed on the entire back surface of the semiconductor layer 22 (p ⁺ type semiconductor substrate 23). The drain electrode 53 is a common electrode for the first transistor Tr1 and the second transistor Tr2.

The following description is added regarding the configuration of the semiconductor chip 6.
The p ⁺ type semiconductor substrate 23 is made of, for example, a p type silicon substrate. The thickness of the p ⁺ type semiconductor substrate 23 is, for example, 40 μm to 250 μm. The p ⁺ type semiconductor substrate 23 includes, for example, B (boron) as a p type impurity, and the concentration thereof is about 1 × 10 ²¹ cm ⁻³ to 1 × 10 ²² cm ⁻³ .

The thickness of the p-type epitaxial layer 24 is, for example, about 3 μm to 8 μm. The p-type epitaxial layer 24 includes, for example, B (boron) as a p-type impurity, and its concentration is about 1 × 10 ¹⁶ cm ⁻³ to 1 × 10 ¹⁷ cm ⁻³ .
The n-type body region 28 includes, for example, P (phosphorus), As (arsenic) or the like as an n-type impurity, and its concentration is about 2 × 10 ¹⁶ cm ^{−3 to} 3 × 10 ¹⁷ cm ⁻³ .

The p-type drain region 29 contains, for example, B (boron) or the like as a p-type impurity, and its concentration is about 1 × 10 ¹⁶ cm ⁻³ to 1 × 10 ¹⁷ cm ⁻³ .
The p ⁺ type source regions 37 and 39 include, for example, B (boron) as a p type impurity, and the concentration thereof is about 1 × 10 ²¹ cm ^{−3 to} 5 × 10 ²¹ cm ⁻³ .
The n ⁺ -type body contact regions 38 and 40 include, for example, P (phosphorus), As (arsenic), etc. as n-type impurities, and the concentration thereof is about 1 × 10 ²¹ cm ^{−3 to} 5 × 10 ²¹ cm ⁻³ . is there.

The gate insulating film 41 is made of, for example, SiO ₂ (silicon oxide), and the gate electrode 42 is made of, for example, polysilicon (doped polysilicon).
The interlayer insulating film 46 is made of, for example, SiO ₂ (silicon oxide), and the surface protective film 50 is made of, for example, SiN (silicon nitride).
The gate wiring 9, the first source wiring 10, the second source wiring 11, and the drain electrode 53 are made of, for example, Al or an alloy containing Al.

4A and 4B are diagrams showing a circuit configuration of the semiconductor chip 6. FIG. 4A shows a configuration in which no potential is applied to the drain (the drain is electrically floating), and FIG. In this configuration, a potential is applied. FIG. 5 is a diagram illustrating the IV characteristics of the semiconductor chip 6.
Next, the operation of the semiconductor chip 6 will be described with reference to FIG. 2 and FIGS. 4A and 4B. The correspondence relationship between the alphabetical symbols in FIGS. 4A and 4B and the components in FIG. 2 is as follows.

First source S ₁ : First source wiring 10 Second source S ₂ : Second source wiring 11
Drain D: Drain electrode 53 Gate G: Gate wiring 9
First, in a state in which a voltage to the gate G is not applied, the voltage between (between S ₁ -S ₂₎ of the first source S ₁ and the second source S ₂ is applied. More specifically, the positive voltage (+) is applied to the first source S _1, the voltage of the second source S ₂ and the gate G is set to 0V. In the configuration of FIG. 4A, the drain D is electrically floating. On the other hand, as shown in FIG. 4B, the drain D may be used as a terminal. Since the first and second gate electrodes 43 and 44 are commonly connected to the third gate electrode 45, they are held at the same potential.

In the first transistor Tr1, the potential of the n-type body region 28 becomes the same positive potential as that of the first source wiring 10 (first source S ₁ ) via the n ⁺ -type body contact region 38. As a result, due to the potential difference between the n-type body region 28 and the first gate electrode 43, holes, which are minority carriers in the n-type body region 28, contact the gate insulating film 41 and the n-type body region 28. Attracted to the surface. Then, a channel is formed by the attracted holes, the first transistor Tr 1 is turned on, and a current I ₁ flows from the first source S ₁ to the p-type drain region 29 via the parasitic diode 54.

By turning on the first transistors Tr1, the potential of the drain D is substantially the same potential as the first source S _1, a high potential second for the source S _2. As a result, a forward voltage is applied to both ends of the parasitic diode 55 of the second unit cell 32 to turn on the parasitic diode 55, and between the p-type drain region 29 and the second source S ₂ via the parasitic diode 55. And become conductive. The current I ₁ flowing to the p-type drain region 29 flows from the p-type drain region 29 to the second source S ₂ as the current I ₂ . As a result, the first source _{S 1} and a current flows between _(between S 1 -S ₂₎ and the second source _{S 2.}

On the other hand, when a positive voltage is applied to the gate G and the potential difference (VGS ₁ ) between the gate G and the first source S ₁ approaches 0, the n-type body region 28 of the first unit cell 31 is formed. The channel disappears and the first transistor Tr1 is turned off. Thus, current between _(between S 1 -S ₂₎ of the first source _{S 1} and the second source _{S 2} is blocked.
Thus, S ₁ -S ₂ conducts when no voltage is applied to the gate G, while S ₁ -S ₂ is cut off when a voltage is applied to the gate G. That is, a normally-on operation is realized. More specifically, as shown in FIG. 5, the semiconductor chip 6 having the structure of FIG. 2, during the first source _{S 1} and the second source _{S 2 (S} 1 -S ₂ between) the voltage of 5V When no voltage was applied to the gate G, a current IS ₁ S ₂ of about 2.2 mA flowed between S _{1 and} S ₂ . On the other hand, as the voltage applied to the gate G was increased, the current IS ₁ S ₂ decreased, and the current IS ₁ S ₂ was cut off when the voltage value of the gate G was about 4.5V.

  In the first transistor Tr1 and the second transistor Tr2 that turn on and off the current in the semiconductor chip 6, unlike the JFET and the depletion type MISFET, the spread of the depletion layer is not used for turning on and off the current. Therefore, it is not necessary to design the impurity concentration of each impurity region (28, 29, 37, 39, etc.) of the semiconductor layer 22 in consideration of the depletion layer, so that a low resistance value can be maintained even if the size is reduced. it can. In addition, in the semiconductor chip 6, the first transistor Tr1 and the second transistor Tr2 are integrated into one chip, so that further downsizing can be achieved.

Furthermore, between the first active region 25 and the second active region 26, the entire region on the back side of the front surface portion of the semiconductor layer 22 (in this embodiment, a region below the bottom portion of the gate trench 30), The p-type drain region 29 is occupied. For this reason, there is no structure that obstructs the current flowing between the first active region 25 and the second active region 26 (for example, an element isolation structure using an insulating film), so that the current flows in a wide range in the thickness direction of the semiconductor layer 22. A route can be secured. As a result, the low resistance value in the semiconductor layer 22 can be favorably maintained.
<Other embodiments>
Hereinafter, other embodiments of the semiconductor package 1 and the semiconductor chip 6 described with reference to FIGS. 1 to 5 will be described.

FIG. 6 is a schematic cross-sectional view of a semiconductor chip 6 according to another embodiment of the present invention.
In the semiconductor chip 6 shown in FIG. 2, the third gate electrode 45 embedded in the gate trench 30 is used as an electrode for commonly connecting the first gate electrode 43 and the second gate electrode 44. The three gate electrode 45 may be omitted.
In this case, the first gate electrode 43 and the second gate electrode 44 are, as shown in FIG. 6, a third gate electrode 56 formed along the surface of the semiconductor layer 22 (p-type epitaxial layer 24) in the central region 27. May be connected to each other. The third gate electrode 56 extends across the first gate electrode 43 and the second gate electrode 44 and is connected to the first gate electrode 43 and the second gate electrode 44 from above.

Further, as shown in FIG. 6, the n-type body region 28 in the central region 27 may be omitted, and the omitted portion may be occupied by a part of the p-type drain region 29. This configuration may be applied to the configuration shown in FIG.
FIG. 7 is a schematic configuration diagram of a semiconductor package 1 according to another embodiment of the present invention. FIG. 8 is a cross-sectional view that appears when the semiconductor chip 6 of FIG. 7 is cut along the VIII-VIII cutting line. FIG. 9 is a diagram showing a cell layout of the first transistor Tr1 and the second transistor Tr2. In FIG. 7, the gate finger 13 is omitted.

In the semiconductor chip 6 of FIG. 2, the region on the semiconductor layer 22 is divided into two, and the first active region 25 is formed on one side and the second active region 26 is formed on the other side. The first source line 10 and the second source line 11 were formed in a planar shape so as to cover the first active region 25 and the second active region 26, respectively.
On the other hand, in the semiconductor chip 6 of FIG. 7, the first source wiring 10 and the second source wiring 11 are formed in a comb-teeth shape that meshes with a space therebetween. In this case, as shown in FIGS. 8 and 9, the semiconductor layer 22 includes a linear first unit cell row 57 including a plurality of first unit cells 31 and a plurality of second unit cells 32. The straight second unit cell rows 58 may be alternately arranged at intervals.

As shown in FIG. 9, the teeth 59 and 60 of the comb-like first source wiring 10 and second source wiring 11 are respectively located above the first unit cell row 57 and the second unit cell row 58, respectively. By providing, the contact between the first source line 10 and the first transistor Tr1 (p ⁺ -type source region 37) and the contact between the second source line 11 and the second transistor Tr2 (p ⁺ -type source region 39) are facilitated. Can be taken.

7 to 9, since the distance from the first transistor Tr1 to the second transistor Tr2 can be made uniform over the entire semiconductor layer 22 regardless of the position of the first transistor Tr1, current variation between cells is suppressed. can do.
FIG. 10 is a schematic cross-sectional view of a semiconductor chip 6 according to another embodiment of the present invention.
In the semiconductor chip 6 of FIG. 2, MISFETs having a trench gate structure are employed as the first transistor Tr1 and the second transistor Tr2, but a MISFET having a planar gate structure may be employed as shown in FIG.

In the first and second transistors Tr1 and Tr2 having the planar gate structure, the gate insulating film 41 is formed on the surface of the semiconductor layer 22, and the gate electrode 42 is formed on the gate insulating film 41. The first gate electrode 43 and the second gate electrode 44 are opposed to the portion of the n-type body region 28 exposed on the surface of the semiconductor layer 22.
FIG. 11 is a diagram showing a cell layout of the first transistor Tr1 and the second transistor Tr2.

In the semiconductor chip 6 of FIG. 2, the plurality of first unit cells 31 (first transistors Tr1) and the plurality of second unit cells 32 (second transistors Tr2) are respectively constant regions (first active regions 25 and first transistors). 2 active areas 26).
On the other hand, as shown in FIG. 11, the plurality of first unit cells 31 and the plurality of second unit cells 32 arranged in a matrix may be alternately arranged in the row direction and the column direction. Also with this configuration, the distance from the first transistor Tr1 to the second transistor Tr2 can be made uniform over the entire semiconductor layer 22 as in the configurations shown in FIGS. be able to.

FIG. 12 is a schematic configuration diagram of a semiconductor package 1 according to another embodiment of the present invention.
In the semiconductor package 1 shown in FIG. 1, the first transistor Tr1 and the second transistor Tr2 are integrated into one semiconductor chip 6 to form a single chip. However, the semiconductor package 1 may satisfy the circuit configuration diagram shown in FIGS. 4A and 4B. For example, a form as shown in FIG.
The semiconductor package 1 of FIG. 12 includes an island 68, a plurality of terminals 62 to 64, a first semiconductor chip 65, a second semiconductor chip 66, and a sealing resin 7.

In the island 68, both the first semiconductor chip 65 and the second semiconductor chip 66 are provided. That is, the island 68 may be a common electrode for the drains of the first semiconductor chip 65 (first transistor Tr1) and the second semiconductor chip 66 (second transistor Tr2).
The plurality of terminals 62 to 64 include a first source terminal 62, a second source terminal 63, and a gate terminal 64.

The first source terminal 62 is connected to the source pad 70 of the first semiconductor chip 65 through the bonding wire 69. On the other hand, the second source terminal 63 is connected to the source pad 72 of the second semiconductor chip 66 through the bonding wire 71.
The gate terminal 64 is connected to the gate pad 75 of the first semiconductor chip 65 and the gate pad 76 of the second semiconductor chip 66 via bonding wires 73 and 74. That is, the gate terminal 64 is a common electrode for the gates of the first semiconductor chip 65 (first transistor Tr1) and the second semiconductor chip 66 (second transistor Tr2).

  FIG. 13 is a schematic perspective view of a semiconductor package 1 according to another embodiment of the present invention. FIG. 14 is a schematic plan view of the semiconductor package 1 of FIG. FIG. 15 is a schematic cross-sectional view of the semiconductor package 1 of FIG. Note that FIG. 15 does not show a cross section of the specific part of FIGS. 13 and 14, but selectively shows the components necessary for explaining the internal structure of the semiconductor package 1.

  13 and 14 has a package structure of WL-CSP (Wafer Level-Chip Size Package). That is, in the semiconductor package 1, the above-described semiconductor chip 6 has a semiconductor layer 22 (semiconductor substrate) having a rectangular shape in plan view, and is configured to have almost the same size as the outer size of the semiconductor layer 22. For example, the length L of the semiconductor package 1 is less than 0.50 mm (preferably 0.40 mm or more), the width W is less than 0.40 mm (preferably 0.30 mm or more), and the thickness D is 0. Less than 15 mm (preferably 0.10 mm or more). That is, the semiconductor package 1 has a very small package structure of 0403 size. Further, since the thickness of the semiconductor package 1 is less than 0.15 mm, the amount of protrusion from the normal position of the side surface of the semiconductor package 1 can be reduced even when the semiconductor package 1 is mounted with an inclination. Thereby, even when the semiconductor package 1 is mounted with high density, contact with an adjacent semiconductor package can be suppressed.

  Since the semiconductor package 1 has a WL-CSP package structure, when the shape and size of the semiconductor package 1 and the semiconductor layer 22 and the arrangement positions of other components are described below, It may be replaced with the other. For example, the semiconductor layer 22 having a quadrilateral shape in plan view may be replaced with the semiconductor package 1 having a quadrangular shape in plan view, and the description that the pads are disposed on the peripheral portion of the semiconductor layer 22 It may be replaced with the description that the pads are arranged in

  The rectangular parallelepiped semiconductor layer 22 has a front surface 22A, a back surface 22B opposite to the front surface 22A, and four side surfaces 22C, 22D, 22E, and 22F between the front surface 22A and the back surface 22B. 22C to 22F are covered with the surface protective film 50 (see FIG. 15). Of the four side surfaces 22C to 22F of the semiconductor layer 22, the side surfaces 22C and 22E are side surfaces along the long side 77 of the semiconductor layer 22, and the side surfaces 22D and 22F are side surfaces along the short side 78 of the semiconductor layer 22. Corner portions 80CD, 80DE, 80EF, and 80FC of the semiconductor layer 22 are formed at the intersections of the adjacent side surfaces 22C to 22F.

  On the surface 22A of the semiconductor layer 22, a first source pad 83 is disposed on the first peripheral edge 81 along one side surface 22C on the long side 77 side. As shown in FIG. 15, the first source pad 83 is a portion where a part of the first source wiring 10 is exposed from the pad opening 51. The first source pad 83 is formed at a central portion spaced from both end corners 80CD and 80FC of the first peripheral edge 81, and between the first source pad 83 and each corner 80CD and 80FC, A region with a constant interval (for example, about 0.1 mm to 0.15 mm) covered with the surface protective film 50 is provided.

  On the other hand, a second source pad 84 is disposed at one end corner 80EF of the second peripheral edge 82 of the semiconductor layer 22 facing the first peripheral edge 81, and at the other end corner 80DE of the second peripheral edge 82, A gate pad 85 is disposed. As shown in FIG. 15, the second source pad 84 is a portion where a part of the second source wiring 11 is exposed from the pad opening 52. On the other hand, the gate pad 85 is a portion where a part of the gate wiring 9 is exposed from the pad opening 79 (see FIGS. 13 and 14) at a position not shown in FIG.

  In the semiconductor package 1 of FIGS. 13 to 15, the layout of the gate wiring 9, the first source wiring 10 and the second source wiring 11 is the layout shown in FIG. 1 (arranged at the corner 80DE of the gate pad 85). The gate wiring 9, the first source wiring 10, and the second source wiring 11 may have an appropriate shape and size so as not to interfere with each other by making the structure on the semiconductor layer 22 a multilayer wiring structure. You may be drawn around.

Next, the layout and shape of the first source pad 83, the second source pad 84, and the gate pad 85 will be described.
As shown in FIG. 14, the first source pad 83 is centered on the vertex V1 of the one end corner 80EF of the second peripheral edge 82, and the length of the short side 78 (width W in FIG. 13) of the semiconductor layer 22 is a radius. And a second arc whose radius is the length (width W in FIG. 13) of the short side 78 of the semiconductor layer 22 centered on the vertex V2 of the other end corner 80DE of the second peripheral edge 82. 87 is drawn on the surface 22 </ b> A of the semiconductor layer 22, it is disposed outside the first arc 86 and outside the second arc 87. The first source pad 83 has two sides of a pair of tangent lines drawn from the intersection 88 of the first arc 86 and the second arc 87 with respect to each of the first arc 86 and the second arc 87 in the outer region. It is formed in a triangular shape.

On the other hand, the second source pad 84 is formed in a fan shape having the same center as the first arc 86. The radius R1 of the second source pad 84 is, for example, 0.1 mm to 0.13 mm. The gate pad 85 is formed in a fan shape having the same center as the second arc 87. The radius R2 of the gate pad 85 is, for example, 0.1 mm to 0.13 mm.
Since the semiconductor package 1 of FIGS. 13 to 15 has a WL-CSP package structure, all the electrical connections inside the package are wireless structures that do not use bonding wires. As a result, the wire resistance can also be reduced, and the on-resistance per package size can be greatly reduced.

Further, although the semiconductor package 1 has a WL-CSP package structure, the side surfaces 22 </ b> C to 22 </ b> F of the semiconductor layer 22 are covered with the surface protective film 50. Therefore, when the semiconductor package 1 is mounted with high density, it is possible to prevent a short circuit between adjacent semiconductor packages.
As mentioned above, although one Embodiment of this invention was described with reference to FIGS. 1-15, the structure of the semiconductor package 1 and the semiconductor chip 6 is not restricted to the above-mentioned thing, The thing of the matter described in the claim Various design changes can be made within the range.

For example, in the above-described embodiment, only the vertical structure element is shown as the structure of the first transistor Tr1 and the second transistor Tr2. However, a horizontal structure element can also be applied.
FIG. 16 is a schematic perspective view of a semiconductor device 101 according to an embodiment of the present invention. FIG. 17 is a schematic plan view of a semiconductor device 101 according to an embodiment of the present invention.

The semiconductor device 101 has a package structure of WL-CSP (Wafer Level-Chip Size Package). In other words, the semiconductor device 101 includes a semiconductor substrate 102 that is rectangular in plan view, and is configured to have substantially the same size as the outer size of the semiconductor substrate 102. For example, the length L of the semiconductor device 101 is less than 0.50 mm (preferably 0.40 mm or more), the width W is less than 0.40 mm (preferably 0.30 mm or more), and the thickness D is 0. Less than 15 mm (preferably 0.10 mm or more). For example, when the length L of the semiconductor device 101 is 0.50 mm and the width W is 0.40 mm, the planar area of the semiconductor device 101 is 0.20 mm ² . When the length L of the semiconductor device 101 is 0.40 mm and the width W is 0.30 mm, the planar area of the semiconductor device 101 is 0.12 mm ² . That is, the semiconductor device 101 has a very small package structure of 0403 size. Further, since the thickness of the semiconductor device 101 is less than 0.15 mm, the amount of protrusion from the normal position of the side surface of the semiconductor device 101 can be reduced even when the semiconductor device 101 is mounted with an inclination. Thereby, even when the semiconductor device 101 is mounted at high density, contact with an adjacent semiconductor device can be suppressed.

  Since the semiconductor device 101 has a WL-CSP package structure, when the shape and size of the semiconductor device 101 and the semiconductor substrate 102, the arrangement positions of other components, and the like are described below, It may be replaced with the other. For example, the semiconductor substrate 102 having a quadrangular shape in plan view may be replaced with the semiconductor device 101 having a quadrangular shape in plan view, and the description that the pads are arranged on the peripheral portion of the semiconductor substrate 102 It may be replaced with the description that the pads are arranged in

  The rectangular parallelepiped semiconductor substrate 102 has a front surface 102A, a back surface 102B opposite to the front surface 102A, and four side surfaces 102C, 102D, 102E, and 102F between the front surface 102A and the back surface 102B. 102C to 102F are covered with the surface insulating film 103. Of the four side surfaces 102C to 102F of the semiconductor substrate 102, the side surfaces 102C and 102E are side surfaces along the long side 121 of the semiconductor substrate 102, and the side surfaces 102D and 102F are side surfaces along the short side 122 of the semiconductor substrate 102. Corner portions 104CD, 104DE, 104EF, and 104FC of the semiconductor substrate 102 are formed at the intersections of the adjacent side surfaces 102C to 102F.

  On the surface 102A of the semiconductor substrate 102, a drain pad 107 (first pad) is disposed on the first peripheral edge 105 along one side surface 102C on the long side 121 side. The drain pad 107 is formed at the center of the first peripheral edge 105 spaced from both corners 104CD and 104FC, and between the drain pad 107 and each corner 104CD and 104FC, the surface insulating film 103 is formed. A region of a constant interval (for example, about 0.1 mm to 0.15 mm) covered with is provided.

On the other hand, a source pad 108 (second pad) is arranged at one end corner 104EF of the second peripheral edge 106 of the semiconductor substrate 102 facing the first peripheral edge 105, and the other end corner 104DE of the second peripheral edge 106. The gate pad 109 (third pad) is disposed in the gate.
Next, the layout and shape of the drain pad 107, the source pad 108, and the gate pad 109 will be described.

  As shown in FIG. 17, the drain pad 107 is centered on the vertex V1 of the one end corner 104EF of the second peripheral edge 106, and the length of the short side 122 of the semiconductor substrate 102 (width W in FIG. 16) is the radius. A first arc 110 and a second arc 111 centered on the vertex V2 of the other end corner portion 104DE of the second peripheral edge portion 106 and having a radius of the length (width W in FIG. 16) of the short side 122 of the semiconductor substrate 102; Is drawn on the surface 102 </ b> A of the semiconductor substrate 102, it is disposed outside the first arc 110 and outside the second arc 111. The drain pad 107 has two sides of a pair of tangent lines drawn from the intersection 112 of the first arc 110 and the second arc 111 to each of the first arc 110 and the second arc 111 in the outer region. It is formed in a triangular shape.

On the other hand, the source pad 108 is formed in a fan shape having the same center as the first arc 110. The radius R1 of the source pad 108 is, for example, 0.07 mm to 0.13 mm (preferably 0.10 mm or more). For example, when the radius R1 is 0.07 mm, the area of the source pad 108 is 3.85 × 10 ⁻³ mm ² , and when the radius R1 is 0.10 mm, the area of the source pad 108 is 7.85 × 10 ⁻³ mm ² . The gate pad 109 is formed in a fan shape having the same center as the second arc 111. The radius R2 of the gate pad 109 is, for example, 0.07 mm to 0.13 mm (preferably 0.10 mm or more). For example, when the radius R2 is 0.07 mm, the area of the gate pad 109 is 3.85 × 10 ⁻³ mm ² , and when the radius R2 is 0.10 mm, the area of the gate pad 109 is 7.85 × 10 ⁻³ mm ² .

Next, how much the mounting area of the semiconductor device 101 can be reduced by the layout and shape of the drain pad 107, the source pad 108, and the gate pad 109 described above will be described with reference to FIG.
FIG. 18 is a diagram for comparing the chip sizes of the semiconductor device 101 and the semiconductor device 200 according to the comparative example. In FIG. 18, for the sake of clarity, only the reference symbols necessary for comparison among the reference symbols shown in FIGS. 16 and 17 are shown, and the other reference symbols are omitted.

  First, when the source pad 108 and the gate pad 109 are arranged adjacent to each other on the short side 122 of the semiconductor substrate 102 as in the comparative semiconductor device 200, the package size of the semiconductor device 200 is, for example, the length L = 0.6 mm and width W = 0.4 mm. This is to secure at least the pitch P = 0.2 mm as the distance between the source pad 108 and the gate pad 109 in order to avoid a short circuit between the source and the gate in the short side direction. The drain pad 107 is formed in a shape extending from one end corner of the short side 122 to the other end corner. Therefore, if the package size is reduced without changing the pad layout, the source-gate pitch P is less than 0.2 mm, which causes a problem of short-circuiting between the source and gate during mounting. On the other hand, even if the source pad 108 and the gate pad 109 are arranged adjacent to each other on the long side 121, it is difficult to solve the problem of short circuit between the pads. This is because, in this pad layout, the drain pad 107 has a shape extending from one end corner portion of the long side 121 to the other end corner portion, as indicated by reference numeral “107 ′” and a broken line. Therefore, a short circuit between the source and the drain or between the gate and the drain occurs as the package size decreases.

On the other hand, in the configuration of the semiconductor device 101 described above, the source pad 108 and the gate pad 109 are arranged adjacent to each other on the long side 121. Further, the drain pad 107 is disposed at the center of the long side 121 of the semiconductor substrate 102, and the surface insulating film 103 is covered between the drain pad 107 and both corners 104 CD and 104 FC of the long side 121. A region with a constant interval is provided. Thereby, the distance (pitch P1) between the drain pad 107 and the source pad 108 and the distance (pitch P2) between the drain pad 107 and the gate pad 109 can be made longer than those of the semiconductor device 200 of the comparative example. Therefore, even if the package size of the semiconductor device 101 is reduced to, for example, a length L = 0.44 mm and a width W = 0.32 mm, the pitch P1 and the pitch P2 are set to the source-gate pitch P in the semiconductor device 200. Can be maintained at 0.2 mm, which is equivalent to That is, the distance secured between the pads is 0.20 / 0.32 = 62.5% or more of the short side 122 of the package of the semiconductor device 101. At least when the short side 122 of the package is 0.40 mm, the distance secured between the pads is 0.20 / 0.40 = 50% or more of the short side 122 of the package of the semiconductor device 101. Further, when the package size of the semiconductor device 101 is 1.41 × 10 ⁻¹ mm ² and the pad radii R1 and R2 are 0.10 mm, the pad area is 7.85 × 10 ⁻³ mm ^2. The area of the pad 108 and the gate pad 109 (pad area) is 5% or more of the package size. Therefore, the size of the semiconductor substrate can be made smaller than that of the semiconductor device 200 while avoiding a short circuit during mounting. Thereby, a miniaturized semiconductor device can be provided.

  In the semiconductor device 101, as shown in FIG. 17, the drain pad 107 is disposed in the outer region of the first arc 110 and the second arc 111 each having the radius of the short side 122. Therefore, at least the length corresponding to the difference between the length of the short side 122 of the semiconductor device 101 and the size (width) of the source pad 108 and the gate pad 109 can be secured as the pitch P1 and the pitch P2. Further, the drain pad 107 is formed in a triangular shape having a pair of tangent lines drawn from the intersection 112 of the first arc 110 and the second arc 111 with respect to the first arc 110 and the second arc 111, respectively. ing. Thereby, it is possible to secure a sufficient bonding area for the drain pad 107 while reducing the size of the semiconductor device 101. Therefore, it is possible to suppress a decrease in the adhesion strength when the semiconductor device 101 is mounted.

  Regarding securing of the fixing strength when the semiconductor device 101 is mounted, the source pad 108 and the gate pad 109 are further formed in a fan shape having the same center as the first arc 110 and the second arc 111, respectively. Thereby, it is possible to secure a sufficient bonding area for the source pad 108 and the gate pad 109 while securing a length of 0.2 mm as the pitch P1 and the pitch P2.

As described above, according to the semiconductor device 101, the mounting area can be reduced by about 40% as compared with the semiconductor device 200 of the comparative form, while ensuring a sufficient pitch between adjacent pads and a bonding area of the pads.
Next, the internal structure of the semiconductor device 101 will be described with reference to FIGS.
19 to 21 are diagrams showing the internal structure of the semiconductor device 101. 19 mainly shows a layout of the active region 113, FIG. 20 mainly shows a layout of the first wiring layer 144, and FIG. 21 mainly shows a layout of the top wiring layer 154. FIG. 22 is a diagram showing the surface structure of the semiconductor device 101 and mainly shows the layout of the pad openings 160 to 162. 23 and 24 are schematic cross-sectional views of the semiconductor device 101. FIG. FIG. 23 shows a source-side cross section of the active region 113, and FIG. 24 shows a drain-side cross section of the active region 113. FIG. 25 is a schematic cross-sectional view of the semiconductor device 101 and shows a cross-section of the protection diode region 114. 23 to 25 do not show a cross section of a specific portion of the plan views of FIGS. 19 to 21, but selectively show components necessary for explaining the internal structure of the semiconductor device 101. .

  As described above, the semiconductor device 101 includes the semiconductor substrate 102. An active region 113 and a protection diode region 114 are set in the semiconductor substrate 102. In this embodiment, as shown in FIG. 19, a protective diode region 114 having, for example, a rectangular shape in plan view is formed at one corner 104DE of the semiconductor substrate 102. The active region 113 is formed on substantially the entire surface region of the semiconductor substrate 102 excluding the corner portion 104DE with a certain distance from the protective diode region 114.

As shown in FIGS. 23 and 24, the semiconductor substrate 102 includes, on the surface thereof, an isolation well 115 that separates a part of the active region 113 from another part as an electrically floating region. More specifically, the semiconductor substrate 102 includes a p-type silicon substrate 116 and an n ⁻ -type epitaxial layer 117 formed on the p-type silicon substrate 116. The p-type isolation well 115 is formed in a band shape that draws a closed curve in plan view, and reaches the p-type silicon substrate 116 from the surface 102A of the n ⁻ -type epitaxial layer 117. The thickness of the n ⁻ type epitaxial layer 117 is, for example, 5.0 μm to 10 μm.

The isolation well 115 has a two-layer structure of a p ⁺ type well region 118 disposed on the upper side and a p ⁻ type low isolation (L / I) region 119 disposed on the lower side. A boundary between 118 and 119 is set in the middle of the n ⁻ type epitaxial layer 117 in the thickness direction. For example, the boundary between regions 118 and 119 is set to a depth position of 1.0 μm to 2.0 μm from surface 102 A of n ⁻ type epitaxial layer 117.

As a result, the semiconductor substrate 102 is partitioned with an element region 120 formed of a part of the n ⁻ -type epitaxial layer 117 surrounded by the isolation well 115 on the p-type silicon substrate 116.
An n ⁺ type buried layer (B / L) 123 is selectively formed in the element region 120. The n ⁺ type buried layer 123 is formed in the semiconductor substrate 102 so as to straddle the boundary between the p type silicon substrate 116 and the n ⁻ type epitaxial layer 117. The film thickness of the n ⁺ type buried layer 123 is, for example, 2.0 μm to 3.0 μm.

A field insulating film 124 is formed on the surface of the isolation well 115. Field insulating film 124 is, for example, a LOCOS film formed by selectively oxidizing the surface of n ⁻ type epitaxial layer 117.
In the element region 120, a DMOSFET (Double-Diffused MOSFET) 125 is formed. The DMOSFET 125 includes an n ⁻ type well region 126 and a p ⁻ type well region 127 formed on the surface of the n ⁻ type epitaxial layer 117 so as to be spaced from each other. The n ⁻ type well region 126 and the p ⁻ type well region 127 are stripes extending in the short side direction from the first peripheral edge 105 to the second peripheral edge 106 of the semiconductor substrate 102 as shown in the planes of FIGS. Are formed and arranged alternately. 19 to 22, for the sake of clarity, in addition to the n ⁻ type well region 126 and the p ⁻ type well region 127, a striped n ⁺ type drain region 128 (described later) formed in these inner regions. ), An n ⁺ -type source region 129 (described later) and an n ⁻ -type impurity region 130 (described later).

An n ⁺ type drain region 128 having a higher impurity concentration than the n ⁻ type well region 126 is formed on the surface of the n ⁻ type well region 126. An n ⁺ type source region 129 is formed on the surface of the p ⁻ type well region 127, and an n ⁻ type impurity region 130 is formed so as to surround the n ⁺ type source region 129.
The outer peripheral edge of the n ⁺ -type source region 129 is arranged at a position spaced a certain distance inward from the outer peripheral edge of the p ⁻ -type well region 127.

A field insulating film 131 is formed on the surface of the n ⁻ type epitaxial layer 117 at a portion between the n ⁻ type well region 126 and the p ⁻ type well region 127. The field insulating film 131 is a LOCOS film formed in the same process as the field insulating film 124 described above.
One peripheral edge of the field insulating film 131 is disposed on the peripheral edge of the n ⁺ -type drain region 128, and the other peripheral edge of the field insulating film 131 is n spaced apart from the outer peripheral edge of the n ⁻ -type well region 126 to the inside. Located on the ⁻ type well region 126. The n ⁺ -type drain region 128 is formed in a region sandwiched between the periphery of the field insulating film 131 and the field insulating film 124.

Further, n ^- the surface of the type epitaxial layer 117, n ^- -type epitaxial layer 117 and p ^- gate insulating film 132 so as to straddle between the type well region 127 is formed. A gate electrode 133 is formed via the gate insulating film 132. The gate electrode 133 is formed so as to selectively cover part of the gate insulating film 132 and part of the field insulating film 131.

The gate electrode 133 may be composed of, for example, a lower layer film 134 containing Poly-Si (polysilicon) and an upper layer film 135 containing WSi / Si (tungsten silicide / silicon). The gate insulating film 132 may be, for example, silicon oxide (SiO ₂ ) formed by oxidizing the surface of the n ⁻ type epitaxial layer 117.
A region where the gate electrode 133 faces the p ⁻ type well region 127 through the gate insulating film 132 is a channel region 136 of the DMOSFET 125. The formation of the channel in the channel region 136 is controlled by the gate electrode 133.

  On the other hand, in the protection diode region 114, as shown in FIG. 25, a protection diode 137 is formed on the gate insulating film 132. Protection diode 137 includes a p-type portion 138 and an n-type portion 139. The p-type portion 138 and the n-type portion 139 are formed in stripes extending in the short-side direction from the first peripheral edge 105 to the second peripheral edge 106 of the semiconductor substrate 102 as shown in the planes of FIGS. Are arranged alternately. The p-type portion 138 is disposed at both ends of the stripe pattern. The protective diode 137 includes a pair of p-type portion 138 and n-type portion 139 that are adjacent to each other. Further, similarly to the gate electrode 133, the protective diode 137 may have a two-layer structure of a lower layer film 134 and an upper layer film 135.

Then, a first interlayer film 140 and a second interlayer film 141 are formed so as to cover the entire surface region of the semiconductor substrate 102. The first interlayer film 140 and the second interlayer film 141 are formed of an insulating material such as silicon oxide (SiO ₂ ), for example. In this embodiment, the first interlayer film 140 and the second interlayer film 141 are formed, but a third, fourth, or more interlayer film is further formed as an upper layer film of the second interlayer film 141. It may be a configuration. Etching stop films 142 and 143 made of, for example, silicon nitride (SiN) are provided between the first interlayer film 140 and the semiconductor substrate 102 and between the second interlayer film 141 and the first interlayer film 140, respectively. It may be sandwiched. The etching stop film 142 may be formed on the field insulating films 124 and 131.

A first wiring layer 144 is formed on the first interlayer film 140. The first wiring layer 144 includes a source first metal 145, a drain first metal 146, and a gate first metal 147. These are made of a metal layer such as AlCu, for example, and a barrier layer (for example, Ti, TiN, etc.) may be formed on the front and back surfaces as necessary.
As shown in FIG. 20, the source first metal 145 is formed so as to cover a substantially half region on the second peripheral edge 106 side of the active region 113. Specifically, in order to avoid the protection diode region 114, the protection diode region 114 is formed on the side surface 102F side in the longitudinal direction and on the side surface 102C side in the width direction. Therefore, in the plan view, the substantially rectangular protective diode region 114 has two inner sides adjacent to the source first metal 145. The source first metal 145 is connected to the striped n ⁺ type drain region 128 and the source side end region 148 on the second peripheral edge 106 side of the n ⁺ type source region 129 via a plug (eg, tungsten plug) 149. , N ⁺ type source region 129. Further, as shown in FIG. 25, the source first metal 145 is connected to a p-type portion 138 disposed at one end of the protective diode 137 via a plug (for example, a tungsten plug) 150.

As shown in FIG. 20, the drain first metal 146 is formed so as to cover a substantially half region on the first peripheral edge 105 side of the active region 113. The drain first metal 146 is connected to the striped n ⁺ type drain region 128 and the drain side end region 151 on the first peripheral edge 105 side of the n ⁺ type source region 129 via a plug (for example, a tungsten plug) 152. , N ⁺ type drain region 128.

As shown in FIG. 25, the gate first metal 147 is connected to a p-type portion 138 disposed at the other end of the protective diode 137 via a plug (for example, a tungsten plug) 153. The gate first metal 147 is connected to the gate electrode 133 at a position not shown.
A top wiring layer 154 is formed on the second interlayer film 141. In this embodiment, since the second interlayer film 141 is the uppermost interlayer film, it is referred to as a top wiring layer 154. However, when a third interlayer film or the like is further formed on the second interlayer film 141, The wiring layer of the two interlayer film 141 may be referred to as a second wiring layer.

The top wiring layer 154 includes a source top metal 155, a drain top metal 156, and a gate top metal 157. These are made of a metal layer such as AlCu, for example, and a barrier layer (for example, Ti, TiN, etc.) may be formed on the front and back surfaces as necessary.
As shown in FIG. 21, the gate top metal 157 is formed in a fan shape similar to that of the gate pad 109 in a plan view. It overlaps with the source side end region 148. The gate top metal 157 is connected to the gate first metal 147 at a position not shown.

  As shown in FIG. 21, the source top metal 155 is formed so as to cover a substantially half region on the second peripheral edge 106 side of the active region 113. Specifically, the gate top metal 157 is formed on the side surface 102F side in the longitudinal direction and on the side surface 102C side in the width direction so as to avoid the gate top metal 157. Accordingly, the arc-shaped gate top metal 157 having a fan shape in plan view is adjacent to the source top metal 155. As shown in FIG. 23, the source top metal 155 is connected to the source first metal 145 via a plug (for example, a tungsten plug) 158.

As shown in FIG. 21, the drain top metal 156 is formed so as to cover a substantially half region on the first peripheral edge 105 side of the active region 113. As shown in FIG. 24, the drain top metal 156 is connected to the drain first metal 146 via a plug (for example, a tungsten plug) 159.
A surface insulating film 103 is formed on the second interlayer film 141 so as to cover the top wiring layer 154. The surface insulating film 103 covers the surface 102A side of the semiconductor substrate 102 and also covers the side surfaces 102C to 102F of the semiconductor substrate 102 (see FIG. 23). The surface insulating film 103 may be made of, for example, silicon nitride (SiN).

The surface insulating film 103 is formed with pad openings 160 to 162 exposing parts of the source top metal 155, the drain top metal 156, and the gate top metal 157 as the source pad 108, the drain pad 107, and the gate pad 109, respectively. ing.
As shown in FIG. 23, source terminals 163 (bumps) are formed on the source pad 108. As shown in FIG. 24, drain terminals 164 (bumps) are formed on the drain pad 107. Although not shown, gate terminals (bumps) are also formed on the gate pad 109. These terminals may have, for example, a stacked structure of a Ni layer 165, a Pd layer 166, and an Au layer 167 stacked by a plating method. By having the Au layer 167 on the outermost surface, it is possible to provide a highly reliable terminal (electrode) having excellent corrosion resistance and solder wettability.

  As described above, according to the semiconductor device 101, the source first metal 145, the source top metal 155, the drain first metal 146, and the drain top metal 156 are formed to have a size that covers approximately half of the active region 113. Has been. Thereby, a wide current path between the source and the drain can be secured. Therefore, an increase in on-resistance of the MIS transistor can be suppressed while the semiconductor device 101 is downsized. Further, since the semiconductor device 101 has a WL-CSP package structure, all the electrical connections inside the package are wireless structures that do not use bonding wires. As a result, the wire resistance can also be reduced, and the on-resistance per package size can be greatly reduced.

Although the semiconductor device 101 has a WL-CSP package structure, the side surfaces 102 </ b> C to 102 </ b> F of the semiconductor substrate 102 are covered with the surface insulating film 103. Therefore, when the semiconductor device 101 is mounted with high density, a short circuit between adjacent semiconductor devices can be prevented.
Next, a manufacturing process of the semiconductor device 101 will be described with reference to FIGS. 26A to 26F. 26A to 26F are cross-sectional views for explaining an example of the manufacturing process of the semiconductor device 101. 26A to 26F correspond to FIG. 23, respectively.

In order to manufacture the semiconductor device 101, a p-type silicon substrate 116 in a wafer state is prepared. Next, n-type impurities and p-type impurities are selectively implanted into the surface of the p-type silicon substrate 116. Then, for example, silicon of the p-type silicon substrate 116 is epitaxially grown at a temperature of 1100 ° C. or higher while adding n-type impurities. As a result, as shown in FIG. 26A, a semiconductor substrate 102 (wafer) including a p-type silicon substrate 116 and an n ⁻ -type epitaxial layer 117 is formed.

During the epitaxial growth of the p-type silicon substrate 116, the n-type impurity and the p-type impurity implanted into the p-type silicon substrate 116 diffuse in the growth direction of the n ⁻ -type epitaxial layer 117. As a result, an n ⁺ type buried layer 123 and a p ⁻ type low isolation region 119 straddling the boundary between the p type silicon substrate 116 and the n ⁻ type epitaxial layer 117 are formed. Examples of the p-type impurity include B (boron) and Al (aluminum). Examples of the n-type impurity include P (phosphorus) and As (arsenic). it can.

Next, an ion implantation mask (not shown) having an opening selectively in a region where the p ⁺ type well region 118 is to be formed is formed on the n ⁻ type epitaxial layer 117. Then, a p-type impurity is implanted into the n ⁻ -type epitaxial layer 117 through the ion implantation mask. As a result, an isolation well 115 having a two-layer structure of the p ⁺ type well region 118 and the p ⁻ type low isolation region 119 is formed. After the isolation well 115 is formed, the ion implantation mask is removed.

Next, a hard mask (not shown) having an opening selectively in a region where field insulating films 124 and 131 are to be formed is formed on n ⁻ type epitaxial layer 117. Then, the surface of the n ⁻ type epitaxial layer 117 is subjected to a thermal oxidation process through the hard mask to form field insulating films 124 and 131 made of a LOCOS film. Thereafter, the hard mask is removed.

Next, the surface of the n ⁻ type epitaxial layer 117 is subjected to a thermal oxidation process to form the gate insulating film 132. At this time, the gate insulating film 132 is formed to be continuous with the field insulating films 124 and 131. Next, a material for the gate electrode 133 is selectively formed on the n ⁻ type epitaxial layer 117, and the gate electrode 133 and the protection diode 137 (not shown) are formed.

Next, an n ⁻ type well region 126 and a p ⁻ type well region 127 are formed. In order to form the n ⁻ type well region 126, first, an ion implantation mask (not shown) having an opening selectively in a region where the n ⁻ type well region 126 is to be formed is formed. Then, n-type impurities are implanted into the n ⁻ -type epitaxial layer 117 through the ion implantation mask. Thereby, an n ⁻ type well region 126 is formed. After the n ⁻ type well region 126 is formed, the ion implantation mask is removed. In the same procedure, an ion implantation mask (not shown) having an opening selectively in a region where the p ⁻ type well region 127 is to be formed is formed. Then, a p-type impurity is implanted into the n ⁻ -type epitaxial layer 117 through the ion implantation mask. Thereby, a p ⁻ type well region 127 is formed. After the p ⁻ type well region 127 is formed, the ion implantation mask is removed.

Next, n ⁻ type impurity region 130 is formed in the inner region of p ⁻ type well region 127. In order to form the n ⁻ -type impurity region 130, first, an ion implantation mask (not shown) having an opening selectively in a region where the n ⁻ -type impurity region 130 is to be formed is formed. Then, n-type impurities are implanted into the p ⁻ -type well region 127 through the ion implantation mask. As a result, an n ⁻ type impurity region 130 is formed in the inner region of the p ⁻ type well region 127. After the n ⁻ type impurity region 130 is formed, the ion implantation mask is removed.

Next, an n ⁺ type drain region 128 and an n ⁺ type source region 129 are selectively formed in the inner regions of the n ⁻ type well region 126 and the p ⁻ type well region 127, respectively. In order to form the n ⁺ -type drain region 128 and the n ⁺ -type source region 129, first, an ion implantation mask having an opening selectively in a region where the n ⁺ -type drain region 128 and the n ⁺ -type source region 129 are to be formed ( (Not shown) is formed. Then, n-type impurities are implanted into the n ⁻ -type well region 126 and the p ⁻ -type well region 127 through the ion implantation mask. Thereby, an n ⁺ type drain region 128 and an n ⁺ type source region 129 are formed. After the n ⁺ type drain region 128 and the n ⁺ type source region 129 are formed, the ion implantation mask is removed.

  Next, as shown in FIG. 26B, an insulating material is deposited so as to cover the gate electrode 133 to form a first interlayer film 140. Next, plugs 149, 150, 152, and 153 are formed so as to penetrate the first interlayer film 140. Next, after an etching stop film 143 is formed on the first interlayer film 140, a source first metal 145, a drain first metal 146, and a gate first metal 147 are selectively formed.

  Next, as shown in FIG. 26C, an insulating material is deposited so as to cover the source first metal 145, the drain first metal 146, and the gate first metal 147, thereby forming the second interlayer film 141. Next, plugs 158 and 159 are formed so as to penetrate the second interlayer film 141. Next, a source top metal 155, a drain top metal 156, and a gate top metal 157 are selectively formed on the second interlayer film 141.

Next, an insulating material is deposited so as to cover the source top metal 155, the drain top metal 156, and the gate top metal 157, and the surface insulating film 103 is formed. Thereafter, the surface insulating film 103 is selectively removed to form pad openings 160 to 162.
Next, as shown in FIG. 26D, the semiconductor substrate 102 is selectively removed along a predetermined element boundary line by, for example, plasma etching. As a result, a groove 168 having a predetermined depth reaching from the surface 102A of the semiconductor substrate 102 to the middle of the thickness of the semiconductor substrate 102 is formed between adjacent transistor regions. The groove 168 is partitioned by a pair of side walls 168A facing each other and a bottom wall 168B connecting the lower ends of the pair of side walls 168A (the end on the back surface 102B side of the semiconductor substrate 102).

Next, as shown in FIG. 26E, an insulating film made of SiN is formed over the entire region on the surface 102A side of the semiconductor substrate 102 by the CVD method. At this time, the insulating film is also formed over the entire inner peripheral surface of the groove 168 (the side wall 168A and the bottom wall 168B described above). As a result, a portion covering the side surfaces 102C to 102F of the surface insulating film 103 is formed.
Next, Ni, Pd, and Au are sequentially grown from the source pad 108, the drain pad 107, and the gate pad 109 exposed from the pad openings 160 to 162 by electroless plating. As a result, as shown in FIG. 26E, a source terminal 163, a drain terminal 164 (not shown), and a gate terminal (not shown) made of a laminated film of the Ni layer 165 / Pd layer 166 / Au layer 167 are formed. .

  Next, a support tape (not shown) is attached to the front surface 102A side of the semiconductor substrate 102 in a wafer state, and in this state, the semiconductor substrate 102 is ground from the back surface 102B side. When the semiconductor substrate 102 is thinned by grinding until it reaches the upper surface of the bottom wall 168B of the groove 168, there is no connection between adjacent semi-finished products, so that the semiconductor substrate 102 is divided with the groove 168 as a boundary. Through the above steps, individual pieces of the semiconductor device 101 are obtained as shown in FIG. 26F.

As mentioned above, although one Embodiment of this invention was described with reference to FIGS. 16-26F, this invention can also be implemented with another form.
For example, the semiconductor substrate 102 does not need to have a rectangular shape in plan view, and may have another quadrangle such as a square shape in plan view.
Further, the drain pad 107 may be, for example, a circle or a semicircle in plan view, and the source pad 108 and the gate pad 109 may be, for example, a circle, triangle, or the like in plan view.

In the above-described embodiment, only the MOSFET structure is shown as an example of the element structure of the semiconductor device 101. However, the element incorporated in the semiconductor device 101 is, for example, another element such as an IGBT or a bipolar transistor. May be.
The semiconductor device of the present invention can be suitably used for a wearable device (for example, a smartphone, a tablet PC, etc.) that is an application that is particularly required to be downsized.

  In addition, various design changes can be made within the scope of matters described in the claims.

DESCRIPTION OF SYMBOLS 1 Semiconductor package 6 Semiconductor chip 7 Sealing resin 9 Gate wiring 10 1st source wiring 11 2nd source wiring 12 Gate pad 13 Gate finger 16 1st area | region 17 2nd area | region 22 Semiconductor layer 23 p ⁺ type semiconductor substrate 24 p-type epitaxial Layer 25 first active region 26 second active region 27 central region 28 n-type body region 29 p-type drain region 30 gate trench 31 first unit cell 32 second unit cell 33 third unit cell 34 first gate trench 35 second Gate trench 36 Third gate trench 37 p ⁺ type source region 39 p ⁺ type source region 41 Gate insulating film 42 Gate electrode 43 First gate electrode 44 Second gate electrode 45 Third gate electrode 53 Drain electrode 54 First parasitic diode 55 Second parasitic diode 5 Third gate electrode 57 First unit cell row 58 Second unit cell row 59 Tooth portion 60 Tooth portion 61 Drain terminal 62 First source terminal 63 Second source terminal 64 Gate terminal 65 First semiconductor chip 66 Second semiconductor chip 67 Sealing Resin Tr1 First transistor Tr2 Second transistor

Claims (25)

Enhancement-type first p-channel MISFET,
Enhancement-type second p-channel MISFET,
A drain conductor electrically connected in common to drains of the first p-channel MISFET and the second p-channel MISFET;
A first source conductor electrically connected to a source of the first p-channel MISFET;
A second source conductor electrically connected to a source of the second p-channel MISFET;
A semiconductor device comprising: a gate conductor electrically connected in common to the gates of the first p-channel MISFET and the second p-channel MISFET. A semiconductor layer having a common p-type drain region for the first p-channel MISFET and the second p-channel MISFET;
The first p-channel MISFET includes a first n-type body region formed on a surface portion of the semiconductor layer, a first p-type source region formed on a surface portion of the first n-type body region, and the first n-type body region. A first gate electrode opposite to
The second p-channel MISFET includes a second n-type body region formed on a surface portion of the semiconductor layer, a second p-type source region formed on a surface portion of the second n-type body region, and the second n-type body region. A second gate electrode opposite to
The drain conductor includes a drain electrode formed on the back surface of the semiconductor layer and connected to the p-type drain region,
The first source conductor includes a first source electrode connected to the first p-type source region,
The second source conductor includes a second source electrode disposed separately from the first source electrode and connected to the second p-type source region;
The semiconductor device according to claim 1, wherein the gate conductor includes a gate wiring commonly connected to the first gate electrode and the second gate electrode in the semiconductor layer. The semiconductor layer includes a first active region for the first p-channel type MISFET and a second active region for the second p-channel type MISFET disposed adjacent to the first active region,
The semiconductor device according to claim 2, wherein the gate wiring is provided in a region between the first active region and the second active region. A first gate trench formed immediately below the first active region;
A second gate trench formed immediately below the second active region;
A third gate trench formed between the first gate trench and the second gate trench and commonly connecting the first gate trench and the second gate trench;
The first gate electrode includes an electrode embedded in the first gate trench;
The second gate electrode includes an electrode embedded in the second gate trench;
The semiconductor device according to claim 3, wherein the gate wiring includes an electrode embedded in the third gate trench. A first gate trench formed immediately below the first active region;
A second gate trench formed directly under the second active region,
The first gate electrode includes an electrode embedded in the first gate trench;
The second gate electrode includes an electrode embedded in the second gate trench;
The gate wiring is formed in a region on the semiconductor layer, straddles the first gate electrode and the second gate electrode along the surface of the semiconductor layer, and each of the first gate electrode and the second gate electrode The semiconductor device according to claim 3, comprising an electrode connected to the upper side from the upper side.   In the region between the first active region and the second active region, a region on the back surface side of the semiconductor layer with respect to the surface portion of the semiconductor layer is occupied by the common p-type drain region. Item 6. The semiconductor device according to any one of Items 3 to 5. The gate wiring includes a gate pad and a gate finger connected to the gate pad and surrounding the first active region and the second active region,
The semiconductor device according to claim 3, wherein the first source electrode and the second source electrode are arranged in a region separated from each other by the gate finger. A linear first unit cell row constituted by a plurality of first unit cells of the first p-channel type MISFET;
A linear second unit cell row constituted by a plurality of second unit cells of the second p-channel type MISFET,
The first unit cell columns and the second unit cell columns are alternately arranged with a space therebetween,
The first source electrode has a base end portion on one end side of the first unit cell row and the second unit cell row, and is formed in a comb shape having a tooth portion on each first unit cell,
The second source electrode has a base end portion on the other end side of the first unit cell row and the second unit cell row, a tooth portion on each of the second unit cells, and the comb-like shape The semiconductor device according to claim 2, wherein the semiconductor device is formed in a comb-tooth shape that meshes with the first source electrode at an interval. A plurality of first unit cells of the first p-channel type MISFET and a plurality of second unit cells of the second p-channel type MISFET are arranged in a matrix as a whole;
The semiconductor device according to claim 2, wherein the plurality of first unit cells and the plurality of second unit cells are alternately arranged in each of a row direction and a column direction. A semiconductor device according to any one of claims 1 to 9,
A semiconductor package including a sealing resin for sealing all or part of the semiconductor device. A semiconductor substrate having a rectangular shape in plan view, having a front surface, a back surface opposite to the front surface, and a side surface between the front surface and the back surface;
A surface insulating film formed on the semiconductor substrate so as to cover at least the surface;
A first pad disposed on the front side of the semiconductor substrate at a central portion of the first peripheral edge along one of the side surfaces of the semiconductor substrate and spaced from both corners of the first peripheral edge;
A second pad disposed at one end corner of the second peripheral edge facing the first peripheral edge of the semiconductor substrate;
And a third pad disposed at the other end corner of the second peripheral edge of the semiconductor substrate. The semiconductor substrate includes a rectangular semiconductor substrate in plan view,
The semiconductor device according to claim 11, wherein the first peripheral edge and the second peripheral edge include a peripheral edge along a longitudinal direction of the semiconductor substrate. Centering on the apex of one end corner of the second peripheral edge, the first arc having a radius of the short side of the semiconductor substrate as the radius, and the apex of the other end corner of the second peripheral edge, When a second arc having a radius of the short side of the semiconductor substrate is drawn on the surface of the semiconductor substrate,
The semiconductor device according to claim 12, wherein the first pad is disposed in an outer region of the first arc and in an outer region of the second arc. The first arc and the second arc have a size that intersects each other in a region on the semiconductor substrate;
The first pad is formed in a triangular shape having two sides of a pair of tangent lines drawn from the intersection of the first arc and the second arc with respect to the first arc and the second arc, respectively. The semiconductor device according to claim 13.   The semiconductor device according to claim 13, wherein the second pad is formed in a fan shape having the same center as the first arc.   The semiconductor device according to claim 13, wherein the third pad is formed in a fan shape having the same center as the second arc. Including a MIS transistor structure formed on the semiconductor substrate;
The first pad includes a drain pad electrically connected to a drain of the MIS transistor structure,
The second pad includes a source pad electrically connected to a source of the MIS transistor structure,
The semiconductor device according to claim 11, wherein the third pad includes a gate pad electrically connected to a gate of the MIS transistor structure. The semiconductor substrate includes an active region in which the MIS transistor structure is formed,
The MIS transistor structure is formed in a stripe shape extending in a direction from the first peripheral edge to the second peripheral edge, and includes a plurality of alternately arranged source and drain regions,
A first interlayer film formed on the semiconductor substrate so as to cover the source region and the drain region;
The active region is formed on the first interlayer film so as to cover a substantially half region on the second peripheral edge side of the active region, and is electrically connected to the source region at an end of the source region on the second peripheral edge side. Connected first source wiring layers;
The active region is formed on the first interlayer film so as to cover a substantially half region on the first peripheral edge side of the active region, and is electrically connected to the drain region at an end of the drain region on the first peripheral edge side. The semiconductor device according to claim 17, further comprising a connected first drain wiring layer. A second interlayer film formed on the first interlayer film so as to cover the first source wiring layer and the first drain wiring layer;
The active region is formed on the second interlayer film so as to cover a substantially half region on the second peripheral edge side, and is electrically connected to the first source wiring layer, a part of which is the source A second source wiring layer exposed from the surface insulating film as a pad;
The active region is formed on the second interlayer film so as to cover a substantially half region on the first peripheral edge side, and is electrically connected to the first drain wiring layer, a part of which is the drain The semiconductor device according to claim 18, further comprising: a second drain wiring layer exposed from the surface insulating film as a pad. The semiconductor substrate includes a protective diode region outside the active region;
The semiconductor device according to claim 19, further comprising: a gate wiring layer formed on the second interlayer film so as to cover the protection diode region, a part of which is exposed from the surface insulating film as the gate pad.   The semiconductor device according to claim 11, wherein the surface insulating film is further formed to cover the side surface of the semiconductor substrate.   The semiconductor device according to claim 11, having a chip size package structure.   23. The semiconductor device according to claim 22, wherein the chip size package structure includes a long side of less than 0.50 mm and a short side of less than 0.40 mm.   24. The semiconductor device according to claim 22, wherein the chip size package structure is formed with a thickness of less than 0.15 mm.   The semiconductor device according to any one of claims 12 to 16, wherein a distance between each of the first pad, the second pad, and the third pad is 50% or more of a short side of the semiconductor substrate.

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