JP2016086006A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device that can suppress generation of burrs of a metal layer when individualized into chips, and that has a high reliability and a high yield.SOLUTION: A semiconductor device comprises: a substrate 12; a first element region and a second element region 11B provided on a first principal surface of the substrate 12; and a conductive layer 17 formed on a second principal surface at an opposite side to the first principal surface in the substrate 12. Here, the semiconductor device has a current path where a current flows in the first element region 11B, the inside of the substrate 12, the conductive layer 17, the inside of the substrate 12 and the second element region 11B in this order. The conductive layer 17 includes a metal 18 as a main material. A resin 19 is distributed and included in the metal 18.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a semiconductor device having a flip chip structure and a manufacturing method thereof.

  In recent years, with the progress of downsizing, thinning, lightening, and high performance of electronic devices, semiconductor devices have become a mainstream from a conventional package structure to a flip chip structure or a CSP (chip size package) structure. Yes. Under such circumstances, the transistor used for the DC-DC converter or the protection circuit of the lithium battery, in particular, the on-resistance of the transistor aimed at miniaturization, low profile and high performance by the flip chip structure. A small one is required.

  For example, as a semiconductor device on which a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is mounted, semiconductor devices on which flip chip mounting as shown in Patent Document 1 and Patent Document 2 are performed have been proposed.

  In such a MOSFET, as in the semiconductor device 100A shown in FIG. 8, for example, at least two transistor operation regions 102 and 104 are provided in the surface region of the first main surface of the semiconductor substrate 101, and the opposite side of the first main surface. A metal film 103 is provided on the second main surface. By adopting such a structure, the current path flowing from the first transistor operation region 102 to the second transistor operation region 104 does not flow in the semiconductor substrate in the horizontal direction (direction parallel to the surface of the semiconductor substrate). The current path 105 that flows in the vertical direction (thickness direction perpendicular to the surface of the semiconductor substrate) inside the substrate and flows in the metal film 103 on the second main surface can be used, and the on-resistance of the MOSFET can be reduced. is there.

JP 2008-056323 A JP2012-182238

  However, in the conventional structure described above, burrs are generated in the metal layer in the dicing process of cutting individual chips from the semiconductor substrate, which bites into the dicing sheet that is attached to the semiconductor substrate during dicing, and the adhesion between the chip and the dicing sheet is reduced. It will increase.

  As a result, in the pick-up process of picking up the singulated chips from the dicing sheet, pick-up mistakes that cannot be picked up frequently occur frequently, and the yield of the chips decreases.

  The present invention has been made in view of the above problems, and provides a highly reliable and high yield semiconductor device capable of suppressing the occurrence of burrs in a metal layer when chips are separated into pieces and a method for manufacturing the same. is there.

  In order to solve the above problems, a first semiconductor device of the present invention includes a substrate, a first element region and a second element region provided on a first main surface of the substrate, and the first element in the substrate. A conductive layer formed on the second main surface opposite to the main surface, and the first element region, the inside of the substrate, the conductive layer, the inside of the substrate and the second element region in this order. The conductive layer contains a metal as a main material, and a resin is dispersed and contained in the metal.

  In the first semiconductor device of the present invention, it is preferable that the side end face of the conductive layer and the side end face of the substrate are formed flush with each other.

  Moreover, the 1st semiconductor device of this invention WHEREIN: It is preferable that the fracture strain of the said conductive layer is smaller than the fracture strain of the said metal contained in the said conductive layer.

  In the first semiconductor device of the present invention, the conductive layer preferably has a breaking strain of 0 to 0.1.

  In the first semiconductor device of the present invention, the specific resistance of the conductive layer is preferably 2 to 100 μΩcm.

  In the first semiconductor device of the present invention, the metal is preferably at least one selected from Ag, Cu, Ni, Au, and Sn.

  In the first semiconductor device of the present invention, the resin is preferably at least one selected from an epoxy resin, an acrylic resin, a bismaleimide resin, and a silicone resin.

  The second semiconductor device of the present invention includes a substrate, a first element region and a second element region provided on the first main surface of the substrate, and a first element region on the substrate opposite to the first main surface. 2 having a conductive layer formed on the main surface, and having a current path through which current flows in this order through the first element region, the inside of the substrate, the conductive layer, the inside of the substrate, and the second element region. The conductive layer contains carbon nanotubes as a main material.

  In the first and second semiconductor devices of the present invention, it is preferable that a metal thin film is interposed between the substrate and the conductive layer.

  In the first and second semiconductor devices of the present invention, it is preferable that the metal thin film is a laminated film of a first metal thin film and a second metal thin film from a side close to the substrate.

  In the first and second semiconductor devices of the present invention, the conductive layer preferably has a thickness of 30 to 300 μm.

  According to the first method of manufacturing a semiconductor device of the present invention, the step (a) of preparing a semiconductor substrate in which a plurality of first element regions and a plurality of second element regions are formed on a first main surface; A step (b) of forming a conductive layer on the second main surface of the substrate opposite to the first main surface; and after the steps (a) and (b), each of the first main surface includes the first main surface. The semiconductor device comprising the step (c) of singulating the semiconductor substrate so that the one element region and the second element region are mounted and the conductive layer is provided on the second main surface. Each of the substrates has a current path through which the current flows in this order through the first element region, the inside of the substrate, the conductive layer, the inside of the substrate and the second element region, and the conductive layer is mainly made of metal. The resin is dispersed and contained in the metal.

  According to a second method of manufacturing the semiconductor device of the present invention, the step (a) of preparing a semiconductor substrate in which a plurality of first element regions and a plurality of second element regions are formed on a first main surface; A step (b) of forming a conductive layer on the second main surface of the substrate opposite to the first main surface; and after the steps (a) and (b), each of the first main surface includes the first main surface. The semiconductor device comprising the step (c) of singulating the semiconductor substrate so that the one element region and the second element region are mounted and the conductive layer is provided on the second main surface. Each of the substrates has a current path through which the current flows in this order through the first element region, the inside of the substrate, the conductive layer, the inside of the substrate, and the second element region, and the conductive layer mainly includes carbon nanotubes. Include as material.

  The first and second methods for manufacturing a semiconductor device of the present invention further include a step (d) of forming a metal thin film on the second main surface of the semiconductor substrate before the step (b). It is preferable.

  According to the semiconductor device and the manufacturing method thereof of the present invention, it is possible to provide a highly reliable and high-yield semiconductor device and a manufacturing method thereof that can suppress the occurrence of burrs in the metal layer when separated into chips.

1 is a plan view of a semiconductor device according to an embodiment of the present invention. It is principal part sectional drawing of the semiconductor device which concerns on embodiment of this invention. It is a fragmentary sectional enlarged view in principal part sectional drawing of the semiconductor device which concerns on embodiment of this invention. 1 is an equivalent circuit diagram of a semiconductor device according to an embodiment of the present invention. It is a schematic diagram which shows the resistance component of the semiconductor device which concerns on embodiment of this invention. It is process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is principal part sectional drawing of the semiconductor device which concerns on a prior art.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  An exemplary semiconductor device 10A according to an embodiment of the present invention will be described with reference to FIGS. Here, a “vertical” MOSFET will be described as an example, but it goes without saying that the same effect can also be obtained in a diode, a “vertical” bipolar transistor, or the like.

  FIG. 1 is a plan view showing the structure of a semiconductor device 10A according to the present embodiment, FIG. 2 is a cross-sectional view of the semiconductor device 10A shown in FIG. 1, taken along the line AA ', and FIG. 3 is an enlarged cross-sectional view of a portion P of the semiconductor device 10A shown in FIG.

As shown in FIGS. 1 and 2, a semiconductor device 10A according to the present embodiment includes, for example, a pair of MOSFETs, and an N ⁺ type semiconductor substrate in which an element region 11B is formed in a surface region of an N ⁻ type epitaxial layer 11A. An electrode 13 containing, for example, Al or Cu metal, and an external electrode 14 made of a lead-free material such as Sn—Ag—Cu formed on the electrode 13 are provided. Here, in the element region 11B, portions in the vicinity of the external electrodes 14 are examples of the “first element region” and the “second element region” in the present invention, respectively.

  A first metal thin film 15 that is in ohmic contact with the semiconductor substrate 12 is formed on the entire back surface of the semiconductor substrate 12. The first metal thin film 15 has Ti / Ni laminated in order from the side close to the back surface of the semiconductor substrate 12. This is mainly intended to ensure ohmic contact between the semiconductor substrate 12 and the first metal thin film 15, and other metals may be used as long as the metal can realize the purpose. For example, a laminated film such as Cr / NiCr / Ni may be used. In the present embodiment, the thickness of the first metal thin film 15 is, for example, Ti / Ni = 10 nm / 10 nm.

  Further, in the present embodiment, the second metal thin film 16 is formed on the first metal thin film 15. As the second metal thin film 16, Ag, Au, Cu or the like is mainly used. Preferably, the same metal as the metal contained in the conductive layer 17 to be formed later or a metal having high affinity with the metal is desirable. In the present embodiment, the thickness of the second metal thin film 16 is, for example, 10 nm to 1000 nm when Ag is used. If sufficient electrical characteristics (low on-resistance) can be obtained by the conductive layer 17 and the first metal thin film 15 to be formed later, it is not necessary to form the second metal thin film 16.

  A conductive layer 17 is formed on the second metal thin film 16 so as to be electrically connected thereto.

  As shown in FIG. 3, the main constituent of the conductive layer 17 is the conductor 18. For example, a metal made of Ag, Cu, Ni, Au, or Sn is preferable, but Ag is more preferable. Furthermore, the conductive layer 17 contains a thermosetting resin 19 made of, for example, epoxy as a binder in addition to the main conductor 18. The purpose of adding a binder is to reduce the breaking strain.

  In general, a material exhibits plastic deformation or ductility in the presence of breaking strain. The occurrence of ductility means that atoms undergo a slip transition in the crystal plane. For this reason, the larger the breaking strain, the more burrs are generated during dicing.

  Table 1 shows a result of comparison of fracture strains regarding Ag, Cu, Ni, Au metals, epoxy resin, and materials of the conductive layer 17 of the present embodiment.

  As is apparent from Table 1, the epoxy resin has an extremely low breaking strain as compared with the metal. That is, it can be seen that if an epoxy resin is added, the ductility can be reduced and the occurrence of burrs during dicing can be suppressed.

  Further, in the conductive layer 17, a thermosetting resin 19 made of an epoxy resin is uniformly dispersed as an additive of a different material in the main conductor 18, and an atomic transfer that causes ductility occurs between the different materials. As a result, the breaking strain is further reduced. Therefore, in the conductive layer 17 of the present embodiment, the breaking strain is a very low value of 0.005 to 0.01. As a practical level, the breaking strain may be 0 to 0.1, preferably 0 to 0.01.

  Further, if the conductive layer 17 contains a large amount of various metals, the specific resistance can be further reduced. Therefore, the conductive layer 17 becomes a main component based on the specific resistance that can realize desired electrical characteristics (on-resistance). What is necessary is just to determine a metal (conductor 18). Since it is well known that the resistance value decreases as the thickness of the conductive layer 17 increases, the thickness of the conductive layer 17 may be optimized.

  The conductor 18 is not limited to the above metal. For example, carbon nanotubes having a carbon structure having a low specific resistance are also useful. Since the carbon nanotube is a brittle material and the breaking strain is as close to 0 as possible, the generation of burrs during dicing can be further suppressed as compared with the conductive layer 17 using a metal as the conductor 18.

  FIG. 4 shows an equivalent circuit of the semiconductor device 10A. In the pair of MOSFETs illustrated in FIG. 4, as illustrated in FIG. 4, when the potential of the first source 20 is higher than that of the second source 21 in the pair of MOSFETs, When a predetermined voltage is applied to the gate 23 and both MOSFETs are turned on, a current flows in the A direction via the common drain 24.

  On the other hand, FIG. 5 shows a resistance component of the semiconductor device 10A. As shown in FIG. 5, the external electrode 14 has a resistor Rmetal 25 and the element region has a resistor Repi 26. In addition, a resistance Rsub 27 exists in the semiconductor substrate 12, and a resistance Rback 28 exists through the first metal thin film 15, the second metal thin film 16, and the conductive layer 17.

Here, Rsub 27 is determined by the thickness of the N-type layer formed immediately below the element region, that is, the thickness of the semiconductor substrate 12. This thickness becomes the main on-resistance when the circuit is used, and is a factor that determines power consumption. Therefore, in order to reduce power consumption, it is advantageous in terms of electrical characteristics to make the thickness of the semiconductor substrate 12 (N ⁺ type layer) as thin as possible.

  However, the thinner the semiconductor substrate 12 is, the lower the bending strength of the semiconductor substrate 12 is. It is known that the bending strength of the semiconductor substrate 12 decreases in inverse proportion to the square of the thickness. For example, when the thickness of the semiconductor substrate 12 is 80 μm, the bending strength is lower than when the thickness of the semiconductor substrate 12 is 100 μm. The bending strength is only 64%, and the bending strength is greatly reduced. Therefore, if the conductive layer 17 is formed thick in order to ensure the bending strength, the semiconductor substrate 12 can be reinforced. In reality, it is desirable that the conductive layer 17 has a thickness of about 30 to 300 μm.

  Further, the Rback 28 can be reduced by increasing the thickness of the conductive layer 17. Specifically, as the thickness of the semiconductor substrate 12 decreases, the ratio of the resistance component of the conductive layer 17 to the entire on-resistance of the semiconductor device 10A increases. Therefore, assuming that the variation of the specific resistance of the conductive layer 17 is 50%, the specific resistance of the conductive layer 17 is such that the ratio of the resistance component of the conductive layer 17 to the on-resistance of the entire semiconductor device 10A is 20% or less. It is desirable to determine. These on-resistance reduction measures can prevent the occurrence of burrs during dicing, enhance the bending strength of the semiconductor substrate 12, and simultaneously improve the electrical characteristics (on-resistance) of the semiconductor device 10A.

  Furthermore, the configuration of this embodiment is also useful in stress design. In the above description, the epoxy resin is used as the thermosetting resin 19 included in the conductive layer 17. However, for example, the semiconductor can be changed by changing to an acrylic resin, a bismaleimide resin, a silicone resin, or the like having a lower stress than the epoxy resin, or by mixing them. The warpage of the substrate 12 can be reduced, and problems during secondary mounting of the semiconductor device 10A can be prevented.

  In Patent Document 2 taken up in the prior art, the thickness of the semiconductor substrate is reduced to 100 μm, the thickness of the metal film is 20 μm, and the thickness of the insulating resin film is 50 μm in order to reduce the on-resistance of the transistor. In the manufacturing method disclosed in Document 2, since the insulating resin film is formed so as to cover the metal film after forming the metal film on the back surface of the semiconductor substrate formed into a book film, the metal film has a thickness of, for example, 20 μm. When formed, the semiconductor substrate is warped, and it is difficult to form an insulating resin film on the semiconductor substrate with a high yield, so that a so-called chip mounting defect occurs.

  However, in the configuration of the present embodiment, the conductive layer is insulated from the metal film as in Patent Document 2 because the thermosetting resin made of epoxy resin is uniformly dispersed as the additive of the different material in the main conductor. A resin film is not formed separately. Therefore, the warp that occurs in Patent Document 2 does not occur in the semiconductor substrate, and the manufacturing process can be shortened.

  Although not shown, an inorganic substance such as silica may be mixed in the conductive layer 17 in order to prevent clogging of the dicing blade. The mixing amount of silica is preferably 0.5% or more by weight with respect to the conductive layer 17. However, the specific resistance of the conductive layer 17 decreases as the silica content increases. The content of silica is preferably 0.5 to 2.0% by weight.

  In the prior art, due to clogging of the dicing blade, the first metal thin film and the second metal thin film are further ductile deformed without being cut, so that a great amount of stress is generated at the interface between the back surface of the semiconductor substrate 12 and the first metal thin film. And peeling occurred. When this peeling occurs, the current from the transistor cannot be sufficiently supplied, the on-resistance is increased, and an electrical characteristic defect occurs.

  However, in this embodiment, by mixing an inorganic substance such as silica into the conductive layer 17, clogging due to metal pieces generated on the dicing blade when the semiconductor substrate is diced can be removed with silica. Therefore, the chipping and excessive dicing of the dicing blade can be prevented, and the semiconductor device 10A can be provided at a high yield.

  Next, an exemplary method for manufacturing the semiconductor device 10A according to the embodiment of the present invention will be described with reference to FIGS. 6 (a) to 6 (c) and FIGS. 7 (a) to 7 (c). Here, a “vertical” MOSFET will be described as an example, but it goes without saying that the same effect can be obtained in a diode, a “vertical” bipolar transistor, or the like.

First, as shown in FIG. 6A, an N ⁻ type epitaxial layer 11A is formed on one main surface of a wafer 12 ′ made of a semiconductor substrate 12, and an element region 11B is formed on the surface region of the N ⁻ type epitaxial layer 11A. Form. Next, an electrode 13 made mainly of a metal such as Al or Cu is formed at a predetermined location on the element region 11B. At this time, it is desirable that the wafer thickness is back-ground to a desired thickness (preferably 100 μm or less) and further subjected to a mirror finish such as CMP so that the required electrical characteristics (on-resistance) can be realized.

  Next, as shown in FIG. 6B, the first metal thin film 15 is formed on the back surface of the wafer 12 ′ made of the semiconductor substrate 12 on the side opposite to the main surface so as to make ohmic contact with the semiconductor substrate 12. To do. Specifically, the first metal thin film 15 is formed on the entire back surface of the wafer 12 ′ by vapor deposition. Here, as the first metal thin film 15, for example, Ti / Ni is laminated in order from the side close to the back surface of the semiconductor substrate 12. The primary purpose of forming the first metal thin film 15 is to ensure ohmic contact with the semiconductor substrate 12 and is not limited to Ti / Ni as long as it is a metal that can achieve the desired purpose. For example, Cr / NiCr / Ni may be used. The film thickness of the first metal thin film 15 is, for example, Ti / Ni = 10 nm / 10 nm.

  Next, the second metal thin film 16 is formed on the first metal thin film 15. Specifically, it is formed by vapor deposition in the same manner as the first metal thin film 15. In this case, since the deposition can be performed in the same chamber as the first metal thin film 15, the number of switching steps can be reduced. Here, Ag, Au, Cu or the like is mainly used as the second metal thin film 16, but preferably the same metal as the metal contained in the conductive layer 17 formed on the second metal thin film 16, or A metal having a high affinity for this metal is desirable.

  However, if the conductive layer 17 and the first metal thin film 15 can provide a sufficiently low on-resistance, the second metal thin film 16 may not be formed.

  Next, as shown in FIG. 6C, a liquid conductive layer 17 ′ before thermosetting is formed on the second metal layer 16 (or the first metal thin film 15 when the second metal thin film 16 is not required). To do. Here, the liquid conductive layer 17 includes a metal filler mainly composed of, for example, Ag, Cu, Ni, Au, or Sn (preferably Ag). The size of the metal filler is 1 nm to 10 μm, preferably 1 nm to 1 μm. However, the present invention is not limited to the above metal, and for example, wire-like CNT (carbon nanotube) may be used.

  The liquid conductive layer 17 ′ includes a thermosetting resin 19 made of, for example, epoxy, acrylic resin or bismaleimide resin as a binder, and preferably further contains, for example, an amine-based curing accelerator. The conductive layer 17 contains a solvent for uniformly dispersing the metal filler.

  Although not shown, an inorganic substance such as silica may be mixed in the liquid conductive layer 17 ′. The mixing amount of silica is preferably 0.5% or more by weight with respect to the liquid conductive layer 17 ′. However, the specific resistance of the liquid conductive layer 17 ′ decreases as the silica content increases. The content of silica is preferably 0.5 to 2.0% by weight.

  As a specific method for forming the liquid conductive layer 17 ′ before thermosetting, as shown in FIG. 6C, for example, the liquid conductive layer 17 ′ before thermosetting formed on the wafer 12 ′ is printed. Using a method or the like, the squeegee 29 is used to prepare a uniform thickness. At this time, the liquid conductive layer 17 ′ is formed to have a film thickness of, for example, 30 to 300 μm so as to have a specific resistance (for example, 2 to 100 μΩcm) that can obtain a desired on-resistance.

  Next, as shown in FIG. 7A, the liquid conductive layer 17 ′ formed on the wafer 12 ′ is cured. For example, it is desirable to cure using a curing method or the like. The cured conductive layer 17 has, for example, a breaking strain of 0 to 0.1 (preferably 0 to 0.01). Further, when baking is performed while pressing (preferably 10 Pa or more) with a highly water-repellent member 30 such as Teflon (registered trademark), the high-quality conductive layer 17 with few bubbles and low specific resistance can be obtained. Can be obtained.

  Next, as shown in FIG. 7B, the electrode 13 is electrically connected to the electrode 13 using a solder ball mounting method, a solder paste printing method, or an electrolytic plating method using a flux, for example, Sn-Ag. The external electrode 14 made of a lead-free solder material having a Cu composition is formed.

  Finally, as shown in FIG. 7C, the wafer-like semiconductor substrate 12 ′ is diced into a plurality of semiconductor substrates 12 using a dicing blade 31 such as a dicing saw, for example. At this time, as shown in Table 1, since the breaking strain of the conductive layer 17 is extremely lower than various metals, the generation of metal burrs can be prevented. Moreover, clogging of the dicing blade 31 during dicing can be suppressed.

  In the present embodiment, the “vertical” MOSFET has been described as an example. However, the present invention is not limited to this. For example, the structure described above can be applied to a bipolar transistor. In this case as well, the effects described above can be realized, such as the generation of burrs in the conductive layer 17 can be prevented.

  Further, as another example, in the case of a PN diode and an NP diode, each effect described above can be realized by forming the conductive layer 17 in the common cathode layer of the pair of anode layer and cathode layer. It can also be applied to various other “vertical” elements.

  The semiconductor device and the manufacturing method thereof according to the present invention can realize low power consumption and downsizing due to reduction of on-resistance, and can be particularly applied to CSP and the like to reduce the size, weight and performance of various electronic devices. Can contribute.

10A Semiconductor device 11A Epitaxial layer 11B Element region 12 Semiconductor substrate (chip shape)
12 'Semiconductor substrate (wafer shape)
13 Electrode 14 External electrode 15 First metal thin film 16 Second metal thin film 17 Conductive layer (after thermosetting)
17 'conductive layer (before thermosetting)
18 Conductor 19 Resin 20 First Source 21 Second Source 22 First Gate 23 Second Gate 24 Common Drain 25 Rmetal
26 Repi
27 Rsub
28 Rback
29 Squeegee 30 Member 31 Dicing Blade 100A Semiconductor Device 101 Semiconductor Substrate 102 First Transistor Region 103 Metal Film 104 Second Transistor Region 105 Current Path

Claims (14)

A substrate,
A first element region and a second element region provided on the first main surface of the substrate;
A conductive layer formed on a second main surface opposite to the first main surface of the substrate;
A current path through which current flows through the first element region, the inside of the substrate, the conductive layer, the inside of the substrate, and the second element region in this order;
The conductive layer includes a metal as a main material, and a semiconductor device in which a resin is dispersed in the metal.   The semiconductor device according to claim 1, wherein a side end surface of the conductive layer and a side end surface of the substrate are formed flush with each other. The semiconductor device according to claim 1, wherein a breaking strain of the conductive layer is smaller than a breaking strain of the metal contained in the conductive layer.   The semiconductor device according to claim 1, wherein the breaking strain of the conductive layer is 0 to 0.1.  5. The semiconductor device according to claim 1, wherein a specific resistance of the conductive layer is 2 to 100 μΩcm.  The semiconductor device according to claim 1, wherein the metal is at least one selected from Ag, Cu, Ni, Au, and Sn.   The semiconductor device according to claim 1, wherein the resin is at least one selected from an epoxy resin, an acrylic resin, a bismaleimide resin, and a silicone resin. A substrate,
A first element region and a second element region provided on the first main surface of the substrate;
A conductive layer formed on a second main surface opposite to the first main surface of the substrate;
A current path through which current flows through the first element region, the inside of the substrate, the conductive layer, the inside of the substrate, and the second element region in this order;
The conductive layer is a semiconductor device containing carbon nanotubes as a main material.   The semiconductor device according to claim 1, wherein a metal thin film is interposed between the substrate and the conductive layer.   The semiconductor device according to claim 9, wherein the metal thin film is a stacked film of a first metal thin film and a second metal thin film from a side close to the substrate.  The semiconductor device according to claim 1, wherein the conductive layer has a thickness of 30 to 300 μm. Preparing a semiconductor substrate in which a plurality of first element regions and a plurality of second element regions are formed on a first main surface;
Forming a conductive layer on the second main surface opposite to the first main surface of the semiconductor substrate (b);
After each of the steps (a) and (b), the first element region and the second element region are mounted on the first main surface and the conductive layer is provided on the second main surface. A step (c) of separating the semiconductor substrate into pieces;
Each of the separated semiconductor substrates has a current path through which the current flows in this order through the first element region, the inside of the substrate, the conductive layer, the inside of the substrate, and the second element region,
The method for manufacturing a semiconductor device, wherein the conductive layer includes a metal as a main material, and a resin is dispersed and included in the metal. Preparing a semiconductor substrate in which a plurality of first element regions and a plurality of second element regions are formed on a first main surface;
Forming a conductive layer on the second main surface opposite to the first main surface of the semiconductor substrate (b);
After each of the steps (a) and (b), the first element region and the second element region are mounted on the first main surface and the conductive layer is provided on the second main surface. A step (c) of separating the semiconductor substrate into pieces;
Each of the separated semiconductor substrates has a current path through which the current flows in this order through the first element region, the inside of the substrate, the conductive layer, the inside of the substrate, and the second element region,
The method for manufacturing a semiconductor device, wherein the conductive layer includes carbon nanotubes as a main material.   The method for manufacturing a semiconductor device according to claim 12, further comprising a step (d) of forming a metal thin film on the second main surface of the semiconductor substrate before the step (b).

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