JP2006237261A - Mosfet - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To effectively prevent generation of a self-turn-on phenomenon in a MOSFET mainly used as a power device. <P>SOLUTION: The MOSFET comprises a first MOSFET 10 including a semiconductor substrate where the cross-sectional structure perpendicular to a first horizontal direction A-Aa is almost constant without relation to the position in the first horizontal direction, and a second MOSFET 20 formed on the semiconductor substrate at the outside of edge in the first horizontal direction of the first MOSFET 10 to include respective regions of a drain region, channel region, and source region adjacent to the first horizontal direction. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a MOSFET (metal oxide semiconductor field effect transistor) mainly used for power applications, and more particularly to a MOSFET having a structure suitable for preventing the occurrence of a self-turn-on phenomenon.

  As the power supply voltage to a semiconductor device typified by a CPU such as a computer is lowered, a synchronous rectification DC-DC converter is frequently used as a power supply device. The synchronous rectification DC-DC converter has a structure in which an input (primary side) voltage is applied to a series-connected MOSFET and an intermediate point thereof is connected to a low-pass filter including an inductor and a capacitor. The MOSFETs connected in series are switched so that the on periods of the high-side and low-side MOSFETs are exclusive.

  In such a type of power supply, the voltage change rate at the intermediate point increases as the switching frequency becomes higher. When a high-frequency current due to this voltage change rate flows from the drain to the gate of the low-side MOSFET due to parasitic capacitance, the gate is connected to the gate even during a period when a low voltage for turning off the channel is supplied to the gate. A voltage is generated due to the parasitic inductance and resistance of the wiring. This may turn on the low-side MOSFET (self-turn-on phenomenon). When such a phenomenon occurs, the input voltage is short-circuited by the two MOSFETs, so that the power conversion efficiency (output power / input power) deteriorates.

In order to prevent this, it is necessary to make the parasitic inductance and resistance of the wiring to the gate smaller than before. Note that power-use MOSFETs include structures disclosed in, for example, Patent Documents 1 to 3 below, but none of them intends to reduce the parasitic inductance or resistance of the wiring to the gate.
Japanese National Patent Publication No. 11-506267 Japanese Patent Laid-Open No. 9-213956 JP-A-8-279613

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a MOSFET capable of effectively preventing the occurrence of a self-turn-on phenomenon in a MOSFET mainly used for power applications. To do.

  A MOSFET according to one embodiment of the present invention includes a semiconductor substrate, and a cross-sectional structure perpendicular to the first horizontal direction is substantially constant regardless of the position in the first horizontal direction, and the cross-sectional structure is A first MOSFET portion having a constant repetitive pattern in a second horizontal direction perpendicular to the first horizontal direction, and the semiconductor substrate on the semiconductor substrate outside the first horizontal end portion of the first MOSFET portion; And a second MOSFET portion having a drain region, a channel region, and a source region adjacent to each other in the first horizontal direction.

  According to the MOSFET of the present invention, it is possible to effectively prevent the occurrence of the self-turn-on phenomenon in a MOSFET mainly used for power.

  According to the MOSFET of one embodiment of the present invention, the gate after the first MOSFET portion is switched to the off state is connected between the source and drain of the second MOSFET portion on the same substrate as the first MOSFET portion. It can be fixed at a constant voltage using the ON state of. That is, it is possible to generate a gate voltage when the first MOSFET portion is off, which is not affected by the parasitic inductance or resistance of the wiring to the gate of the first MOSFET portion. Therefore, the occurrence of the self turn-on phenomenon can be effectively prevented.

  As an embodiment of the present invention, the first MOSFET section may have a plurality of trench-type gate electrodes with the constant repeating pattern. This is a configuration in the case of a so-called trench MOSFET. Here, a part of the plurality of trench-type gate electrodes is electrically connected to a source electrode included in the first MOSFET portion, and at least a part of the semiconductor region facing the part of the trench-type gate electrodes is formed. A metal layer that has the same conductivity type as that of the semiconductor substrate in the vertical direction, is formed on the upper surface of at least a part of the semiconductor region, and is electrically conductive to the source electrode of the first MOSFET portion. It may be provided. This is a configuration in which a Schottky diode serving as a flywheel diode is built in parallel between the source and drain of the first MOSFET section.

  As an embodiment, the first MOSFET section may have a plurality of planar base regions with the constant repeating pattern. This is a configuration in the case of a so-called planar type MOSFET.

  As an embodiment, the first MOSFET portion may include a vertical MOSFET. The vertical MOSFET is suitable for power applications because the arrangement of the source electrode and the drain electrode opposes in the vertical direction and the resistance of the current path becomes smaller.

  As an embodiment, the semiconductor substrate may be an N-type semiconductor. This is a configuration when the first MOSFET portion is an n-channel MOSFET. Of course, the semiconductor substrate may be a P-type semiconductor and the first MOSFET portion may be a p-channel MOSFET.

  As an embodiment, the second MOSFET portion may be an arrangement of the drain region, the channel region, and the source region from the side closer to the first MOSFET portion. When the drain region of the second MOSFET part is arranged close to the first MOSFET part, the electrical connection between the gate of the first MOSFET part and the drain region of the second MOSFET part becomes the shortest in the layout. With this connection, the gate after the first MOSFET portion is switched to the off state can be fixed to a constant voltage by utilizing the on state between the source and drain of the second MOSFET portion.

  Alternatively, the drain region, the channel region, the source region, the channel region,... May be arranged in the second direction in place of the above-described regions. In this case, the source region of the first MOSFET part and the source region of the second MOSFET part can be easily electrically connected on the semiconductor structure.

  Further, as an embodiment, the second horizontal width of the drain region, the channel region, and the source region of the second MOSFET portion is the same as the constant repetition pattern of the first MOSFET portion, respectively. The width between both ends may be substantially the same. In this configuration, the size (width) of the second MOSFET portion is made as large as possible.

  Based on the above, embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a plan view schematically showing a schematic configuration of a MOSFET according to an embodiment of the present invention. This figure shows the arrangement of each region at a certain depth. The structures of cross sections A-Aa and B-Ba in the figure will be described later.

As shown in FIG. 1, the MOSFET 1 includes a first MOSFET portion 10 and a second MOSFET portion 20. In the first MOSFET section 10, a gate electrode layer 11 (illustrated by a dot pattern), a source layer 12 (illustrated by a cross hatch pattern), and a base contact layer 13 (illustrated by a grid pattern) are disposed. Although the outermost portion of the gate electrode layer 11 is not shown, it is covered with a gate insulating film. The source layer 12 is an N ⁺ semiconductor layer, the base contact layer 13 is a P ⁺ semiconductor layer, and the gate electrode layer 11 is a layer of polycrystalline silicon having high conductivity, for example.

A plurality of gate contacts 114 are provided in the vicinity of one end in the vertical direction in the figure of the first MOSFET portion 10 so as to be electrically connected to the outside or the like. Further, the second MOSFET portion 20 adjacent to the end portion of the MOSFET portion 10 includes a drain layer 21 (illustrated by a cross hatch pattern), a channel region (below the gate electrode layer 22), and a source layer 23 (cross). (Shown in a hatch pattern). The drain layer 21 and the source layer 23 are N ⁺ semiconductor layers, and the channel region is a P-type semiconductor layer. The drain layer 21 can be electrically connected to the outside and the gate contact 114 of the first MOSFET section 10 by a plurality of drain contacts 24 and the like. The source layer 23 can be electrically connected to the outside by a plurality of source contacts 25 and the like. Thereby, the source layer 23 can be electrically connected to the source layer 12 of the first MOSFET section 10.

  FIG. 2 is a schematic cross-sectional view in the arrow direction of the position A-Aa shown in FIG. In FIG. 2, the same parts as those shown in FIG. 1 are denoted by the same reference numerals. As shown in the figure, the first MOSFET portion 10 has a cross-sectional structure having a constant repeating pattern in the A-Aa direction. The gate electrode layer 11 is a so-called trench type, and the outermost part is covered with a gate insulating film 14. In the overall vertical direction, the drain electrode layer 19, the semiconductor substrate 18, the N-type semiconductor layer 17, and the base layer (body region) 16 are provided from the bottom, and the source layer 12 is selectively formed on the base layer 16. A base contact layer 13 is formed. The semiconductor substrate 18 is N-type and has a higher impurity concentration than the N-type semiconductor layer 17. The N-type semiconductor layer 17 can be formed on the semiconductor substrate 18 by epitaxial growth, for example. The base layer 16 is a P-type semiconductor layer.

  The trench-type gate electrode layer 11 has a depth to reach the N-type semiconductor layer 17, and the opposing base layer 16 region becomes a channel region by this depth formation. The source layer 12 formed on the upper side of the base layer 16 is adjacent to the gate electrode layer 11 through the gate insulating film 14. A source electrode layer 15 may be provided on the source layer 12 and the base contact layer 13 via a top metal (not shown). The source electrode layer 15 and the drain electrode layer 19 are disposed to face each other with the semiconductor substrate 18 interposed therebetween, so that the first MOSFET unit 10 is a vertical MOSFET.

  FIG. 3 is a schematic cross-sectional view in the arrow direction of the B-Ba position shown in FIG. In FIG. 3, parts that are the same as those already described are denoted by the same reference numerals. As shown in FIG. 3, the drain layer 21 and the source layer 23 are selectively formed on the surface of the region of the base layer 16. A drain electrode layer 27 may be formed on the drain layer 21 via a top metal (not shown), and a source electrode layer 28 may be formed on the source layer 28 via a top metal (not shown). A gate electrode layer 22 may be formed on a slightly wider region including between the drain layer 21 and the source layer 23 via a gate insulating film 26.

  The lengths of the drain layer 21, the gate electrode layer 22, and the source layer 23 in the A-Aa direction can be the same as the length between both ends of the repetitive pattern in the cross section of the first MOSFET unit 10. . Alternatively, the second MOSFET unit 20 may be formed so that a plurality of parallel MOSFET elements are arranged in the A-Aa direction.

  FIG. 4 is a plan view schematically showing the upper surface of MOSFET 1 shown in FIG. In FIG. 4, the same parts as those already described in FIG. The source electrode 41 is an electrode wiring that is electrically connected to the source electrode layer 15 (FIG. 2) via the source contact 42. A plurality of bumps 43 are formed on the source electrode 41 and can be mounted on the substrate via the bumps 43.

  The gate electrode 44 is electrically connected to the gate electrode layer 11 (FIG. 1) via the gate contact 114 and electrically connected to the drain electrode layer 27 (FIG. 3) via the drain contact 24 (conductive region). ). A plurality of bumps 45 are formed on the gate electrode 44 and can be mounted on a substrate via the bumps 45. As described above, in this embodiment, the gate electrode 44 electrically connects the gate of the first MOSFET unit 10 and the drain of the second MOSFET unit 20. On the other hand, although the preference is somewhat inferior, it is also conceivable to individually connect to the substrate and make electrical connection on the substrate. In this case, the gate wiring of the first MOSFET section 10 and the drain wiring of the second MOSFET section 20 may be formed as separate wiring layers.

  The second gate electrode 46 in FIG. 4 is an electrode wiring that is electrically connected to the gate electrode layer 22 (FIG. 3). A plurality of bumps 47 are formed on the second gate electrode 46 and can be mounted on the substrate via the bumps 47. The second source electrode 48 is an electrode wiring that is electrically connected to the source electrode layer 28 (FIG. 3) via the source contact 25. A plurality of bumps 49 are formed on the second source electrode 48 and can be mounted on the substrate via the bumps 49. Mounting on the substrate via the bumps 43, 45, 47, and 49 enables mounting with lower resistance and lower inductance than when a bonding wire is used.

  FIG. 5 is an equivalent circuit diagram of the MOSFET 1 described with reference to FIGS. As shown in FIG. 5, the MOSFET 1 has a second MOSFET portion 20 attached to the first MOSFET portion 10, and the gate of the first MOSFET portion 10 and the drain of the second MOSFET portion 20 are Conductive (by gate electrode 44 (FIG. 4)). The reference numerals in parentheses attached to the terminals in FIG. 5 correspond to the reference numerals in FIG.

  FIG. 6 is an exemplary circuit diagram when the MOSFET 1 according to the embodiment of the present invention is applied to a DC-DC converter. In FIG. 6, the upper MOSFET 71 and the first MOSFET portion 10 of the lower MOSFET 1 are controlled so as not to be turned on at least simultaneously (by the driver 60 described below). As a result, the intermediate connection point conducts to the original voltage (primary side voltage) or the ground. Therefore, the connection point is connected to the output terminal 75 via the low-pass filter formed by the inductor 73 and the capacitor 74. The intermediate voltage can be generated as an output voltage (secondary voltage) at the output terminal 75. The maximum current that can be output from the output terminal 75 is, for example, 10A. Thus, since the output current value is large, the MOSFET 71 and the MOSFET 1 are discrete components different from the driver 60.

  The diode 72 connected in parallel between the source and drain of the first MOSFET section 10 is a flywheel diode. The gate of the upper MOSFET 71 and the gate of the first MOSFET section 10 of the lower MOSFET 1 are connected to and controlled by a driver 60 as shown. The output of the inverter composed of the pMOSFET 61 and the nMOSFET 62 included in the driver 60 is connected to the gate of the upper MOSFET 71. The MOSFET 71 is on when the inverter output is high level, and the MOSFET 71 is off when the inverter output is low level.

  The drain of the pMOSFET 63 included in the driver 60 is connected to the gate of the first MOSFET section 10 of the lower MOSFET 1. Further, the second gate of the lower MOSFET 1 is connected so that the same signal as that applied to the gate of the pMOSFET 63 is supplied. When the drain output of the pMOSFET 63 is at a high level, the first MOSFET section 10 is turned on. When the drain output is not at a high level, the gate of the pMOSFET 63 is at a high level, so that the second MOSFET section 20 of the MOSFET 1 is turned on. Therefore, the first MOSFET portion 10 is turned off. Further, the source of the first MOSFET part 10 and the source of the second MOSFET part 20 are commonly connected to the ground.

  As can be seen from the above description, in the driver 60, a predetermined control signal is applied so that the input side c1 of the inverter composed of the pMOSFET 61 and the nMOSFET 62 and the gate c2 of the pMOSFET 63 do not go low at the same time. The frequency of this control signal is 1 MHz, for example. In driving at such a high frequency, the connection from the driver 60 to the MOSFET 71 and the MOSFET 1 becomes a parasitic inductor, and the inductance cannot be ignored.

  For example, considering the case where the second MOSFET portion 20 of the MOSFET 1 is on the driver 60 side, the voltage change rate of the drain voltage of the MOSFET portion 10 at the timing when the MOSFET portion 10 is turned off by turning on the MOSFET portion 20. The high frequency current flowing due to the parasitic capacitance between the drain and source becomes a problem due to the large current. This current generates a voltage at the gate due to a parasitic inductance of a wiring (including a bonding wire when a bonding wire is used) connected to the gate of the MOSFET 10 part. With this voltage, the MOSFET section 10 is turned on at a timing that should be originally turned off. This is a so-called self turn-on phenomenon.

  As shown in FIG. 6, when the MOSFET unit 20 exists on the side of the MOSFET unit 10, the MOSFET unit 20 is turned on even if a high-frequency current flows between the drain and the gate of the MOSFET unit 10. In this case, the MOSFET unit 20 fixes the ground level. Therefore, even if there is a parasitic inductance or resistance in the connection wiring from the drain of the pMOSFET 63 to the gate of the MOSFET unit 10, the MOSFET unit 10 is not turned on unnecessarily. That is, a current path penetrating through the MOSFET 71 and the MOSFET section 10 is not generated, so that a loss due to power conversion is reduced and a highly efficient DC-DC converter is obtained.

  Next, a MOSFET according to another embodiment of the present invention will be described with reference to FIG. FIG. 7 is a cross-sectional view (corresponding to the position A-Aa in FIG. 2) showing a schematic configuration of a MOSFET according to another embodiment of the present invention. In FIG. 7, parts that are the same as or equivalent to the parts in the drawings already described are given the same reference numerals. The description of the part is omitted unless there is an additional matter.

  In this embodiment, a so-called planar type MOSFET is formed as the first MOSFET section 10. Accordingly, a planar base layer 16a is provided instead of the base layer 16, and the source layer 12 and the base contact layer 13 are selectively formed on the surface of the planar base layer 16a. The source electrode layer 15 is formed on the base contact layer 13 and part of the source layer 12. The stacked layer of the gate insulating film 14 and the gate electrode layer 11 is formed so as to extend on the adjacent source layer 12 with the N-type semiconductor layer 17 exposed as a center. A region of the base layer 16a facing the gate electrode 11 through the gate electrode layer 11 is a channel.

  The first MOSFET portion according to this embodiment is also the same as the above-described embodiment in that it has a cross-sectional structure of a repetitive pattern as shown in the A1-A1a direction. This structure has an advantage that it can be manufactured more easily than the structure shown in FIG.

  Next, a MOSFET according to still another embodiment of the present invention will be described with reference to FIG. FIG. 8 is a cross-sectional view showing a schematic configuration of a MOSFET according to still another embodiment of the present invention. In FIG. 8, parts that are the same as or equivalent to the parts in the already described figures are given the same reference numerals. The description of the part is omitted unless there is an additional matter.

  In this embodiment, the flywheel diode 72 shown in FIG. 6 is built in the MOSFET 1, and a part of the structure shown in FIG. 2 is modified to a diode (Schottky diode). Specifically, as shown in FIG. 8, a part of the plurality of trench-type gate electrode layers 11 is electrically connected to the source electrode layer 15 included in the first MOSFET unit 10. At least a part of the semiconductor region facing the gate electrode layer 11 has the same conductivity type as that of the semiconductor substrate 18 in the vertical direction. Then, a metal layer 81 is formed on the upper surface of at least a part of the semiconductor region, and the metal layer 81 is conducted to the source electrode layer 15 included in the first MOSFET unit 10.

  With the above structure, a diode is formed by using a Schottky barrier generated between the metal layer 81 and the N-type semiconductor layer 17 in contact therewith. The metal layer 81 side is an anode. According to such a structure, the flywheel diode 72 as the discrete component shown in FIG.

  Next, a MOSFET according to still another embodiment of the present invention will be described with reference to FIG. FIG. 9 is a plan view schematically showing a schematic configuration of a MOSFET according to still another embodiment of the present invention. In FIG. 9, parts that are the same as or equivalent to the parts in the already described figures are given the same reference numerals. The description of the part is omitted unless there is an additional matter.

  In this embodiment, the arrangement of each region in the second MOSFET unit 20 is different from that in each of the above embodiments. That is, the drain layer 21, the channel region (located below the gate electrode layer 22), the source layer 23, the channel region (same),... Are arranged in the A-Aa direction. As a result, the channel formation direction is the A-Aa direction, and the above embodiments are different from the channel formation in the B-Ba direction. With such an arrangement, both sources of the first and second MOSFET portions 10 and 20 can be easily electrically connected by forming a conductive region on the semiconductor device. That is, as can be seen from FIG. 9, the conductive region connecting the source contact 25 in the source layer 23 of the second MOSFET part 20 to the source electrode layer 15 (FIG. 2) of the first MOSFET part It can be formed without intersecting the conductive region.

  FIG. 10 is an equivalent circuit diagram of the MOSFET shown in FIG. The reference numerals in parentheses attached to each terminal in FIG. 10 correspond to the reference numerals in FIG. 9 or FIG. That is, the gate contact 114 and the drain contact 24 are electrically connected by the conductive region and become the same node, and the terminal G and the source contact 42 (FIG. 4) and the source contact 25 are electrically connected by the conductive region and become the same node. Each terminal of the terminal S and the terminal G2 where the plurality of gate contacts 91 become the same node due to the conductive region and exit to the outside can be formed on the side of the surface shown in FIG. This point is an advantage that cannot be obtained in each of the above-described embodiments, as can be seen in comparison with FIGS. 4 and 5. The removal effect of the self turn-on phenomenon is the same.

  In the above description of the embodiment, the first MOSFET portion 10 and the second MOSFET portion 20 are both N-channel MOSFETs having an N-type semiconductor substrate, but of course, P-channel MOSFETs having a P-type semiconductor substrate. It is also possible to configure as.

The top view which shows typically schematic structure of MOSFET which concerns on one Embodiment of this invention. FIG. 2 is a schematic cross-sectional view in the direction of arrow A-Aa shown in FIG. 1. FIG. 2 is a schematic cross-sectional view taken along the arrow B-Ba shown in FIG. 1. The top view which shows typically the upper surface of MOSFET shown in FIG. FIG. 5 is an equivalent circuit diagram of the MOSFET shown in FIGS. 1 to 4. 1 is an exemplary circuit diagram in a case where a MOSFET according to an embodiment of the present invention is applied to a DC-DC converter. Sectional drawing which shows schematic structure of MOSFET which concerns on another embodiment of this invention (A-Aa position equivalent in FIG. 2). Sectional drawing which shows schematic structure of MOSFET which concerns on another embodiment of this invention. The top view which shows typically schematic structure of MOSFET which concerns on another embodiment by this invention. FIG. 10 is an equivalent circuit diagram of the MOSFET shown by FIG. 9.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... MOSFET, 10 ... 1st MOSFET part, 11 ... Gate electrode layer, 12 ... Source layer, 13 ... Base contact layer, 14 ... Gate insulating film, 15 ... Source electrode layer, 16 ... Base layer (body region), 16a ... Planar type base layer, 17 ... N type semiconductor layer, 18 ... Semiconductor substrate, 19 ... Drain electrode layer, 20 ... Second MOSFET part, 21 ... Drain layer, 22 ... Gate electrode layer, 23 ... Source layer, 24 ...... drain contact, 25 ... source contact, 26 ... gate insulating film, 27 ... drain electrode layer, 28 ... source electrode layer, 41 ... source electrode, 42 ... source contact, 43 ... bump, 44 ... gate electrode, 45 ... bump, 46 ... Second gate electrode, 47 ... Bump, 48 ... Second source electrode, 49 ... Bump, 60 ... Driver, 61 ... pMOSFET, 62 ... n OSFET, 63 ... pMOSFET, 71 ... MOSFET, 72 ... flywheel diode 73 ... Inductor, 74 ... capacitor, 75 ... output terminal, 81 ... metal layer, 91 ... gate contact 114 ... gate contact.

Claims (5)

A second cross-sectional structure that is accompanied by a semiconductor substrate and that is perpendicular to the first horizontal direction is substantially constant regardless of the position in the first horizontal direction, and that the cross-sectional structure is perpendicular to the first horizontal direction. A first MOSFET portion having a constant repeating pattern in the horizontal direction of
The first MOSFET portion is formed on the semiconductor substrate outside the first horizontal end portion, and has a drain region, a channel region, and a source region adjacent to the first horizontal direction. A MOSFET comprising: 2 MOSFET parts.   2. The MOSFET according to claim 1, further comprising a conductive region that electrically connects a region functioning as a gate of the first MOSFET portion and the drain region of the second MOSFET portion.   2. The MOSFET according to claim 1, wherein the first MOSFET section has a plurality of trench-type gate electrodes according to the fixed repeating pattern.   2. The MOSFET according to claim 1, wherein the first MOSFET section includes a vertical MOSFET. A part of the plurality of trench-type gate electrodes is electrically connected to a source electrode included in the first MOSFET portion;
At least a part of the semiconductor region facing the part of the trench-type gate electrode has the same conductivity type as the semiconductor substrate in the vertical direction,
4. The MOSFET according to claim 3, further comprising a metal layer formed on an upper surface of at least a part of the semiconductor region and electrically connected to the source electrode of the first MOSFET portion.

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